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| author | Gabe Black <gabeblack@google.com> | 2019-10-21 11:43:53 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-23 22:36:20 +0000 |
| commit | cc614875540016b53f0bb4d5c119c7e1af159e6e (patch) | |
| tree | 0f3f3d351882d499031c9487fcdeab24fc7cb847 | |
| parent | 239054f48439c18b93e1a70ff29dbcb0c4742cff (diff) | |
| download | gem5-cc614875540016b53f0bb4d5c119c7e1af159e6e.tar.xz | |
cpu: Apply the ARM TLB rework to the O3 checker CPU.
The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU and SimpleCPU checker already, but the TLBs
are added in the O3 checker CPU as well.
Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 4a994f07f..89744e98a 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -181,14 +181,14 @@ class DerivO3CPU(BaseCPU): def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmTLB import ArmTLB + from m5.objects.ArmTLB import ArmDTB, ArmITB self.checker = O3Checker(workload=self.workload, exitOnError=False, updateOnError=True, warnOnlyOnLoadError=True) - self.checker.itb = ArmTLB(size = self.itb.size) - self.checker.dtb = ArmTLB(size = self.dtb.size) + self.checker.itb = ArmITB(size = self.itb.size) + self.checker.dtb = ArmDTB(size = self.dtb.size) self.checker.cpu_id = self.cpu_id else: |