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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-17 18:49:22 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-17 18:49:22 -0700 |
commit | d85cd08113e61817fdf1df978f2713ba8b094996 (patch) | |
tree | 6159f9514ac84a4ff0792b346422b03d16052dc0 | |
parent | 7b6587fc9cbd5e7e7930abbc5c6e2683e527f629 (diff) | |
download | gem5-d85cd08113e61817fdf1df978f2713ba8b094996.tar.xz |
X86: Set up a named constant for the "fold bit" for int register indices.
-rw-r--r-- | src/arch/x86/insts/microregop.cc | 2 | ||||
-rw-r--r-- | src/arch/x86/insts/static_inst.cc | 4 | ||||
-rw-r--r-- | src/arch/x86/insts/static_inst.hh | 6 | ||||
-rw-r--r-- | src/arch/x86/intregs.hh | 3 | ||||
-rw-r--r-- | src/arch/x86/isa.hh | 2 |
5 files changed, 10 insertions, 7 deletions
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index 2ea975746..2edd3ba87 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -67,7 +67,7 @@ namespace X86ISA bool subtract) const { DPRINTF(X86, "flagMask = %#x\n", flagMask); - if (_destRegIdx[0] & (1 << 6)) { + if (_destRegIdx[0] & IntFoldBit) { _dest >>= 8; } uint64_t flags = oldFlags & ~flagMask; diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index 0820a47d4..4f48c4c59 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -149,8 +149,8 @@ namespace X86ISA if (reg < FP_Base_DepTag) { const char * suffix = ""; - bool fold = reg & (1 << 6); - reg &= ~(1 << 6); + bool fold = reg & IntFoldBit; + reg &= ~IntFoldBit; if(fold) suffix = "h"; diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index 4ca7a4984..32065f7c0 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -108,7 +108,7 @@ namespace X86ISA inline uint64_t merge(uint64_t into, uint64_t val, int size) const { X86IntReg reg = into; - if(_destRegIdx[0] & (1 << 6)) + if(_destRegIdx[0] & IntFoldBit) { reg.H = val; return reg; @@ -139,7 +139,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if(_srcRegIdx[idx] & (1 << 6)) + if(_srcRegIdx[idx] & IntFoldBit) return reg.H; switch(size) { @@ -160,7 +160,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if(_srcRegIdx[idx] & (1 << 6)) + if(_srcRegIdx[idx] & IntFoldBit) return reg.SH; switch(size) { diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index 627d7062f..2c6d871ed 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -167,6 +167,9 @@ namespace X86ISA NUM_INTREGS }; + // This needs to be large enough to miss all the other bits of an index. + static const IntRegIndex IntFoldBit = (IntRegIndex)(1 << 6); + inline static IntRegIndex INTREG_MICRO(int index) { diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 8d3b110c6..9a1880062 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -69,7 +69,7 @@ namespace X86ISA int flattenIntIndex(int reg) { - return reg & ~(1 << 6); + return reg & ~IntFoldBit; } int |