Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
    Hand merge.

--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e

9 files changed, 302 insertions, 199 deletions

diff --git a/SConstruct b/SConstruct
index 259b6c583..ce80068f3 100644
--- a/SConstruct
+++ b/SConstruct
@@ -279,6 +279,8 @@ sticky_opts.AddOptions(
     # scons 0.96.90 or later.
     ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU',
                env['ALL_CPU_LIST']),
+    ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '',
+               env['ALL_CPU_LIST']),
     BoolOption('ALPHA_TLASER',
                'Model Alpha TurboLaser platform (vs. Tsunami)', False),
     BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
new file mode 100644
index 000000000..5b0de2d6d
--- /dev/null
+++ b/configs/common/FSConfig.py
@@ -0,0 +1,104 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Kevin Lim
+
+import m5
+from m5.objects import *
+from FullO3Config import *
+from SysPaths import *
+from Util import *
+
+script.dir =  '/z/saidi/work/m5.newmem/configs/boot'
+linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
+
+class CowIdeDisk(IdeDisk):
+    image = CowDiskImage(child=RawDiskImage(read_only=True),
+                         read_only=False)
+
+    def childImage(self, ci):
+        self.image.child.image_file = ci
+
+class BaseTsunami(Tsunami):
+    ethernet = NSGigE(configdata=NSGigEPciData(),
+                      pci_bus=0, pci_dev=1, pci_func=0)
+    etherint = NSGigEInt(device=Parent.ethernet)
+    ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+                        pci_func=0, pci_dev=0, pci_bus=0)
+
+def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
+    self = LinuxAlphaSystem()
+    self.iobus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
+    self.bridge = Bridge()
+    self.physmem = PhysicalMemory(range = AddrRange('128MB'))
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+    self.physmem.port = self.membus.port
+    self.disk0 = CowIdeDisk(driveID='master')
+    self.disk2 = CowIdeDisk(driveID='master')
+    self.disk0.childImage(linux_image)
+    self.disk2.childImage(disk('linux-bigswap2.img'))
+    self.tsunami = BaseTsunami()
+    self.tsunami.attachIO(self.iobus)
+    self.tsunami.ide.pio = self.iobus.port
+    self.tsunami.ide.dma = self.iobus.port
+    self.tsunami.ide.config = self.iobus.port
+    self.tsunami.ethernet.pio = self.iobus.port
+    self.tsunami.ethernet.dma = self.iobus.port
+    self.tsunami.ethernet.config = self.iobus.port
+    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
+                                               read_only = True))
+    self.intrctrl = IntrControl()
+    self.cpu = cpu
+
+    connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
+    for each_cpu in listWrapper(self.cpu):
+        each_cpu.itb = AlphaITB()
+        each_cpu.dtb = AlphaDTB()
+    self.cpu.clock = '2GHz'
+    self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
+    self.kernel = binary('vmlinux')
+    self.pal = binary('ts_osfpal')
+    self.console = binary('console')
+    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+    return self
+
+class TsunamiRoot(Root):
+    pass
+
+def DualRoot(clientSystem, serverSystem):
+    self = Root()
+    self.client = clientSystem
+    self.server = serverSystem
+
+    self.etherdump = EtherDump(file='ethertrace')
+    self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
+                               int2 = Parent.server.tsunami.etherint[0],
+                               dump = Parent.etherdump)
+    self.clock = '1THz'
+    return self
diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py
new file mode 100644
index 000000000..2070d11f8
--- /dev/null
+++ b/configs/common/SysPaths.py
@@ -0,0 +1,68 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+import os, sys
+from os.path import isdir, join as joinpath
+from os import environ as env
+
+def disk(file):
+    system()
+    return joinpath(disk.dir, file)
+
+def binary(file):
+    system()
+    return joinpath(binary.dir, file)
+
+def script(file):
+    system()
+    return joinpath(script.dir, file)
+
+def system():
+    if not system.dir:
+        try:
+                path = env['M5_PATH'].split(':')
+        except KeyError:
+                path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
+
+        for system.dir in path:
+            if os.path.isdir(system.dir):
+                break
+        else:
+            raise ImportError, "Can't find a path to system files."
+
+    if not binary.dir:
+        binary.dir = joinpath(system.dir, 'binaries')
+    if not disk.dir:
+        disk.dir = joinpath(system.dir, 'disks')
+    if not script.dir:
+        script.dir = joinpath(system.dir, 'boot')
+
+system.dir = None
+binary.dir = None
+disk.dir = None
+script.dir = None
diff --git a/configs/test/SysPaths.py b/configs/test/SysPaths.py
deleted file mode 100644
index 3f96a546f..000000000
--- a/configs/test/SysPaths.py
+++ /dev/null
@@ -1,40 +0,0 @@
-import os, sys
-from os.path import isdir, join as joinpath
-from os import environ as env
-
-def disk(file):
-    system()
-    return joinpath(disk.dir, file)
-
-def binary(file):
-    system()
-    return joinpath(binary.dir, file)
-
-def script(file):
-    system()
-    return joinpath(script.dir, file)
-
-def system():
-    if not system.dir:
-        try:
-                path = env['M5_PATH'].split(':')
-        except KeyError:
-                path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
-
-        for system.dir in path:
-            if os.path.isdir(system.dir):
-                break
-        else:
-            raise ImportError, "Can't find a path to system files."
-
-    if not binary.dir:
-        binary.dir = joinpath(system.dir, 'binaries')
-    if not disk.dir:
-        disk.dir = joinpath(system.dir, 'disks')
-    if not script.dir:
-        script.dir = joinpath(system.dir, 'boot')
-
-system.dir = None
-binary.dir = None
-disk.dir = None
-script.dir = None
diff --git a/configs/test/fs.py b/configs/test/fs.py
index 7e89b7dd4..5468c5924 100644
--- a/configs/test/fs.py
+++ b/configs/test/fs.py
@@ -2,8 +2,10 @@ import optparse, os, sys
 
 import m5
 from m5.objects import *
+m5.AddToPath('../common')
+from FSConfig import *
 from SysPaths import *
-from FullO3Config import *
+from Util import *
 
 parser = optparse.OptionParser()
 
@@ -20,90 +22,27 @@ if args:
     print "Error: script doesn't take any positional arguments"
     sys.exit(1)
 
-# Base for tests is directory containing this file.
-test_base = os.path.dirname(__file__)
-
-script.dir =  '/z/saidi/work/m5.newmem/configs/boot'
-
-linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
-
-class CowIdeDisk(IdeDisk):
-    image = CowDiskImage(child=RawDiskImage(read_only=True),
-                         read_only=False)
-
-    def childImage(self, ci):
-        self.image.child.image_file = ci
-
-class BaseTsunami(Tsunami):
-    ethernet = NSGigE(configdata=NSGigEPciData(),
-                      pci_bus=0, pci_dev=1, pci_func=0)
-    etherint = NSGigEInt(device=Parent.ethernet)
-    ide = IdeController(disks=[Parent.disk0, Parent.disk2],
-                        pci_func=0, pci_dev=0, pci_bus=0)
-
-class MyLinuxAlphaSystem(LinuxAlphaSystem):
-    iobus = Bus(bus_id=0)
-    membus = Bus(bus_id=1)
-    bridge = Bridge()
-    physmem = PhysicalMemory(range = AddrRange('128MB'))
-    bridge.side_a = iobus.port
-    bridge.side_b = membus.port
-    physmem.port = membus.port
-    disk0 = CowIdeDisk(driveID='master')
-    disk2 = CowIdeDisk(driveID='master')
-    disk0.childImage(linux_image)
-    disk2.childImage(disk('linux-bigswap2.img'))
-    tsunami = BaseTsunami()
-    tsunami.attachIO(iobus)
-    tsunami.ide.pio = iobus.port
-    tsunami.ide.dma = iobus.port
-    tsunami.ide.config = iobus.port
-    tsunami.ethernet.pio = iobus.port
-    tsunami.ethernet.dma = iobus.port
-    tsunami.ethernet.config = iobus.port
-    simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
-                                               read_only = True))
-    intrctrl = IntrControl()
-    if options.detailed:
-        cpu = DetailedO3CPU()
-    elif options.timing:
-        cpu = TimingSimpleCPU()
-        mem_mode = 'timing'
-    else:
-        cpu = AtomicSimpleCPU()
-    cpu.mem = membus
-    cpu.icache_port = membus.port
-    cpu.dcache_port = membus.port
-    cpu.itb = AlphaITB()
-    cpu.dtb = AlphaDTB()
-    cpu.clock = '2GHz'
-    sim_console = SimConsole(listener=ConsoleListener(port=3456))
-    kernel = binary('vmlinux')
-    pal = binary('ts_osfpal')
-    console = binary('console')
-    boot_osflags = 'root=/dev/hda1 console=ttyS0'
-
-class TsunamiRoot(Root):
-    pass
-
-def DualRoot(clientSystem, serverSystem):
-    self = Root()
-    self.client = clientSystem
-    self.server = serverSystem
-
-    self.etherdump = EtherDump(file='ethertrace')
-    self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
-                               int2 = Parent.server.tsunami.etherint[0],
-                               dump = Parent.etherdump)
-    self.clock = '1THz'
-    return self
+if options.detailed:
+    cpu = DetailedO3CPU()
+    cpu2 = DetailedO3CPU()
+    mem_mode = 'Timing'
+elif options.timing:
+    cpu = TimingSimpleCPU()
+    cpu2 = TimingSimpleCPU()
+    mem_mode = 'Timing'
+else:
+    cpu = AtomicSimpleCPU()
+    cpu2 = AtomicSimpleCPU()
+    mem_mode = 'Atomic'
 
 if options.dual:
     root = DualRoot(
-        MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
-        MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
+        MyLinuxAlphaSystem(cpu, mem_mode, linux_image),
+        MyLinuxAlphaSystem(cpu2, mem_mode, linux_image))
+    root.client.readfile = script('netperf-stream-nt-client.rcS')
+    root.server.readfile = script('netperf-server.rcS')
 else:
-    root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem())
+    root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem(cpu, mem_mode, linux_image))
 
 m5.instantiate(root)
 
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 7d45c7870..2bb9a2399 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -160,7 +160,8 @@ if 'O3CPU' in env['CPU_MODELS']:
         ''')
     if env['USE_CHECKER']:
         sources += Split('o3/checker_builder.cc')
-    env['SMT_CPU_MODELS'].append('O3CPU')
+    else:
+        env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now
 
 if 'OzoneCPU' in env['CPU_MODELS']:
     need_bp_unit = True
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index d6bc454ad..41208929a 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -1,91 +1,101 @@
 from m5 import build_env
 from m5.config import *
 from BaseCPU import BaseCPU
+from Checker import O3Checker
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
-    activity = Param.Unsigned("Initial count")
-    numThreads = Param.Unsigned("number of HW thread contexts")
-
-    checker = Param.BaseCPU(NULL, "checker")
+    activity = Param.Unsigned(0, "Initial count")
+    numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+    if build_env['USE_CHECKER']:
+        if not build_env['FULL_SYSTEM']:
+            checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+                                              exitOnError=True,
+                                              warnOnlyOnLoadError=False),
+                                    "checker")
+        else:
+            checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
+            checker.itb = Parent.itb
+            checker.dtb = Parent.dtb
 
     cachePorts = Param.Unsigned("Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
 
-    decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
-    renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
-    iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
-               "delay")
-    commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
-    fetchWidth = Param.Unsigned("Fetch width")
+    decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
+    renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
+    iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
+                                     "delay")
+    commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
+    fetchWidth = Param.Unsigned(8, "Fetch width")
 
-    renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
-    iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+    renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
+    iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
                "delay")
-    commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
-    fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
-    decodeWidth = Param.Unsigned("Decode width")
+    commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
+    fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
+    decodeWidth = Param.Unsigned(8, "Decode width")
 
-    iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+    iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
                "delay")
-    commitToRenameDelay = Param.Unsigned("Commit to rename delay")
-    decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
-    renameWidth = Param.Unsigned("Rename width")
+    commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
+    decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
+    renameWidth = Param.Unsigned(8, "Rename width")
 
-    commitToIEWDelay = Param.Unsigned("Commit to "
+    commitToIEWDelay = Param.Unsigned(1, "Commit to "
                "Issue/Execute/Writeback delay")
-    renameToIEWDelay = Param.Unsigned("Rename to "
+    renameToIEWDelay = Param.Unsigned(2, "Rename to "
                "Issue/Execute/Writeback delay")
-    issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+    issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
               "to the IEW stage)")
-    dispatchWidth = Param.Unsigned("Dispatch width")
-    issueWidth = Param.Unsigned("Issue width")
-    wbWidth = Param.Unsigned("Writeback width")
-    wbDepth = Param.Unsigned("Writeback depth")
-    fuPool = Param.FUPool(NULL, "Functional Unit pool")
+    dispatchWidth = Param.Unsigned(8, "Dispatch width")
+    issueWidth = Param.Unsigned(8, "Issue width")
+    wbWidth = Param.Unsigned(8, "Writeback width")
+    wbDepth = Param.Unsigned(1, "Writeback depth")
+    fuPool = Param.FUPool("Functional Unit pool")
 
-    iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+    iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
                "delay")
-    renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
-    commitWidth = Param.Unsigned("Commit width")
-    squashWidth = Param.Unsigned("Squash width")
-    trapLatency = Param.Tick("Trap latency")
-    fetchTrapLatency = Param.Tick("Fetch trap latency")
-
-    backComSize = Param.Unsigned("Time buffer size for backwards communication")
-    forwardComSize = Param.Unsigned("Time buffer size for forward communication")
-
-    predType = Param.String("Branch predictor type ('local', 'tournament')")
-    localPredictorSize = Param.Unsigned("Size of local predictor")
-    localCtrBits = Param.Unsigned("Bits per counter")
-    localHistoryTableSize = Param.Unsigned("Size of local history table")
-    localHistoryBits = Param.Unsigned("Bits for the local history")
-    globalPredictorSize = Param.Unsigned("Size of global predictor")
-    globalCtrBits = Param.Unsigned("Bits per counter")
-    globalHistoryBits = Param.Unsigned("Bits of history")
-    choicePredictorSize = Param.Unsigned("Size of choice predictor")
-    choiceCtrBits = Param.Unsigned("Bits of choice counters")
-
-    BTBEntries = Param.Unsigned("Number of BTB entries")
-    BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
-
-    RASSize = Param.Unsigned("RAS size")
-
-    LQEntries = Param.Unsigned("Number of load queue entries")
-    SQEntries = Param.Unsigned("Number of store queue entries")
-    LFSTSize = Param.Unsigned("Last fetched store table size")
-    SSITSize = Param.Unsigned("Store set ID table size")
-
-    numRobs = Param.Unsigned("Number of Reorder Buffers");
-
-    numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
-    numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
-               "registers")
-    numIQEntries = Param.Unsigned("Number of instruction queue entries")
-    numROBEntries = Param.Unsigned("Number of reorder buffer entries")
-
-    instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+    renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
+    commitWidth = Param.Unsigned(8, "Commit width")
+    squashWidth = Param.Unsigned(8, "Squash width")
+    trapLatency = Param.Tick(13, "Trap latency")
+    fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
+
+    backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
+    forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
+
+    predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
+    localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
+    localCtrBits = Param.Unsigned(2, "Bits per counter")
+    localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
+    localHistoryBits = Param.Unsigned(11, "Bits for the local history")
+    globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
+    globalCtrBits = Param.Unsigned(2, "Bits per counter")
+    globalHistoryBits = Param.Unsigned(4096, "Bits of history")
+    choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
+    choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
+
+    BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
+    BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
+
+    RASSize = Param.Unsigned(16, "RAS size")
+
+    LQEntries = Param.Unsigned(32, "Number of load queue entries")
+    SQEntries = Param.Unsigned(32, "Number of store queue entries")
+    LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
+    SSITSize = Param.Unsigned(1024, "Store set ID table size")
+
+    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
+
+    numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
+    numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
+                                      "registers")
+    numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
+    numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
+
+    instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
 
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/tests/SConscript b/tests/SConscript
index 5eadce6d4..8e4d1da01 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -25,6 +25,9 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Kevin Lim
 
 import os
 import sys
@@ -136,7 +139,8 @@ def update_test_string(target, source, env):
 
 updateAction = env.Action(update_test, update_test_string)
 
-def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15):
+def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref',
+                 timeout=15):
     """Define a test.
 
     Args:
@@ -153,12 +157,23 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
         default_refdir = True
     if len(cpu_list) == 0:
         cpu_list = env['CPU_MODELS']
+    if env['TEST_CPU_MODELS']:
+        temp_cpu_list = []
+        for i in env['TEST_CPU_MODELS']:
+            if i in cpu_list:
+                temp_cpu_list.append(i)
+        cpu_list = temp_cpu_list
+# Code commented out that shows the general structure if we want to test
+# different OS's as well.
 #    if len(os_list) == 0:
-#        raise RuntimeError, "No OS specified"
+#        for test_cpu in cpu_list:
+#            build_cpu_test(env, category, '', test_cpu, refdir, timeout)
 #    else:
 #        for test_os in os_list:
-#            build_cpu_test(env, category, test_os, cpu_list, refdir, timeout)
-    # Loop through CPU models and generate proper options, ref directories for each
+#            for test_cpu in cpu_list:
+#                build_cpu_test(env, category, test_os, test_cpu, refdir,
+#                               timeout)
+    # Loop through CPU models and generate proper options, ref directories
     for cpu in cpu_list:
         test_os = ''
         if cpu == "AtomicSimpleCPU":
@@ -171,7 +186,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
             raise TypeError, "Unknown CPU model specified"
 
         if default_refdir:
-            # Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified
+            # Reference stats located in ref/arch/os/cpu or ref/arch/cpu
+            # if no OS specified
             test_refdir = os.path.join(refdir, env['TARGET_ISA'])
             if test_os != '':
                 test_refdir = os.path.join(test_refdir, test_os)
@@ -202,8 +218,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
         else:
             cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr]
             
-        env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'],
-                    ' '.join(cmd))
+        env.Command([stdout_string, stderr_string, m5stats_string],
+                    [env.M5Binary, 'run.py'], ' '.join(cmd))
 
         # order of targets is important... see check_test
         env.Command([outdiff_string, statsdiff_string, status_string],
@@ -212,10 +228,12 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1
 
         # phony target to echo status
         if env['update_ref']:
-            p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string],
+            p = env.Command(cpu_option[1] + '_update',
+                            [ref_stats, m5stats_string, status_string],
                             updateAction)
         else:
-            p = env.Command(cpu_option[1] + '_print', [status_string], printAction)
+            p = env.Command(cpu_option[1] + '_print', [status_string],
+                            printAction)
         env.AlwaysBuild(p)
 
         env.Tests.setdefault(category, [])
diff --git a/tests/halt.sh b/tests/halt.sh
new file mode 100644
index 000000000..b1332ebab
--- /dev/null
+++ b/tests/halt.sh
@@ -0,0 +1 @@
+m5 exit