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author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-10-08 19:02:33 +0800 |
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committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-10-09 03:45:47 +0000 |
commit | e1a97946510dd5551f2adf4d7367a954cb34330b (patch) | |
tree | bb887135f0581a1ea8681c7ebf4e35e2119df317 | |
parent | b1fb2d55c598d89e5a29c569da546b74f99a8bbc (diff) | |
download | gem5-e1a97946510dd5551f2adf4d7367a954cb34330b.tar.xz |
system-arm: Initialize ICC_SRE_EL3 register of all CPUs
Fix a bug that only CPU0 initialized ICC_SRE_EL3 register.
Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
-rw-r--r-- | system/arm/aarch64_bootloader/boot.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S index 5e5e39439..38090c8f2 100644 --- a/system/arm/aarch64_bootloader/boot.S +++ b/system/arm/aarch64_bootloader/boot.S @@ -91,12 +91,12 @@ _start: str w0, [x1], #4 /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */ - mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 +2: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 orr x10, x10, #0xf // enable 0xf msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3 isb -2: mov x0, #1 + mov x0, #1 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable #else |