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| author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-05-31 15:50:02 +0800 |
|---|---|---|
| committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-05-31 11:13:35 +0000 |
| commit | ef29f8068e9b9b19d765cad963ba7c476ee61207 (patch) | |
| tree | 327a70df75a4c894796dd686293e377eb71299b9 | |
| parent | 019e3204ba54e23daf597becf36bb92f7272b0d3 (diff) | |
| download | gem5-ef29f8068e9b9b19d765cad963ba7c476ee61207.tar.xz | |
arm: Fix decoding of CRC32 instructions in thumb32
The CRC32 and CRC32C instructions are incorrectly decoded in thumb32
mode according to the latest manual:
https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r
Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578
Signed-off-by: Chun-Chen TK Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index cff3d22f0..aaa0d34e7 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -830,6 +830,15 @@ def format Thumb32DataProcReg() {{ return new Clz(machInst, rd, rm); } break; + } + } else if (bits(op1, 3, 2) == 0x3 && bits(op2, 3, 2) == 0x2) { + const uint32_t op1 = bits(machInst, 22, 20); + const uint32_t op2 = bits(machInst, 5, 4); + const IntRegIndex rd = + (IntRegIndex)(uint32_t)bits(machInst, 11, 8); + const IntRegIndex rm = + (IntRegIndex)(uint32_t)bits(machInst, 3, 0); + switch (op1) { case 0x4: switch (op2) { case 0x0: |