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authorGabe Black <gabeblack@google.com>2019-08-28 17:12:55 -0700
committerGabe Black <gabeblack@google.com>2019-10-02 09:28:49 +0000
commitf469ee610f1fb355a485f96de9ce6c976b48df50 (patch)
tree9636e9a8cb6c056583b31f35cd1e935d46f343b8
parentfc63dc6221357a2d1e16b3295610528452ac1402 (diff)
downloadgem5-f469ee610f1fb355a485f96de9ce6c976b48df50.tar.xz
fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.
This was to support port proxies and getInstPort and getDataPort. With some recent upstream changes, getInstPort and getDataPort are only used for CPU switching which we can't support (TLM ports are bound permanently), and with the sendFunctional delegate for port proxies, we don't need to have a traditional gem5 port lying around. This gets rid of the "mem" port and all its plumbing. Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
-rw-r--r--src/arch/arm/fastmodel/arm/FastModelArch.py2
-rw-r--r--src/arch/arm/fastmodel/arm/cpu.cc11
-rw-r--r--src/arch/arm/fastmodel/arm/cpu.hh26
3 files changed, 1 insertions, 38 deletions
diff --git a/src/arch/arm/fastmodel/arm/FastModelArch.py b/src/arch/arm/fastmodel/arm/FastModelArch.py
index efc40b2d8..b2869563f 100644
--- a/src/arch/arm/fastmodel/arm/FastModelArch.py
+++ b/src/arch/arm/fastmodel/arm/FastModelArch.py
@@ -36,5 +36,3 @@ class FastModelArmCPU(IrisArmCPU):
cxx_header = 'arch/arm/fastmodel/arm/cpu.hh'
cntfrq = Param.UInt64("Value for the CNTFRQ timer register")
-
- mem = RequestPort('Port for port proxies to attach to.')
diff --git a/src/arch/arm/fastmodel/arm/cpu.cc b/src/arch/arm/fastmodel/arm/cpu.cc
index 47420368f..c87c2ac5f 100644
--- a/src/arch/arm/fastmodel/arm/cpu.cc
+++ b/src/arch/arm/fastmodel/arm/cpu.cc
@@ -35,8 +35,7 @@ namespace FastModel
{
ArmCPU::ArmCPU(FastModelArmCPUParams *params) :
- Iris::ArmCPU(params, scx::scx_get_iris_connection_interface()),
- mem(name() + ".mem", this)
+ Iris::ArmCPU(params, scx::scx_get_iris_connection_interface())
{
}
@@ -48,14 +47,6 @@ ArmCPU::initState()
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, cntfrq);
}
-Port &
-ArmCPU::getPort(const std::string &if_name, PortID idx)
-{
- if (if_name == "mem")
- return mem;
- return Iris::ArmCPU::getPort(if_name, idx);
-}
-
} // namespace FastModel
FastModel::ArmCPU *
diff --git a/src/arch/arm/fastmodel/arm/cpu.hh b/src/arch/arm/fastmodel/arm/cpu.hh
index 1d9d585c3..379174ec3 100644
--- a/src/arch/arm/fastmodel/arm/cpu.hh
+++ b/src/arch/arm/fastmodel/arm/cpu.hh
@@ -39,36 +39,10 @@ namespace FastModel
// This class adds non-Iris, gem5 functionality to this CPU model.
class ArmCPU : public Iris::ArmCPU
{
- private:
- class MemPort : public MasterPort
- {
- public:
- using MasterPort::MasterPort;
-
- bool
- recvTimingResp(PacketPtr pkt) override
- {
- panic("%s.%s not implemented.\n", name(), __FUNCTION__);
- }
-
- void
- recvReqRetry() override
- {
- panic("%s.%s not implemented.\n", name(), __FUNCTION__);
- }
- };
-
- MemPort mem;
-
public:
ArmCPU(FastModelArmCPUParams *params);
void initState() override;
- Port &getPort(const std::string &if_name,
- PortID idx=InvalidPortID) override;
-
- Port &getDataPort() override { return mem; }
- Port &getInstPort() override { return mem; }
};
} // namespace FastModel