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authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:12 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:12 -0500
commitf64c8bafd2609ad21535cef3ee9d8a0ac41f1f8c (patch)
treef9abed96e9e3c333e3122ead11f617b9696d0682
parent1fcd389fa327493d66767ee11698ccff8fccb7ac (diff)
downloadgem5-f64c8bafd2609ad21535cef3ee9d8a0ac41f1f8c.tar.xz
ARM: BXJ should be BX when there is no J support
-rw-r--r--src/arch/arm/isa/decoder/arm.isa6
-rw-r--r--src/arch/arm/isa/formats/branch.isa7
2 files changed, 8 insertions, 5 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 31456dfc6..4c5d71ad9 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -67,10 +67,8 @@ format DataOp {
1: decode OPCODE_7 {
0x0: decode MISC_OPCODE {
0x0: ArmMsrMrs::armMsrMrs();
- 0x1: ArmBxClz::armBxClz();
- 0x2: decode OPCODE {
- 0x9: WarnUnimpl::bxj();
- }
+ // bxj unimplemented, treated as bx
+ 0x1,0x2: ArmBxClz::armBxClz();
0x3: decode OPCODE {
0x9: ArmBlxReg::armBlxReg();
}
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index dbb6f9f9d..055955520 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -207,7 +207,12 @@ def format Thumb32BranchesAndMiscCtrl() {{
break;
}
case 0x3c:
- return new WarnUnimplemented("bxj", machInst);
+ {
+ // On systems that don't support bxj, bxj == bx
+ return new BxReg(machInst,
+ (IntRegIndex)(uint32_t)bits(machInst, 19, 16),
+ COND_UC);
+ }
case 0x3d:
{
const uint32_t imm32 = bits(machInst, 7, 0);