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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-27 15:45:57 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | f73caae20fed7b4500a724ac85c20b637ee353a1 (patch) | |
| tree | b4f10cb3e3b35bd5c71b86bc5e26120f697d5d09 | |
| parent | 390a74f59934b85d91489f8a563450d8321b602d (diff) | |
| download | gem5-f73caae20fed7b4500a724ac85c20b637ee353a1.tar.xz | |
cpu: Add byteEnable assertions to readMem and initateMemRead
Those are already present in writeMem; looking for consistency
Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 2 | ||||
| -rw-r--r-- | src/cpu/checker/cpu.cc | 2 | ||||
| -rw-r--r-- | src/cpu/minor/exec_context.hh | 1 | ||||
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 2 |
4 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 4b4b05c1d..c228357ce 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -965,6 +965,7 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector<bool>& byteEnable) { + assert(byteEnable.empty() || byteEnable.size() == size); return cpu->pushRequest( dynamic_cast<typename DynInstPtr::PtrType>(this), /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr, @@ -977,6 +978,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector<bool>& byteEnable) { + assert(byteEnable.empty() || byteEnable.size() == size); return cpu->pushRequest( dynamic_cast<typename DynInstPtr::PtrType>(this), /* st */ false, data, size, addr, flags, res, nullptr, byteEnable); diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index cca6d6b12..48ee05985 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -178,6 +178,8 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector<bool>& byteEnable) { + assert(byteEnable.empty() || byteEnable.size() == size); + Fault fault = NoFault; bool checked_flags = false; bool flags_match = true; diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 184dd2910..9b347b225 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -116,6 +116,7 @@ class ExecContext : public ::ExecContext const std::vector<bool>& byteEnable = std::vector<bool>()) override { + assert(byteEnable.empty() || byteEnable.size() == size); return execute.getLSQ().pushRequest(inst, true /* load */, nullptr, size, addr, flags, nullptr, nullptr, byteEnable); } diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 48a9f9423..8e4aa3961 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -440,6 +440,7 @@ class SimpleExecContext : public ExecContext { const std::vector<bool>& byteEnable = std::vector<bool>()) override { + assert(byteEnable.empty() || byteEnable.size() == size); return cpu->readMem(addr, data, size, flags, byteEnable); } @@ -449,6 +450,7 @@ class SimpleExecContext : public ExecContext { const std::vector<bool>& byteEnable = std::vector<bool>()) override { + assert(byteEnable.empty() || byteEnable.size() == size); return cpu->initiateMemRead(addr, size, flags, byteEnable); } |