diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-10 22:15:34 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-10 22:15:34 -0400 |
| commit | fb8c95824144d1984539f7a918086f87858ff27d (patch) | |
| tree | 837ffa4ffb3cfeb8d45f09e3eff4e9bd9fb063ff | |
| parent | c8b43641fdf189b7148137f5f8f40bcb01e1c0ec (diff) | |
| download | gem5-fb8c95824144d1984539f7a918086f87858ff27d.tar.xz | |
sparc: update o3 regressions
6 files changed, 2139 insertions, 2148 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 67bff692e..99d6fe91b 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 13:27:10 -M5 started Apr 21 2011 13:28:40 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing +gem5 compiled Jun 10 2011 22:06:52 +gem5 started Jun 10 2011 22:07:32 +gem5 executing on zooks +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -22,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18633000 because target called exit() +Exiting @ tick 19016500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index db37ab210..9c30078fb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,459 +1,460 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 79158 # Simulator instruction rate (inst/s) -host_mem_usage 209796 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 101982426 # Simulator tick rate (ticks/s) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19016500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 51742 # Simulator instruction rate (inst/s) +host_tick_rate 68090181 # Simulator tick rate (ticks/s) +host_mem_usage 162768 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18633000 # Number of ticks simulated +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 38034 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5148 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3432 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 838 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4682 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2465 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5154 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted -system.cpu.commit.branches 3359 # Number of branches committed -system.cpu.commit.bw_lim_events 86 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 337 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 167 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4256 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 23684 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5148 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 937 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 353 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.810513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.905949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21526 73.67% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3882 13.28% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 537 1.84% 88.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 503 1.72% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.33% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 525 1.80% 94.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 239 0.82% 95.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 0.66% 96.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1137 3.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 29221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.135353 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.622706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13502 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6935 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7417 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1260 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 23270 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13958 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6236 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7103 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 21729 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 19486 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40358 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 40358 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5654 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 629 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2349 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3050 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1902 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 18598 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18016 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 95 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.185129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20388 69.77% 69.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 4239 14.51% 84.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1899 6.50% 90.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1712 5.86% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 1.51% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 282 0.97% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 168 0.57% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 79 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29221 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13295 73.80% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2920 16.21% 90.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1801 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 18016 # Type of FU issued +system.cpu.iq.rate 0.473681 # Inst issue rate +system.cpu.iq.fu_busy_cnt 123 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006827 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65447 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 23160 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 18139 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 824 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 454 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20254 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3050 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1902 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 372 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17560 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2852 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 456 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1086 # number of nop insts executed +system.cpu.iew.exec_refs 4598 # number of memory reference insts executed +system.cpu.iew.exec_branches 3866 # Number of branches executed +system.cpu.iew.exec_stores 1746 # Number of stores executed +system.cpu.iew.exec_rate 0.461692 # Inst execution rate +system.cpu.iew.wb_sent 17276 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17101 # cumulative count of insts written-back +system.cpu.iew.wb_producers 7938 # num instructions producing a value +system.cpu.iew.wb_consumers 9273 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.449624 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.856034 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 27481 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.552200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 838 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.542390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.183434 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.14% 99.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 86 0.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20215 72.25% 72.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4492 16.06% 88.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1466 5.24% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 768 2.75% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 366 1.31% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 259 0.93% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 283 1.01% 99.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.15% 99.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 87 0.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27978 # Number of insts commited each cycle system.cpu.commit.count 15175 # Number of instructions committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.int_insts 12186 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 3674 # Number of memory references committed system.cpu.commit.loads 2226 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 3674 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 3359 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 12186 # Number of committed integer instructions. +system.cpu.commit.function_calls 187 # Number of function calls committed. +system.cpu.commit.bw_lim_events 87 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 47306 # The number of ROB reads +system.cpu.rob.rob_writes 41741 # The number of ROB writes +system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8813 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.579210 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.579210 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2764 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.044863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.cpi 2.632293 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.632293 # CPI: Total CPI of All Threads +system.cpu.ipc 0.379897 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.379897 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28130 # number of integer regfile reads +system.cpu.int_regfile_writes 15668 # number of integer regfile writes +system.cpu.misc_regfile_reads 6217 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 195.108308 # Cycle average of tags in use +system.cpu.icache.total_refs 3800 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.445783 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 195.108308 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.095268 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3800 # number of ReadReq hits +system.cpu.icache.demand_hits 3800 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3800 # number of overall hits +system.cpu.icache.ReadReq_misses 456 # number of ReadReq misses +system.cpu.icache.demand_misses 456 # number of demand (read+write) misses +system.cpu.icache.overall_misses 456 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15987000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15987000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15987000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4256 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.107143 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.107143 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.107143 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35059.210526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35059.210526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35059.210526 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 11676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11676000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.078008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.078008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.078008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35168.674699 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 102.568719 # Cycle average of tags in use +system.cpu.dcache.total_refs 3697 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25.321918 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 102.568719 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025041 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits +system.cpu.dcache.demand_hits 3691 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3691 # number of overall hits +system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses +system.cpu.dcache.demand_misses 523 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 523 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4005000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14642500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18647500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18647500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2772 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35890.931373 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35837.349398 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 14643500 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 4214 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 4214 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.041486 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2974500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.205479 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.124110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.124110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34826.086957 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35888.480392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35654.875717 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35654.875717 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4206 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35361.842105 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3674 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 18812500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.126486 # miss rate for demand accesses -system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5215000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.034712 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 377 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 377 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 102.139862 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.024936 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 4206 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35361.842105 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3674 # number of overall hits -system.cpu.dcache.overall_miss_latency 18812500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.126486 # miss rate for overall accesses -system.cpu.dcache.overall_misses 532 # number of overall misses -system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5215000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.034712 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 2242500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2973500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5216000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5216000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.034646 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034646 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35595.238095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35825.301205 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.139862 # Cycle average of tags in use -system.cpu.dcache.total_refs 3680 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 7079 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 23444 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 13037 # Number of cycles decode is idle -system.cpu.decode.RunCycles 7241 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1159 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 5154 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4051 # Number of cache lines fetched -system.cpu.fetch.Cycles 7481 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 377 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 23840 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 813 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.138299 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4051 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2697 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.639708 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 28623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.832897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.946042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21142 73.86% 73.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3578 12.50% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 587 2.05% 88.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 505 1.76% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 662 2.31% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 528 1.84% 94.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 244 0.85% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 195 0.68% 95.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1182 4.13% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28623 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35069.791667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3571 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16833500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.118489 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 480 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 126 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.087386 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10.087571 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4051 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35069.791667 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency -system.cpu.icache.demand_hits 3571 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16833500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.118489 # miss rate for demand accesses -system.cpu.icache.demand_misses 480 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 126 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.087386 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 204.373592 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.099792 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 4051 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35069.791667 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3571 # number of overall hits -system.cpu.icache.overall_miss_latency 16833500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.118489 # miss rate for overall accesses -system.cpu.icache.overall_misses 480 # number of overall misses -system.cpu.icache.overall_mshr_hits 126 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.087386 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 204.373592 # Cycle average of tags in use -system.cpu.icache.total_refs 3571 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 3851 # Number of branches executed -system.cpu.iew.exec_nop 1086 # number of nop insts executed -system.cpu.iew.exec_rate 0.469692 # Inst execution rate -system.cpu.iew.exec_refs 4584 # number of memory reference insts executed -system.cpu.iew.exec_stores 1742 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3044 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 564 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1894 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20242 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2842 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17504 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 818 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 446 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 9307 # num instructions consuming a value -system.cpu.iew.wb_count 17063 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.856022 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 7967 # num instructions producing a value -system.cpu.iew.wb_rate 0.457858 # insts written-back per cycle -system.cpu.iew.wb_sent 17239 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 28062 # number of integer regfile reads -system.cpu.int_regfile_writes 15640 # number of integer regfile writes -system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13268 73.84% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2908 16.18% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1793 9.98% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17969 # Type of FU issued -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 125 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006956 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 29 23.20% 45.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 18094 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 64767 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17063 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 23189 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 18592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17969 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 564 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3563 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 28623 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.627782 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.193207 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19805 69.19% 69.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 4241 14.82% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1891 6.61% 90.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1717 6.00% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 425 1.48% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 0.97% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 79 0.28% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.05% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28623 # Number of insts issued each cycle -system.cpu.iq.rate 0.482169 # Inst issue rate +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 230.191737 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 230.191737 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.007025 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 476 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 13493000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2870000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2871000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34314.769976 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.324455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12837000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.313253 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34376.050420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34376.050420 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34360.887097 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17043000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15447500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 496 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 238.651434 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.007283 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34360.887097 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17043000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 496 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15447500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 496 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 12217500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14827500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14827500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31087.786260 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31445.783133 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 238.651434 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 3044 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1894 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6202 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.numCycles 37267 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.IdleCycles 13492 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 40241 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 21695 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 19448 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 7019 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1159 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 5616 # Number of HB maps that are undone due to squashing -system.cpu.rename.int_rename_lookups 40241 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 6278 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 613 # count of serializing insts renamed -system.cpu.rename.skidInsts 2673 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 579 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 46798 # The number of ROB reads -system.cpu.rob.rob_writes 41616 # The number of ROB writes -system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index a126d9514..e4939da40 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,30 +1,26 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 13:27:10 -M5 started Apr 21 2011 13:27:31 -M5 executing on maize -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +gem5 compiled Jun 10 2011 22:06:52 +gem5 started Jun 10 2011 22:06:57 +gem5 executing on zooks +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 @@ -61,19 +57,19 @@ Iteration 6 completed [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed [Iteration 10, Thread 1] Got lock [Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 @@ -83,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 117445500 because target called exit() +Exiting @ tick 117354500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 6a03641e3..0e7434ae8 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,276 +1,140 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 107432 # Simulator instruction rate (inst/s) -host_mem_usage 220336 # Number of bytes of host memory used -host_seconds 10.73 # Real time elapsed on the host -host_tick_rate 10941647 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1153138 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 117445500 # Number of ticks simulated +sim_ticks 117354500 # Number of ticks simulated +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 90067 # Simulator instruction rate (inst/s) +host_tick_rate 9199514 # Simulator tick rate (ticks/s) +host_mem_usage 171836 # Number of bytes of host memory used +host_seconds 12.76 # Real time elapsed on the host +sim_insts 1148940 # Number of instructions simulated +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 234710 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.BPredUnit.lookups 91844 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 90062 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 91032 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 88645 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 89261 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 91887 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 92336 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 92336 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu0.commit.branches 89544 # Number of branches committed -system.cpu0.commit.bw_lim_events 223 # number cycles where commit BW limit reached -system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.commitCommittedInsts 534493 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 9438 # The number of squashed insts skipped by commit -system.cpu0.commit.committed_per_cycle::samples 214748 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.488931 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.121519 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33657 15.67% 15.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90653 42.21% 57.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2478 1.15% 59.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 734 0.34% 59.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 738 0.34% 59.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 85720 39.92% 99.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 469 0.22% 99.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 76 0.04% 99.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 223 0.10% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 214748 # Number of insts commited each cycle -system.cpu0.commit.count 534493 # Number of instructions committed -system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.function_calls 0 # Number of function calls committed. -system.cpu0.commit.int_insts 359762 # Number of committed integer instructions. -system.cpu0.commit.loads 174300 # Number of loads committed -system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.refs 261956 # Number of memory references committed -system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.committedInsts 448134 # Number of Instructions Simulated -system.cpu0.committedInsts_total 448134 # Number of Instructions Simulated -system.cpu0.cpi 0.524156 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.524156 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 89494 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 27082.653061 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27751.366120 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 89004 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 13270500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.005475 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 490 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 307 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 5078500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002045 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 16923.076923 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13923.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 440000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_mshr_miss_latency 362000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 87614 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 46112.007407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37114.942529 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 87074 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 24900484 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.006163 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 366 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 6458000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001986 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 608.017241 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 177108 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 37059.207767 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32315.126050 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 176078 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 38170984 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.005816 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1030 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 673 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 11536500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.002016 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 357 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_blocks::0 141.294426 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.121239 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.275966 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.002190 # Average percentage of cache occupancy -system.cpu0.dcache.overall_accesses 177108 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 37059.207767 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32315.126050 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 176078 # number of overall hits -system.cpu0.dcache.overall_miss_latency 38170984 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.005816 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1030 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 673 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 11536500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.002016 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 357 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 140.173187 # Cycle average of tags in use -system.cpu0.dcache.total_refs 105795 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.decode.BlockedCycles 13474 # Number of cycles decode is blocked -system.cpu0.decode.DecodedInsts 548904 # Number of instructions handled by decode -system.cpu0.decode.IdleCycles 20013 # Number of cycles decode is idle -system.cpu0.decode.RunCycles 181043 # Number of cycles decode is running -system.cpu0.decode.SquashCycles 2044 # Number of cycles decode is squashing -system.cpu0.decode.UnblockCycles 201 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 92336 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 5242 # Number of cache lines fetched -system.cpu0.fetch.Cycles 181487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 476 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 549904 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 1222 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.393100 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 5242 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 89261 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 2.341093 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 216775 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.536750 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.186468 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 397 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 5189 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 547166 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 91844 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89042 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 180871 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1241 # Number of cycles fetch has spent squashing +system.cpu0.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.CacheLines 5189 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 438 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 216259 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.530142 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.183723 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35288 16.28% 16.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 90175 41.60% 57.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 487 0.22% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 807 0.37% 58.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 586 0.27% 58.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86536 39.92% 98.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 826 0.38% 99.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 206 0.10% 99.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1864 0.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35388 16.36% 16.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 90011 41.62% 57.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 494 0.23% 58.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785 0.36% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 592 0.27% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86207 39.86% 98.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 812 0.38% 99.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 223 0.10% 99.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1747 0.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 216775 # Number of instructions fetched each cycle (Total) -system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.icache.ReadReq_accesses 5242 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 39013.262599 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36995.894910 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 4488 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 29416000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.143838 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 754 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 22530500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.116177 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11000 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.381579 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 5242 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 39013.262599 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36995.894910 # average overall mshr miss latency -system.cpu0.icache.demand_hits 4488 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 29416000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.143838 # miss rate for demand accesses -system.cpu0.icache.demand_misses 754 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22530500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.116177 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_blocks::0 257.473705 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.502878 # Average percentage of cache occupancy -system.cpu0.icache.overall_accesses 5242 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 39013.262599 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36995.894910 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 4488 # number of overall hits -system.cpu0.icache.overall_miss_latency 29416000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.143838 # miss rate for overall accesses -system.cpu0.icache.overall_misses 754 # number of overall misses -system.cpu0.icache.overall_mshr_hits 145 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22530500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.116177 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 307 # number of replacements -system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 257.473705 # Cycle average of tags in use -system.cpu0.icache.total_refs 4488 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 18117 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.branchMispredicts 1242 # Number of branch mispredicts detected at execute -system.cpu0.iew.exec_branches 90345 # Number of branches executed -system.cpu0.iew.exec_nop 86733 # number of nop insts executed -system.cpu0.iew.exec_rate 1.932437 # Inst execution rate -system.cpu0.iew.exec_refs 263598 # number of memory reference insts executed -system.cpu0.iew.exec_stores 88173 # Number of stores executed -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.iewBlockCycles 823 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 175971 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 722 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 481 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 88710 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 543927 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 175425 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 910 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 453914 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 2044 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread0.forwLoads 85880 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.squashedLoads 1671 # Number of loads squashed -system.cpu0.iew.lsq.thread0.squashedStores 1054 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 817 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.wb_consumers 270902 # num instructions consuming a value -system.cpu0.iew.wb_count 453315 # cumulative count of insts written-back -system.cpu0.iew.wb_fanout 0.992949 # average fanout of values written-back -system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.wb_producers 268992 # num instructions producing a value -system.cpu0.iew.wb_rate 1.929887 # insts written-back per cycle -system.cpu0.iew.wb_sent 453561 # cumulative count of insts sent to commit -system.cpu0.int_regfile_reads 812740 # number of integer regfile reads -system.cpu0.int_regfile_writes 365710 # number of integer regfile writes -system.cpu0.ipc 1.907830 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.907830 # IPC: Total IPC of All Threads +system.cpu0.fetch.rateDist::total 216259 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391308 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.331243 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20008 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 13629 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 180385 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 202 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2035 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 546099 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2035 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20667 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1184 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11729 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 179959 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 685 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 543550 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 277 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 370143 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1084537 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1084537 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 360120 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10023 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 796 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 810 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3593 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 175288 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 88379 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 85877 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 85749 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 454609 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 808 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 453072 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8037 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 6746 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 216259 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.095043 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.058701 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33498 15.49% 15.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5606 2.59% 18.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 87868 40.63% 58.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 86822 40.15% 98.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1462 0.68% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 715 0.33% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 184 0.09% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 95 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 216259 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 33 15.71% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 75 35.71% 51.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 102 48.57% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 190821 41.95% 41.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 190073 41.95% 41.95% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 41.95% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 41.95% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 41.95% # Type of FU issued @@ -299,1491 +163,1627 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 41.95% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 41.95% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 41.95% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 175718 38.63% 80.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88285 19.41% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 175045 38.64% 80.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 87954 19.41% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 454824 # Type of FU issued -system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iq.FU_type_0::total 453072 # Type of FU issued +system.cpu0.iq.rate 1.930348 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 210 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000464 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1122705 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 463496 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 451578 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu0.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000490 # FU busy rate (busy events/executed inst) -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 33 14.80% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 81 36.32% 51.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 109 48.88% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.int_alu_accesses 455047 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 1126736 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 453315 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 465372 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 456374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 454824 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 820 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 8136 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 261 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 6774 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.issued_per_cycle::samples 216775 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.098139 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.056899 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33322 15.37% 15.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5647 2.61% 17.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88171 40.67% 58.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87126 40.19% 98.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1486 0.69% 99.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 733 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 191 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 90 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 216775 # Number of insts issued each cycle -system.cpu0.iq.rate 1.936311 # Inst issue rate -system.cpu0.memDep0.conflictingLoads 86214 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86089 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 175971 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 88710 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 265353 # number of misc regfile reads +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 453282 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 85551 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 1644 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1051 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 2035 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 809 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 541811 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 507 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 175288 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 88379 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 716 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 486 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 773 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 452172 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 174750 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 900 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 86394 # number of nop insts executed +system.cpu0.iew.exec_refs 262594 # number of memory reference insts executed +system.cpu0.iew.exec_branches 89995 # Number of branches executed +system.cpu0.iew.exec_stores 87844 # Number of stores executed +system.cpu0.iew.exec_rate 1.926514 # Inst execution rate +system.cpu0.iew.wb_sent 451822 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 451578 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 267957 # num instructions producing a value +system.cpu0.iew.wb_consumers 269862 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 1.923983 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.992941 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitCommittedInsts 532525 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 9290 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 1094 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 214241 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.485635 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.121796 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33798 15.78% 15.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90322 42.16% 57.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2486 1.16% 59.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 740 0.35% 59.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 737 0.34% 59.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 85412 39.87% 99.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 444 0.21% 99.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 77 0.04% 99.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 225 0.11% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 214241 # Number of insts commited each cycle +system.cpu0.commit.count 532525 # Number of instructions committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 260972 # Number of memory references committed +system.cpu0.commit.loads 173644 # Number of loads committed +system.cpu0.commit.membars 84 # Number of memory barriers committed +system.cpu0.commit.branches 89216 # Number of branches committed +system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 358450 # Number of committed integer instructions. +system.cpu0.commit.function_calls 223 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 754670 # The number of ROB reads +system.cpu0.rob.rob_writes 1085676 # The number of ROB writes +system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18451 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 446494 # Number of Instructions Simulated +system.cpu0.committedInsts_total 446494 # Number of Instructions Simulated +system.cpu0.cpi 0.525673 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.525673 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.902322 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.902322 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 809682 # number of integer regfile reads +system.cpu0.int_regfile_writes 364308 # number of integer regfile writes +system.cpu0.fp_regfile_reads 192 # number of floating regfile reads +system.cpu0.misc_regfile_reads 264341 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.numCycles 234892 # number of cpu cycles simulated -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.BlockCycles 1209 # Number of cycles rename is blocking -system.cpu0.rename.CommittedMaps 361432 # Number of HB maps that are committed -system.cpu0.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu0.rename.IdleCycles 20699 # Number of cycles rename is idle -system.cpu0.rename.LSQFullEvents 289 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenameLookups 1088795 # Number of register rename lookups that rename has made -system.cpu0.rename.RenamedInsts 545750 # Number of instructions processed by rename -system.cpu0.rename.RenamedOperands 371672 # Number of destination operands rename has renamed -system.cpu0.rename.RunCycles 180600 # Number of cycles rename is running -system.cpu0.rename.SquashCycles 2044 # Number of cycles rename is squashing -system.cpu0.rename.UnblockCycles 697 # Number of cycles rename is unblocking -system.cpu0.rename.UndoneMaps 10240 # Number of HB maps that are undone due to squashing -system.cpu0.rename.int_rename_lookups 1088795 # Number of integer rename lookups -system.cpu0.rename.serializeStallCycles 11526 # count of cycles rename stalled for serializing inst -system.cpu0.rename.serializingInsts 803 # count of serializing insts renamed -system.cpu0.rename.skidInsts 4179 # count of insts added to the skid buffer -system.cpu0.rename.tempSerializingInsts 807 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 757295 # The number of ROB reads -system.cpu0.rob.rob_writes 1089916 # The number of ROB writes -system.cpu0.timesIdled 338 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.icache.replacements 291 # number of replacements +system.cpu0.icache.tagsinuse 245.354699 # Cycle average of tags in use +system.cpu0.icache.total_refs 4480 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 576 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.777778 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 245.354699 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.479208 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits 4480 # number of ReadReq hits +system.cpu0.icache.demand_hits 4480 # number of demand (read+write) hits +system.cpu0.icache.overall_hits 4480 # number of overall hits +system.cpu0.icache.ReadReq_misses 709 # number of ReadReq misses +system.cpu0.icache.demand_misses 709 # number of demand (read+write) misses +system.cpu0.icache.overall_misses 709 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 27352000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 27352000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 27352000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses 5189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses 5189 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses 5189 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate 0.136635 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate 0.136635 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate 0.136635 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency 38578.279267 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency 38578.279267 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency 38578.279267 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 16000 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 132 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 577 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 577 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 577 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency 21152000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 21152000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 21152000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.111197 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate 0.111197 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate 0.111197 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36658.578856 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 9 # number of replacements +system.cpu0.dcache.tagsinuse 140.104909 # Cycle average of tags in use +system.cpu0.dcache.total_refs 105362 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 605.528736 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::0 141.224248 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.119339 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.275829 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.002186 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits 88681 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits 86746 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits 175427 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits 175427 # number of overall hits +system.cpu0.dcache.ReadReq_misses 467 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses 1007 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses 1007 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 13105000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 24852484 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency 37957484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 37957484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses 89148 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses 87286 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses 176434 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses 176434 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate 0.005238 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate 0.006187 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate 0.005708 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate 0.005708 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency 28062.098501 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 46023.118519 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency 37693.628600 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency 37693.628600 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 173500 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6673.076923 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks 6 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 284 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 649 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 649 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 5054000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6424000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 11478000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 11478000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002005 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate 0.002029 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate 0.002029 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27617.486339 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36708.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 199395 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.BPredUnit.lookups 54492 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 52165 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1102 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 53937 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 51730 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 53298 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 55521 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 55616 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 55616 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted -system.cpu1.commit.branches 52878 # Number of branches committed -system.cpu1.commit.bw_lim_events 488 # number cycles where commit BW limit reached -system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.commitCommittedInsts 297918 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 6615 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 8048 # The number of squashed insts skipped by commit -system.cpu1.commit.committed_per_cycle::samples 188159 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.583331 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.956493 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 78134 41.53% 41.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53655 28.52% 70.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 7488 3.98% 74.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7425 3.95% 77.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2454 1.30% 79.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 37926 20.16% 99.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 461 0.25% 99.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 128 0.07% 99.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 188159 # Number of insts commited each cycle -system.cpu1.commit.count 297918 # Number of instructions committed -system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.function_calls 0 # Number of function calls committed. -system.cpu1.commit.int_insts 203433 # Number of committed integer instructions. -system.cpu1.commit.loads 87419 # Number of loads committed -system.cpu1.commit.membars 5903 # Number of memory barriers committed -system.cpu1.commit.refs 128431 # Number of memory references committed -system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.committedInsts 248345 # Number of Instructions Simulated -system.cpu1.committedInsts_total 248345 # Number of Instructions Simulated -system.cpu1.cpi 0.804816 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.804816 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 51009 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 20896.247241 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13877.358491 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 50556 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9466000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.008881 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 453 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 294 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003117 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 159 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 25933.962264 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22933.962264 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1374500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.803030 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_miss_latency 1215500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.803030 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 53 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 40946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 23975.806452 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15514.150943 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 40822 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 2973000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.003028 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1644500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002589 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 1612.206897 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 91955 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 21558.058925 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14532.075472 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 91378 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 12439000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.006275 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 577 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 3851000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.002882 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_blocks::0 25.063911 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -9.009839 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.048953 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.017597 # Average percentage of cache occupancy -system.cpu1.dcache.overall_accesses 91955 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 21558.058925 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14532.075472 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 91378 # number of overall hits -system.cpu1.dcache.overall_miss_latency 12439000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.006275 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 577 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 312 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 3851000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.002882 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 16.054072 # Cycle average of tags in use -system.cpu1.dcache.total_refs 46754 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.BlockedCycles 20803 # Number of cycles decode is blocked -system.cpu1.decode.DecodedInsts 309923 # Number of instructions handled by decode -system.cpu1.decode.IdleCycles 54694 # Number of cycles decode is idle -system.cpu1.decode.RunCycles 107191 # Number of cycles decode is running -system.cpu1.decode.SquashCycles 1741 # Number of cycles decode is squashing -system.cpu1.decode.UnblockCycles 5470 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 55616 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 20621 # Number of cache lines fetched -system.cpu1.fetch.Cycles 113033 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 217 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 311054 # Number of instructions fetch has processed +system.cpu1.BPredUnit.usedRAS 504 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 21267 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 303560 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 54492 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 52234 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 111140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1177 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 1161 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.278258 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 20621 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 53298 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.556266 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 196498 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.582988 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.040174 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 21267 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 240 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 196288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.546503 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.023941 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 83465 42.48% 42.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 58273 29.66% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7057 3.59% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2697 1.37% 77.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1913 0.97% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 38892 19.79% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2445 1.24% 99.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 254 0.13% 99.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1502 0.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 85148 43.38% 43.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 57550 29.32% 72.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7358 3.75% 76.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2678 1.36% 77.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1913 0.97% 78.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 37446 19.08% 97.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2461 1.25% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 260 0.13% 99.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 196498 # Number of instructions fetched each cycle (Total) -system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses 20621 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 15456.066946 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12612.500000 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 20143 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 7388000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.023180 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 478 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5549500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.021337 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 45.779545 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 20621 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 15456.066946 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12612.500000 # average overall mshr miss latency -system.cpu1.icache.demand_hits 20143 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 7388000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.023180 # miss rate for demand accesses -system.cpu1.icache.demand_misses 478 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5549500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.021337 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_blocks::0 88.430285 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.172715 # Average percentage of cache occupancy -system.cpu1.icache.overall_accesses 20621 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 15456.066946 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12612.500000 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 20143 # number of overall hits -system.cpu1.icache.overall_miss_latency 7388000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.023180 # miss rate for overall accesses -system.cpu1.icache.overall_misses 478 # number of overall misses -system.cpu1.icache.overall_mshr_hits 38 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5549500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.021337 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 440 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 328 # number of replacements -system.cpu1.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 88.430285 # Cycle average of tags in use -system.cpu1.icache.total_refs 20143 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.branchMispredicts 1186 # Number of branch mispredicts detected at execute -system.cpu1.iew.exec_branches 53426 # Number of branches executed -system.cpu1.iew.exec_nop 44397 # number of nop insts executed -system.cpu1.iew.exec_rate 1.290846 # Inst execution rate -system.cpu1.iew.exec_refs 129529 # number of memory reference insts executed -system.cpu1.iew.exec_stores 41363 # Number of stores executed -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.iewBlockCycles 1504 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 88859 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 932 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 535 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 41782 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 305999 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 88166 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 964 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 258004 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 47 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread0.forwLoads 37142 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.squashedLoads 1440 # Number of loads squashed -system.cpu1.iew.lsq.thread0.squashedStores 770 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 196 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 990 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.wb_consumers 149591 # num instructions consuming a value -system.cpu1.iew.wb_count 257643 # cumulative count of insts written-back -system.cpu1.iew.wb_fanout 0.975567 # average fanout of values written-back -system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.wb_producers 145936 # num instructions producing a value -system.cpu1.iew.wb_rate 1.289040 # insts written-back per cycle -system.cpu1.iew.wb_sent 257774 # cumulative count of insts sent to commit -system.cpu1.int_regfile_reads 446126 # number of integer regfile reads -system.cpu1.int_regfile_writes 206677 # number of integer regfile writes -system.cpu1.ipc 1.242520 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.242520 # IPC: Total IPC of All Threads -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 123325 47.62% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94249 36.39% 84.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 41394 15.98% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 258968 # Type of FU issued -system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu1.iq.fu_busy_cnt 195 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.000753 # FU busy rate (busy events/executed inst) -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 11 5.64% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 53 27.18% 32.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 131 67.18% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.int_alu_accesses 259163 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 714631 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 257643 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 268053 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 254426 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 258968 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 7176 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 6422 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.fetch.rateDist::total 196288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.273287 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.522405 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 56178 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 20903 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 104877 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 5862 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1747 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 302339 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1747 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 56804 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 7350 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12853 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 110244 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 569 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 300619 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 206640 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 572225 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 572225 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 198555 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 8085 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 945 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1003 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2692 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 86261 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 40322 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 42289 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 35840 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 247735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7474 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 252580 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 561 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 5912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.issued_per_cycle::samples 196498 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.317917 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.287238 # Number of insts issued each cycle +system.cpu1.iq.iqSquashedInstsExamined 6388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 555 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 196288 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.286783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.284176 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 79641 40.53% 40.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 27330 13.91% 54.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43586 22.18% 76.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 41460 21.10% 97.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2668 1.36% 99.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1566 0.80% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 155 0.08% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 81418 41.48% 41.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 28257 14.40% 55.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 42150 21.47% 77.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 39998 20.38% 97.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2642 1.35% 99.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1578 0.80% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 154 0.08% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 196498 # Number of insts issued each cycle -system.cpu1.iq.rate 1.295669 # Inst issue rate -system.cpu1.memDep0.conflictingLoads 43433 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 37289 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 88859 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 41782 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 131065 # number of misc regfile reads +system.cpu1.iq.issued_per_cycle::total 196288 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 120684 47.78% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 91955 36.41% 84.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 39941 15.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 252580 # Type of FU issued +system.cpu1.iq.rate 1.266732 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 190 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.000752 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 701640 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 261627 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 251253 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 252770 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 35691 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 1436 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 758 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 1747 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1477 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 298452 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 533 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 86261 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 40322 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 920 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1025 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 178 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 251613 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 85566 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 967 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 43243 # number of nop insts executed +system.cpu1.iew.exec_refs 125476 # number of memory reference insts executed +system.cpu1.iew.exec_branches 52279 # Number of branches executed +system.cpu1.iew.exec_stores 39910 # Number of stores executed +system.cpu1.iew.exec_rate 1.261882 # Inst execution rate +system.cpu1.iew.wb_sent 251386 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 251253 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 141847 # num instructions producing a value +system.cpu1.iew.wb_consumers 145498 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 1.260077 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.974907 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitCommittedInsts 290439 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 8011 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6919 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1102 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 187821 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.546361 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.941498 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80077 42.63% 42.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 52511 27.96% 70.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 7488 3.99% 74.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7738 4.12% 78.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 2462 1.31% 80.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 36475 19.42% 99.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 459 0.24% 99.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 127 0.07% 99.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 187821 # Number of insts commited each cycle +system.cpu1.commit.count 290439 # Number of instructions committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 124389 # Number of memory references committed +system.cpu1.commit.loads 84825 # Number of loads committed +system.cpu1.commit.membars 6207 # Number of memory barriers committed +system.cpu1.commit.branches 51732 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 198246 # Number of committed integer instructions. +system.cpu1.commit.function_calls 322 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 485200 # The number of ROB reads +system.cpu1.rob.rob_writes 598649 # The number of ROB writes +system.cpu1.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 3107 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 241708 # Number of Instructions Simulated +system.cpu1.committedInsts_total 241708 # Number of Instructions Simulated +system.cpu1.cpi 0.824942 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.824942 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.212207 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.212207 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 433901 # number of integer regfile reads +system.cpu1.int_regfile_writes 201135 # number of integer regfile writes +system.cpu1.fp_regfile_writes 64 # number of floating regfile writes +system.cpu1.misc_regfile_reads 127021 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.numCycles 199872 # number of cpu cycles simulated -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.BlockCycles 7004 # Number of cycles rename is blocking -system.cpu1.rename.CommittedMaps 204047 # Number of HB maps that are committed -system.cpu1.rename.IQFullEvents 57 # Number of times rename has blocked due to IQ full -system.cpu1.rename.IdleCycles 55307 # Number of cycles rename is idle -system.cpu1.rename.LSQFullEvents 48 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenameLookups 588542 # Number of register rename lookups that rename has made -system.cpu1.rename.RenamedInsts 308173 # Number of instructions processed by rename -system.cpu1.rename.RenamedOperands 212215 # Number of destination operands rename has renamed -system.cpu1.rename.RunCycles 112201 # Number of cycles rename is running -system.cpu1.rename.SquashCycles 1741 # Number of cycles rename is squashing -system.cpu1.rename.UnblockCycles 589 # Number of cycles rename is unblocking -system.cpu1.rename.UndoneMaps 8168 # Number of HB maps that are undone due to squashing -system.cpu1.rename.int_rename_lookups 588542 # Number of integer rename lookups -system.cpu1.rename.serializeStallCycles 13057 # count of cycles rename stalled for serializing inst -system.cpu1.rename.serializingInsts 954 # count of serializing insts renamed -system.cpu1.rename.skidInsts 2780 # count of insts added to the skid buffer -system.cpu1.rename.tempSerializingInsts 1009 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 493050 # The number of ROB reads -system.cpu1.rob.rob_writes 613675 # The number of ROB writes -system.cpu1.timesIdled 291 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.icache.replacements 335 # number of replacements +system.cpu1.icache.tagsinuse 81.445548 # Cycle average of tags in use +system.cpu1.icache.total_refs 20780 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 442 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 47.013575 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 81.445548 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.159073 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits 20780 # number of ReadReq hits +system.cpu1.icache.demand_hits 20780 # number of demand (read+write) hits +system.cpu1.icache.overall_hits 20780 # number of overall hits +system.cpu1.icache.ReadReq_misses 487 # number of ReadReq misses +system.cpu1.icache.demand_misses 487 # number of demand (read+write) misses +system.cpu1.icache.overall_misses 487 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7348000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7348000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7348000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses 21267 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses 21267 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses 21267 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate 0.022899 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate 0.022899 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate 0.022899 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency 15088.295688 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency 15088.295688 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency 15088.295688 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 45 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 442 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency 5515000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5515000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5515000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.020783 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate 0.020783 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate 0.020783 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12477.375566 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 2 # number of replacements +system.cpu1.dcache.tagsinuse 15.853389 # Cycle average of tags in use +system.cpu1.dcache.total_refs 45287 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1561.620690 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 24.109583 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -8.256194 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.047089 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::1 -0.016125 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits 49422 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits 39377 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits 88799 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits 88799 # number of overall hits +system.cpu1.dcache.ReadReq_misses 438 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses 121 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses 559 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses 559 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 9255000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 2991000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency 1250500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency 12246000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 12246000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses 49860 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses 39498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses 89358 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses 89358 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate 0.008785 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate 0.003063 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate 0.787879 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate 0.006256 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate 0.006256 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency 21130.136986 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 24719.008264 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency 24048.076923 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency 21906.976744 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency 21906.976744 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks 1 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 300 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 103 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2111500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1675000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency 1094500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3786500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3786500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003129 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002608 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.787879 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate 0.002898 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate 0.002898 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13535.256410 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16262.135922 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 21048.076923 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.numCycles 199106 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.BPredUnit.lookups 57971 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 55658 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 57356 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 55221 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 55906 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 58100 # Number of BTB lookups -system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 1096 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 58228 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 58228 # Number of BP lookups -system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.branchMispredicts 1096 # The number of times a branch was mispredicted -system.cpu2.commit.branches 55433 # Number of branches committed -system.cpu2.commit.bw_lim_events 499 # number cycles where commit BW limit reached -system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.commitCommittedInsts 315535 # The number of committed instructions -system.cpu2.commit.commitNonSpecStalls 5463 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 8360 # The number of squashed insts skipped by commit -system.cpu2.commit.committed_per_cycle::samples 185729 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.698900 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.997080 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 70586 38.00% 38.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 56238 30.28% 68.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 7477 4.03% 72.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6262 3.37% 75.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 2451 1.32% 77.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 41665 22.43% 99.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 421 0.23% 99.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 499 0.27% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 185729 # Number of insts commited each cycle -system.cpu2.commit.count 315535 # Number of instructions committed -system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.function_calls 0 # Number of function calls committed. -system.cpu2.commit.int_insts 215944 # Number of committed integer instructions. -system.cpu2.commit.loads 93671 # Number of loads committed -system.cpu2.commit.membars 4747 # Number of memory barriers committed -system.cpu2.commit.refs 138392 # Number of memory references committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.committedInsts 264567 # Number of Instructions Simulated -system.cpu2.committedInsts_total 264567 # Number of Instructions Simulated -system.cpu2.cpi 0.754365 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.754365 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 53583 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 22410.944206 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15243.827160 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 53117 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 10443500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.008697 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 466 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 304 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 2469500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu2.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 24534.482759 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21534.482759 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 1423000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_rate 0.828571 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 1249000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.828571 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 44651 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 23987.804878 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15485.714286 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 44528 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 2950500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.002755 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 1626000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002352 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 1682.766667 # Average number of references to valid blocks. -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 98234 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 22740.237691 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15338.951311 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 97645 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.005996 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 589 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 322 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 4095500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.002718 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_blocks::0 27.083354 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -9.389236 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.052897 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.018338 # Average percentage of cache occupancy -system.cpu2.dcache.overall_accesses 98234 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 22740.237691 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15338.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 97645 # number of overall hits -system.cpu2.dcache.overall_miss_latency 13394000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.005996 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 589 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 322 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 4095500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.002718 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 17.694118 # Cycle average of tags in use -system.cpu2.dcache.total_refs 50483 # Total number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.decode.BlockedCycles 20050 # Number of cycles decode is blocked -system.cpu2.decode.DecodedInsts 327820 # Number of instructions handled by decode -system.cpu2.decode.IdleCycles 49005 # Number of cycles decode is idle -system.cpu2.decode.RunCycles 112255 # Number of cycles decode is running -system.cpu2.decode.SquashCycles 1781 # Number of cycles decode is squashing -system.cpu2.decode.UnblockCycles 4418 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 58228 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 18194 # Number of cache lines fetched -system.cpu2.fetch.Cycles 117037 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 328955 # Number of instructions fetch has processed -system.cpu2.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.291753 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 18194 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 55906 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.648236 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 194114 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.694649 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.084542 # Number of instructions fetched each cycle (Total) +system.cpu2.BPredUnit.usedRAS 508 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 18228 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 327195 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 57971 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 55729 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 116612 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1192 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.CacheLines 18228 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 193972 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.686816 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.080601 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 77077 39.71% 39.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 59674 30.74% 70.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5837 3.01% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 2794 1.44% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1893 0.98% 75.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 42627 21.96% 97.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 2458 1.27% 99.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 262 0.13% 99.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1492 0.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 77360 39.88% 39.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 59528 30.69% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5848 3.01% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 2830 1.46% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1905 0.98% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 42329 21.82% 97.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 2448 1.26% 99.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 264 0.14% 99.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1460 0.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 194114 # Number of instructions fetched each cycle (Total) -system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.icache.ReadReq_accesses 18194 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 21635.330579 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18220.454545 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 17710 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 10471500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.026602 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 484 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 8017000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.024184 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 40.250000 # Average number of references to valid blocks. -system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 18194 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 21635.330579 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18220.454545 # average overall mshr miss latency -system.cpu2.icache.demand_hits 17710 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 10471500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.026602 # miss rate for demand accesses -system.cpu2.icache.demand_misses 484 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 8017000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.024184 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_blocks::0 90.442244 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.176645 # Average percentage of cache occupancy -system.cpu2.icache.overall_accesses 18194 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 21635.330579 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18220.454545 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 17710 # number of overall hits -system.cpu2.icache.overall_miss_latency 10471500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.026602 # miss rate for overall accesses -system.cpu2.icache.overall_misses 484 # number of overall misses -system.cpu2.icache.overall_mshr_hits 44 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 8017000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.024184 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 440 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 330 # number of replacements -system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 90.442244 # Cycle average of tags in use -system.cpu2.icache.total_refs 17710 # Total number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 5466 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.branchMispredicts 1198 # Number of branch mispredicts detected at execute -system.cpu2.iew.exec_branches 55984 # Number of branches executed -system.cpu2.iew.exec_nop 47025 # number of nop insts executed -system.cpu2.iew.exec_rate 1.368298 # Inst execution rate -system.cpu2.iew.exec_refs 139522 # number of memory reference insts executed -system.cpu2.iew.exec_stores 45069 # Number of stores executed -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 95225 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 555 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 45493 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 323925 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 94453 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 959 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 273085 # Number of executed instructions -system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing -system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread0.forwLoads 40852 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.squashedLoads 1554 # Number of loads squashed -system.cpu2.iew.lsq.thread0.squashedStores 772 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 996 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.wb_consumers 159565 # num instructions consuming a value -system.cpu2.iew.wb_count 272710 # cumulative count of insts written-back -system.cpu2.iew.wb_fanout 0.977063 # average fanout of values written-back -system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.wb_producers 155905 # num instructions producing a value -system.cpu2.iew.wb_rate 1.366419 # insts written-back per cycle -system.cpu2.iew.wb_sent 272842 # cumulative count of insts sent to commit -system.cpu2.int_regfile_reads 476036 # number of integer regfile reads -system.cpu2.int_regfile_writes 220349 # number of integer regfile writes -system.cpu2.ipc 1.325619 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.325619 # IPC: Total IPC of All Threads -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 129561 47.28% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 99383 36.27% 83.54% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 45100 16.46% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274044 # Type of FU issued -system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu2.iq.fu_busy_cnt 205 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.000748 # FU busy rate (busy events/executed inst) -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 5.85% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 62 30.24% 36.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 131 63.90% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.int_alu_accesses 274249 # Number of integer alu accesses -system.cpu2.iq.int_inst_queue_reads 742408 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_wakeup_accesses 272710 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.int_inst_queue_writes 283590 # Number of integer instruction queue writes -system.cpu2.iq.iqInstsAdded 270836 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 274044 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 6661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.fetch.rateDist::total 193972 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291156 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.643321 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 48904 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 20328 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 111841 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4382 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1806 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 325997 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1806 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 49533 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6147 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13457 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 115712 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 606 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 324330 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 65 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 224740 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 625107 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 625107 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 216561 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 8179 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 949 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1011 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2760 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 94652 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 45182 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 45774 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 40713 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 269361 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6099 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 272571 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 601 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 6335 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.issued_per_cycle::samples 194114 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.411768 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.293131 # Number of insts issued each cycle +system.cpu2.iq.iqSquashedInstsExamined 6651 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 6299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 621 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 193972 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.405208 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.293243 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73286 37.75% 37.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23867 12.30% 50.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 47309 24.37% 74.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 45216 23.29% 97.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2634 1.36% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1540 0.79% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73708 38.00% 38.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23872 12.31% 50.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 47052 24.26% 74.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 44924 23.16% 97.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2620 1.35% 99.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1535 0.79% 99.87% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 168 0.09% 99.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 84 0.04% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 194114 # Number of insts issued each cycle -system.cpu2.iq.rate 1.373104 # Inst issue rate -system.cpu2.memDep0.conflictingLoads 46039 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 41011 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 95225 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 45493 # Number of stores inserted to the mem dependence unit. -system.cpu2.misc_regfile_reads 141060 # number of misc regfile reads +system.cpu2.iq.issued_per_cycle::total 193972 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 12 5.97% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 58 28.86% 34.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 131 65.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 128963 47.31% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.31% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 98810 36.25% 83.56% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 44798 16.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 272571 # Type of FU issued +system.cpu2.iq.rate 1.368974 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 201 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.000737 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 739316 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 282139 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 271248 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 272772 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 40559 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 1552 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 752 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1706 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 322227 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 522 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 94652 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 45182 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 1035 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1222 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 271613 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 93867 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 46767 # number of nop insts executed +system.cpu2.iew.exec_refs 138637 # number of memory reference insts executed +system.cpu2.iew.exec_branches 55708 # Number of branches executed +system.cpu2.iew.exec_stores 44770 # Number of stores executed +system.cpu2.iew.exec_rate 1.364163 # Inst execution rate +system.cpu2.iew.wb_sent 271381 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 271248 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 155012 # num instructions producing a value +system.cpu2.iew.wb_consumers 158673 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 1.362330 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.976927 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitCommittedInsts 313840 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 8384 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5478 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1119 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 185456 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.692261 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.994391 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 70838 38.20% 38.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 55984 30.19% 68.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 7465 4.03% 72.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6288 3.39% 75.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 2454 1.32% 77.12% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 41414 22.33% 99.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 401 0.22% 99.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 126 0.07% 99.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 185456 # Number of insts commited each cycle +system.cpu2.commit.count 313840 # Number of instructions committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 137530 # Number of memory references committed +system.cpu2.commit.loads 93100 # Number of loads committed +system.cpu2.commit.membars 4761 # Number of memory barriers committed +system.cpu2.commit.branches 55156 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 214804 # Number of committed integer instructions. +system.cpu2.commit.function_calls 322 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 486 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 506607 # The number of ROB reads +system.cpu2.rob.rob_writes 646257 # The number of ROB writes +system.cpu2.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5134 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.committedInsts 263136 # Number of Instructions Simulated +system.cpu2.committedInsts_total 263136 # Number of Instructions Simulated +system.cpu2.cpi 0.756666 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.756666 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.321587 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.321587 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 473358 # number of integer regfile reads +system.cpu2.int_regfile_writes 219156 # number of integer regfile writes +system.cpu2.fp_regfile_writes 64 # number of floating regfile writes +system.cpu2.misc_regfile_reads 140181 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.numCycles 199580 # number of cpu cycles simulated -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.rename.BlockCycles 6241 # Number of cycles rename is blocking -system.cpu2.rename.CommittedMaps 217715 # Number of HB maps that are committed -system.cpu2.rename.IQFullEvents 58 # Number of times rename has blocked due to IQ full -system.cpu2.rename.IdleCycles 49628 # Number of cycles rename is idle -system.cpu2.rename.LSQFullEvents 58 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenameLookups 628783 # Number of register rename lookups that rename has made -system.cpu2.rename.RenamedInsts 326092 # Number of instructions processed by rename -system.cpu2.rename.RenamedOperands 225995 # Number of destination operands rename has renamed -system.cpu2.rename.RunCycles 116192 # Number of cycles rename is running -system.cpu2.rename.SquashCycles 1781 # Number of cycles rename is squashing -system.cpu2.rename.UnblockCycles 614 # Number of cycles rename is unblocking -system.cpu2.rename.UndoneMaps 8280 # Number of HB maps that are undone due to squashing -system.cpu2.rename.int_rename_lookups 628783 # Number of integer rename lookups -system.cpu2.rename.serializeStallCycles 13053 # count of cycles rename stalled for serializing inst -system.cpu2.rename.serializingInsts 948 # count of serializing insts renamed -system.cpu2.rename.skidInsts 2856 # count of insts added to the skid buffer -system.cpu2.rename.tempSerializingInsts 1003 # count of temporary serializing insts renamed -system.cpu2.rob.rob_reads 508538 # The number of ROB reads -system.cpu2.rob.rob_writes 649574 # The number of ROB writes -system.cpu2.timesIdled 302 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.icache.replacements 333 # number of replacements +system.cpu2.icache.tagsinuse 86.095246 # Cycle average of tags in use +system.cpu2.icache.total_refs 17739 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 40.500000 # Average number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.occ_blocks::0 86.095246 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.168155 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits 17739 # number of ReadReq hits +system.cpu2.icache.demand_hits 17739 # number of demand (read+write) hits +system.cpu2.icache.overall_hits 17739 # number of overall hits +system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses +system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses +system.cpu2.icache.overall_misses 489 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency 10440000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency 10440000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency 10440000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses 18228 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses 18228 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses 18228 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate 0.026827 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate 0.026827 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate 0.026827 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency 21349.693252 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency 21349.693252 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency 21349.693252 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits 51 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses 438 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses 438 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.ReadReq_mshr_miss_latency 8036500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 8036500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 8036500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.024029 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate 0.024029 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate 0.024029 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18348.173516 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.replacements 2 # number of replacements +system.cpu2.dcache.tagsinuse 18.718664 # Cycle average of tags in use +system.cpu2.dcache.total_refs 50172 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1672.400000 # Average number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.occ_blocks::0 27.030706 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -8.312042 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.052794 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::1 -0.016234 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits 52844 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits 44237 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits 97081 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits 97081 # number of overall hits +system.cpu2.dcache.ReadReq_misses 446 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses 122 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses 568 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses 568 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency 10164500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency 2987000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 1380500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency 13151500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency 13151500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses 53290 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 44359 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses 97649 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses 97649 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate 0.008369 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate 0.002750 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate 0.005817 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate 0.005817 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency 22790.358744 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency 24483.606557 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 23398.305085 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency 23154.049296 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency 23154.049296 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.writebacks 1 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits 304 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits 304 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 2394500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 1203500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 4063500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 4063500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003002 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002345 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate 0.002704 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate 0.002704 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14965.625000 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16048.076923 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 20398.305085 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.numCycles 198838 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.BPredUnit.lookups 46930 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 44609 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 46370 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 44223 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 43772 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 45981 # Number of BTB lookups -system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 1096 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 46026 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 46026 # Number of BP lookups -system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.branchMispredicts 1096 # The number of times a branch was mispredicted -system.cpu3.commit.branches 43201 # Number of branches committed -system.cpu3.commit.bw_lim_events 486 # number cycles where commit BW limit reached -system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.commitCommittedInsts 234599 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 9238 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 8312 # The number of squashed insts skipped by commit -system.cpu3.commit.committed_per_cycle::samples 187492 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.251248 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.795283 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 96787 51.62% 51.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44013 23.47% 75.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 7489 3.99% 79.09% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10030 5.35% 84.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 2457 1.31% 85.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 25706 13.71% 99.46% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 396 0.21% 99.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 128 0.07% 99.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 187492 # Number of insts commited each cycle -system.cpu3.commit.count 234599 # Number of instructions committed -system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.function_calls 0 # Number of function calls committed. -system.cpu3.commit.int_insts 159474 # Number of committed integer instructions. -system.cpu3.commit.loads 65432 # Number of loads committed -system.cpu3.commit.membars 8520 # Number of memory barriers committed -system.cpu3.commit.refs 94154 # Number of memory references committed -system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.committedInsts 192092 # Number of Instructions Simulated -system.cpu3.committedInsts_total 192092 # Number of Instructions Simulated -system.cpu3.cpi 1.037576 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.037576 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 41296 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 22460.431655 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14148.484848 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 40879 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 9366000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.010098 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 417 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2334500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003996 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 26552.631579 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23552.631579 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1513500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.791667 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_miss_latency 1342500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.791667 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 57 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 28650 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23359.504132 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15274.509804 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 28529 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2826500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.004223 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 121 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1558000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003560 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 1150.100000 # Average number of references to valid blocks. -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 69946 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 22662.639405 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14578.651685 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 69408 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 12192500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.007692 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 538 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 271 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 3892500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.003817 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_blocks::0 24.182757 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -8.332061 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.047232 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.016274 # Average percentage of cache occupancy -system.cpu3.dcache.overall_accesses 69946 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 22662.639405 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14578.651685 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 69408 # number of overall hits -system.cpu3.dcache.overall_miss_latency 12192500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.007692 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 538 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 271 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 3892500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.003817 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 15.850697 # Cycle average of tags in use -system.cpu3.dcache.total_refs 34503 # Total number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.BlockedCycles 23404 # Number of cycles decode is blocked -system.cpu3.decode.DecodedInsts 246917 # Number of instructions handled by decode -system.cpu3.decode.IdleCycles 67894 # Number of cycles decode is idle -system.cpu3.decode.RunCycles 88329 # Number of cycles decode is running -system.cpu3.decode.SquashCycles 1781 # Number of cycles decode is squashing -system.cpu3.decode.UnblockCycles 7864 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 46026 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 26017 # Number of cache lines fetched -system.cpu3.fetch.Cycles 96566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 248038 # Number of instructions fetch has processed +system.cpu3.BPredUnit.usedRAS 506 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu3.fetch.icacheStallCycles 25370 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 254105 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 46930 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 44729 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 98091 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1197 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.230927 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 26017 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 43772 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.244483 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 195889 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.266217 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.878921 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.CacheLines 25370 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 195684 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.298548 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.898359 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 99323 50.70% 50.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51378 26.23% 76.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9749 4.98% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 2746 1.40% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1924 0.98% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 26575 13.57% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2472 1.26% 99.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 255 0.13% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 1467 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 97593 49.87% 49.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52035 26.59% 76.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9385 4.80% 81.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 2730 1.40% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1923 0.98% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 27840 14.23% 97.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2474 1.26% 99.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 258 0.13% 99.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 1446 0.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 195889 # Number of instructions fetched each cycle (Total) -system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.icache.ReadReq_accesses 26017 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 14208.939709 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11549.661400 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 25536 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 6834500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.018488 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 5116500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.017027 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 57.643341 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 26017 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 14208.939709 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11549.661400 # average overall mshr miss latency -system.cpu3.icache.demand_hits 25536 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 6834500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.018488 # miss rate for demand accesses -system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 5116500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.017027 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_blocks::0 85.462768 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.166919 # Average percentage of cache occupancy -system.cpu3.icache.overall_accesses 26017 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 14208.939709 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11549.661400 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 25536 # number of overall hits -system.cpu3.icache.overall_miss_latency 6834500 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.018488 # miss rate for overall accesses -system.cpu3.icache.overall_misses 481 # number of overall misses -system.cpu3.icache.overall_mshr_hits 38 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 5116500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.017027 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 443 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 331 # number of replacements -system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks. -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 85.462768 # Cycle average of tags in use -system.cpu3.icache.total_refs 25536 # Total number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 3421 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute -system.cpu3.iew.exec_branches 43744 # Number of branches executed -system.cpu3.iew.exec_nop 34814 # number of nop insts executed -system.cpu3.iew.exec_rate 1.024765 # Inst execution rate -system.cpu3.iew.exec_refs 95207 # number of memory reference insts executed -system.cpu3.iew.exec_stores 29059 # Number of stores executed -system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.iewBlockCycles 1619 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 66949 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 934 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 572 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 29464 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 242942 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 66148 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 960 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 204246 # Number of executed instructions -system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing -system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread0.forwLoads 24834 # Number of loads that had data forwarded from stores -system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.squashedLoads 1517 # Number of loads squashed -system.cpu3.iew.lsq.thread0.squashedStores 742 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 182 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 1011 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.wb_consumers 115240 # num instructions consuming a value -system.cpu3.iew.wb_count 203888 # cumulative count of insts written-back -system.cpu3.iew.wb_fanout 0.968327 # average fanout of values written-back -system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.wb_producers 111590 # num instructions producing a value -system.cpu3.iew.wb_rate 1.022969 # insts written-back per cycle -system.cpu3.iew.wb_sent 204019 # cumulative count of insts sent to commit -system.cpu3.int_regfile_reads 343072 # number of integer regfile reads -system.cpu3.int_regfile_writes 159978 # number of integer regfile writes -system.cpu3.ipc 0.963785 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.963785 # IPC: Total IPC of All Threads -system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 101269 49.35% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 74848 36.47% 85.82% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29089 14.18% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 205206 # Type of FU issued -system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu3.iq.fu_busy_cnt 188 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.000916 # FU busy rate (busy events/executed inst) -system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 5.85% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.85% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 46 24.47% 30.32% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 131 69.68% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.int_alu_accesses 205394 # Number of integer alu accesses -system.cpu3.iq.int_inst_queue_reads 606491 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_wakeup_accesses 203888 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.int_inst_queue_writes 214747 # Number of integer instruction queue writes -system.cpu3.iq.iqInstsAdded 198217 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 205206 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 9911 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 6590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.fetch.rateDist::total 195684 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.236021 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.277950 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 66043 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 23415 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 90085 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7606 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1806 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 252876 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1806 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 66691 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 9403 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13294 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 97176 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 585 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 251157 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 61 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 39 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 170213 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 465014 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 465014 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 162080 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 8133 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 958 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1016 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 2718 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69072 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 30693 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 34709 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26217 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 203693 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9545 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 210364 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 673 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 6253 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.issued_per_cycle::samples 195889 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.047563 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.235617 # Number of insts issued each cycle +system.cpu3.iq.iqSquashedInstsExamined 6526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 6179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 195684 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.075019 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.244116 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 95806 48.91% 48.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 35106 17.92% 66.83% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31374 16.02% 82.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 29208 14.91% 97.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 2591 1.32% 99.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1562 0.80% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 150 0.08% 99.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 94148 48.11% 48.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 34086 17.42% 65.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 32603 16.66% 82.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30459 15.57% 97.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 2587 1.32% 99.08% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1559 0.80% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 152 0.08% 99.95% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 80 0.04% 99.99% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 195889 # Number of insts issued each cycle -system.cpu3.iq.rate 1.029582 # Inst issue rate -system.cpu3.memDep0.conflictingLoads 33826 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24974 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 66949 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29464 # Number of stores inserted to the mem dependence unit. -system.cpu3.misc_regfile_reads 96736 # number of misc regfile reads +system.cpu3.iq.issued_per_cycle::total 195684 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 52 26.80% 32.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 131 67.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 103392 49.15% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.15% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 76648 36.44% 85.58% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 30324 14.42% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 210364 # Type of FU issued +system.cpu3.iq.rate 1.057967 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 194 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.000922 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 616608 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 219792 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 209060 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 210558 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 26077 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 1504 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 734 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1713 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 248952 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 576 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69072 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 30693 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 930 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 49 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1047 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 172 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 209414 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68288 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 950 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 35714 # number of nop insts executed +system.cpu3.iew.exec_refs 98584 # number of memory reference insts executed +system.cpu3.iew.exec_branches 44648 # Number of branches executed +system.cpu3.iew.exec_stores 30296 # Number of stores executed +system.cpu3.iew.exec_rate 1.053189 # Inst execution rate +system.cpu3.iew.wb_sent 209192 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 209060 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 114958 # num instructions producing a value +system.cpu3.iew.wb_consumers 118605 # num instructions consuming a value +system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu3.iew.wb_rate 1.051409 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969251 # average fanout of values written-back +system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu3.commit.commitCommittedInsts 240668 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 8282 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8898 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1124 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 187150 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.285963 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.815684 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 94628 50.56% 50.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 44931 24.01% 74.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 7495 4.00% 78.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9690 5.18% 83.75% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 2458 1.31% 85.07% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26940 14.39% 99.46% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 395 0.21% 99.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 187150 # Number of insts commited each cycle +system.cpu3.commit.count 240668 # Number of instructions committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 97527 # Number of memory references committed +system.cpu3.commit.loads 67568 # Number of loads committed +system.cpu3.commit.membars 8180 # Number of memory barriers committed +system.cpu3.commit.branches 44100 # Number of branches committed +system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 163745 # Number of committed integer instructions. +system.cpu3.commit.function_calls 322 # Number of function calls committed. +system.cpu3.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu3.rob.rob_reads 435029 # The number of ROB reads +system.cpu3.rob.rob_writes 499708 # The number of ROB writes +system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 3154 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.committedInsts 197602 # Number of Instructions Simulated +system.cpu3.committedInsts_total 197602 # Number of Instructions Simulated +system.cpu3.cpi 1.006255 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.006255 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.993784 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.993784 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 353198 # number of integer regfile reads +system.cpu3.int_regfile_writes 164587 # number of integer regfile writes +system.cpu3.fp_regfile_writes 64 # number of floating regfile writes +system.cpu3.misc_regfile_reads 100115 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.numCycles 199310 # number of cpu cycles simulated -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.rename.BlockCycles 9536 # Number of cycles rename is blocking -system.cpu3.rename.CommittedMaps 157468 # Number of HB maps that are committed -system.cpu3.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full -system.cpu3.rename.IdleCycles 68516 # Number of cycles rename is idle -system.cpu3.rename.LSQFullEvents 39 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenameLookups 451555 # Number of register rename lookups that rename has made -system.cpu3.rename.RenamedInsts 245166 # Number of instructions processed by rename -system.cpu3.rename.RenamedOperands 165603 # Number of destination operands rename has renamed -system.cpu3.rename.RunCycles 95731 # Number of cycles rename is running -system.cpu3.rename.SquashCycles 1781 # Number of cycles rename is squashing -system.cpu3.rename.UnblockCycles 570 # Number of cycles rename is unblocking -system.cpu3.rename.UndoneMaps 8135 # Number of HB maps that are undone due to squashing -system.cpu3.rename.int_rename_lookups 451555 # Number of integer rename lookups -system.cpu3.rename.serializeStallCycles 13138 # count of cycles rename stalled for serializing inst -system.cpu3.rename.serializingInsts 958 # count of serializing insts renamed -system.cpu3.rename.skidInsts 2735 # count of insts added to the skid buffer -system.cpu3.rename.tempSerializingInsts 1009 # count of temporary serializing insts renamed -system.cpu3.rob.rob_reads 429330 # The number of ROB reads -system.cpu3.rob.rob_writes 487605 # The number of ROB writes -system.cpu3.timesIdled 294 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 73164.893617 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 573125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 529038.461538 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 573125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1748453.355155 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40293.893130 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6877500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.cpu3.icache.replacements 334 # number of replacements +system.cpu3.icache.tagsinuse 83.539668 # Cycle average of tags in use +system.cpu3.icache.total_refs 24889 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 440 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 56.565909 # Average number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.occ_blocks::0 83.539668 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.163163 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits 24889 # number of ReadReq hits +system.cpu3.icache.demand_hits 24889 # number of demand (read+write) hits +system.cpu3.icache.overall_hits 24889 # number of overall hits +system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses +system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses +system.cpu3.icache.overall_misses 481 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency 6766000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency 6766000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency 6766000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses 25370 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses 25370 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses 25370 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate 0.018959 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate 0.018959 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate 0.018959 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency 14066.528067 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency 14066.528067 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency 14066.528067 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits 41 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses 440 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.017343 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate 0.017343 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate 0.017343 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11518.181818 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.replacements 2 # number of replacements +system.cpu3.dcache.tagsinuse 16.417900 # Cycle average of tags in use +system.cpu3.dcache.total_refs 35718 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1190.600000 # Average number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.occ_blocks::0 24.989455 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -8.571555 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.048808 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::1 -0.016741 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits 41747 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits 29763 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits 71510 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits 71510 # number of overall hits +system.cpu3.dcache.ReadReq_misses 446 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses 570 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses 570 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency 9927500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency 2778000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency 1471000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency 12705500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency 12705500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses 42193 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses 29887 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses 72080 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses 72080 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate 0.004149 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate 0.007908 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate 0.007908 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency 22258.968610 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency 22403.225806 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency 25362.068966 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency 22290.350877 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency 22290.350877 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.writebacks 1 # number of writebacks +system.cpu3.dcache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits 291 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits 291 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses 279 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 2494000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency 1504000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency 1297000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency 3998000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency 3998000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004124 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003513 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate 0.003871 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate 0.003871 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14333.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14323.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22362.068966 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.replacements 0 # number of replacements +system.l2c.tagsinuse 428.707153 # Cycle average of tags in use +system.l2c.total_refs 1488 # Total number of references to valid blocks. +system.l2c.sampled_refs 521 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.856046 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 348.158908 # Average occupied blocks per context +system.l2c.occ_blocks::1 9.356931 # Average occupied blocks per context +system.l2c.occ_blocks::2 63.539276 # Average occupied blocks per context +system.l2c.occ_blocks::3 2.442412 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.209626 # Average occupied blocks per context +system.l2c.occ_percent::0 0.005312 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.000143 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.000970 # Average percentage of cache occupancy +system.l2c.occ_percent::3 0.000037 # Average percentage of cache occupancy +system.l2c.occ_percent::4 0.000079 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 232 # number of ReadReq hits +system.l2c.ReadReq_hits::1 440 # number of ReadReq hits +system.l2c.ReadReq_hits::2 370 # number of ReadReq hits +system.l2c.ReadReq_hits::3 449 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1491 # number of ReadReq hits +system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.demand_hits::0 232 # number of demand (read+write) hits +system.l2c.demand_hits::1 440 # number of demand (read+write) hits +system.l2c.demand_hits::2 370 # number of demand (read+write) hits +system.l2c.demand_hits::3 449 # number of demand (read+write) hits +system.l2c.demand_hits::total 1491 # number of demand (read+write) hits +system.l2c.overall_hits::0 232 # number of overall hits +system.l2c.overall_hits::1 440 # number of overall hits +system.l2c.overall_hits::2 370 # number of overall hits +system.l2c.overall_hits::3 449 # number of overall hits +system.l2c.overall_hits::total 1491 # number of overall hits +system.l2c.ReadReq_misses::0 425 # number of ReadReq misses +system.l2c.ReadReq_misses::1 15 # number of ReadReq misses +system.l2c.ReadReq_misses::2 82 # number of ReadReq misses +system.l2c.ReadReq_misses::3 4 # number of ReadReq misses +system.l2c.ReadReq_misses::total 526 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 25 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 93 # number of UpgradeReq misses system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5278500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 454 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 63645.879733 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1905133.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 348500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 7144250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9461529.213066 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 240 # number of ReadReq hits -system.l2c.ReadReq_hits::1 438 # number of ReadReq hits -system.l2c.ReadReq_hits::2 372 # number of ReadReq hits -system.l2c.ReadReq_hits::3 452 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1502 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28577000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.033113 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.180617 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.008772 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.874170 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 449 # number of ReadReq misses -system.l2c.ReadReq_misses::1 15 # number of ReadReq misses -system.l2c.ReadReq_misses::2 82 # number of ReadReq misses -system.l2c.ReadReq_misses::3 4 # number of ReadReq misses -system.l2c.ReadReq_misses::total 550 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 21720000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.788099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.198675 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.196035 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.190789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.373599 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 543 # number of ReadReq MSHR misses +system.l2c.demand_misses::0 519 # number of demand (read+write) misses +system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::2 95 # number of demand (read+write) misses +system.l2c.demand_misses::3 16 # number of demand (read+write) misses +system.l2c.demand_misses::total 657 # number of demand (read+write) misses +system.l2c.overall_misses::0 519 # number of overall misses +system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::2 95 # number of overall misses +system.l2c.overall_misses::3 16 # number of overall misses +system.l2c.overall_misses::total 657 # number of overall misses +system.l2c.ReadReq_miss_latency 27341000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6879000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 34220000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 34220000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 657 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 455 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 453 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 25 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 97 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 6500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 7428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26711.180124 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 96 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 751 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 465 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 465 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 751 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 465 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 465 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.646880 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.032967 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.181416 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.008830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.870093 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 24 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 94 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3760000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 3.241379 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.916667 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 4.086957 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 4.476190 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.721193 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 94 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.750459 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.691079 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.057816 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.204301 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.034409 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.987604 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.691079 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.057816 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.204301 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.034409 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.987604 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 64331.764706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1822733.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 333426.829268 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 6835250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9055741.927308 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 6240 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 8210.526316 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 27233.135011 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 73180.851064 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 573250 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 529153.846154 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 573250 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1748834.697218 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 65934.489403 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1267407.407407 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 360210.526316 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 2138750 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3832302.423126 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 65934.489403 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1267407.407407 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 360210.526316 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 2138750 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3832302.423126 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 783 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 465 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2183 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 65293.738490 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1313129.629630 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 373205.263158 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 2215906.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3967534.881277 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40057.121662 # average overall mshr miss latency -system.l2c.demand_hits::0 240 # number of demand (read+write) hits -system.l2c.demand_hits::1 438 # number of demand (read+write) hits -system.l2c.demand_hits::2 372 # number of demand (read+write) hits -system.l2c.demand_hits::3 452 # number of demand (read+write) hits -system.l2c.demand_hits::total 1502 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35454500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.693487 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.058065 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.203426 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.034188 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.989165 # miss rate for demand accesses -system.l2c.demand_misses::0 543 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses -system.l2c.demand_misses::2 95 # number of demand (read+write) misses -system.l2c.demand_misses::3 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 681 # number of demand (read+write) misses +system.l2c.writebacks 0 # number of writebacks +system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 26998500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.860792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.449462 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.443255 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.440171 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.193680 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 674 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 364.492731 # Average occupied blocks per context -system.l2c.occ_blocks::1 10.237276 # Average occupied blocks per context -system.l2c.occ_blocks::2 62.878855 # Average occupied blocks per context -system.l2c.occ_blocks::3 2.477387 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.202251 # Average occupied blocks per context -system.l2c.occ_percent::0 0.005562 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000156 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000959 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000038 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000079 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 783 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 465 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 468 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2183 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 65293.738490 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1313129.629630 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 373205.263158 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2215906.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3967534.881277 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40057.121662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 240 # number of overall hits -system.l2c.overall_hits::1 438 # number of overall hits -system.l2c.overall_hits::2 372 # number of overall hits -system.l2c.overall_hits::3 452 # number of overall hits -system.l2c.overall_hits::total 1502 # number of overall hits -system.l2c.overall_miss_latency 35454500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.693487 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.058065 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.203426 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.034188 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.989165 # miss rate for overall accesses -system.l2c.overall_misses::0 543 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses -system.l2c.overall_misses::2 95 # number of overall misses -system.l2c.overall_misses::3 16 # number of overall misses -system.l2c.overall_misses::total 681 # number of overall misses system.l2c.overall_mshr_hits 7 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 26998500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.860792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.449462 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.443255 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.440171 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.193680 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 674 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses 519 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 93 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 650 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 650 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 545 # Sample count of references to valid blocks. +system.l2c.ReadReq_mshr_miss_latency 20754000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 3720500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5279000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 26033000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 26033000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.789954 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.140659 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.148230 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.145695 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.224539 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 3.206897 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 3.720000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.043478 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 4.894737 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.865112 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.865513 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.391863 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.397849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.397849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.053075 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.865513 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.391863 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.397849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.397849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.053075 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 39988.439306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.376344 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 445.288501 # Cycle average of tags in use -system.l2c.total_refs 1499 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |