Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

src/SConscript:
    Split off FuncUnits from old FUPool so I'm not including encumbered code.  This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
    Include the func unit file that's not in the encumbered directory.

--HG--
extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241

5 files changed, 291 insertions, 3 deletions

diff --git a/src/SConscript b/src/SConscript
index a1c18711c..0f21891c4 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -85,6 +85,7 @@ base_sources = Split('''
 	cpu/base.cc
 	cpu/cpuevent.cc
 	cpu/exetrace.cc
+        cpu/func_unit.cc
         cpu/op_class.cc
 	cpu/pc_event.cc
         cpu/quiesce_event.cc
@@ -93,8 +94,6 @@ base_sources = Split('''
         cpu/simple_thread.cc
         cpu/thread_state.cc
 
-        encumbered/cpu/full/fu_pool.cc
-        
         mem/bridge.cc
         mem/bus.cc
         mem/connector.cc
diff --git a/src/cpu/func_unit.cc b/src/cpu/func_unit.cc
new file mode 100644
index 000000000..c20578a43
--- /dev/null
+++ b/src/cpu/func_unit.cc
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2002-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Raasch
+ */
+
+#include <sstream>
+
+#include "base/misc.hh"
+#include "cpu/func_unit.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+
+
+////////////////////////////////////////////////////////////////////////////
+//
+//  The funciton unit
+//
+FuncUnit::FuncUnit()
+{
+    capabilityList.reset();
+}
+
+
+//  Copy constructor
+FuncUnit::FuncUnit(const FuncUnit &fu)
+{
+
+    for (int i = 0; i < Num_OpClasses; ++i) {
+        opLatencies[i] = fu.opLatencies[i];
+        issueLatencies[i] = fu.issueLatencies[i];
+    }
+
+    capabilityList = fu.capabilityList;
+}
+
+
+void
+FuncUnit::addCapability(OpClass cap, unsigned oplat, unsigned issuelat)
+{
+    if (issuelat == 0 || oplat == 0)
+        panic("FuncUnit:  you don't really want a zero-cycle latency do you?");
+
+    capabilityList.set(cap);
+
+    opLatencies[cap] = oplat;
+    issueLatencies[cap] = issuelat;
+}
+
+bool
+FuncUnit::provides(OpClass capability)
+{
+    return capabilityList[capability];
+}
+
+bitset<Num_OpClasses>
+FuncUnit::capabilities()
+{
+    return capabilityList;
+}
+
+unsigned &
+FuncUnit::opLatency(OpClass cap)
+{
+    return opLatencies[cap];
+}
+
+unsigned
+FuncUnit::issueLatency(OpClass capability)
+{
+    return issueLatencies[capability];
+}
+
+////////////////////////////////////////////////////////////////////////////
+//
+//  The SimObjects we use to get the FU information into the simulator
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+//  We use 2 objects to specify this data in the INI file:
+//    (1) OpDesc - Describes the operation class & latencies
+//                   (multiple OpDesc objects can refer to the same
+//                   operation classes)
+//    (2) FUDesc - Describes the operations available in the unit &
+//                   the number of these units
+//
+//
+
+
+//
+//  The operation-class description object
+//
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
+
+    SimpleEnumParam<OpClass> opClass;
+    Param<unsigned>    opLat;
+    Param<unsigned>    issueLat;
+
+END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
+
+    INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
+    INIT_PARAM(opLat,        "cycles until result is available"),
+    INIT_PARAM(issueLat,     "cycles until another can be issued")
+
+END_INIT_SIM_OBJECT_PARAMS(OpDesc)
+
+
+CREATE_SIM_OBJECT(OpDesc)
+{
+    return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+}
+
+REGISTER_SIM_OBJECT("OpDesc", OpDesc)
+
+
+//
+//  The FuDesc object
+//
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
+
+    SimObjectVectorParam<OpDesc *> opList;
+    Param<unsigned>                count;
+
+END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
+
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
+
+    INIT_PARAM(opList, "list of operation classes for this FU type"),
+    INIT_PARAM(count,  "number of these FU's available")
+
+END_INIT_SIM_OBJECT_PARAMS(FUDesc)
+
+
+CREATE_SIM_OBJECT(FUDesc)
+{
+    return new FUDesc(getInstanceName(), opList, count);
+}
+
+REGISTER_SIM_OBJECT("FUDesc", FUDesc)
+
diff --git a/src/cpu/func_unit.hh b/src/cpu/func_unit.hh
new file mode 100644
index 000000000..780143096
--- /dev/null
+++ b/src/cpu/func_unit.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2002-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Raasch
+ */
+
+#ifndef __CPU_FUNC_UNIT_HH__
+#define __CPU_FUNC_UNIT_HH__
+
+#include <bitset>
+#include <string>
+#include <vector>
+
+#include "cpu/op_class.hh"
+#include "sim/sim_object.hh"
+
+////////////////////////////////////////////////////////////////////////////
+//
+//  Structures used ONLY during the initialization phase...
+//
+//
+//
+
+struct OpDesc : public SimObject
+{
+    OpClass opClass;
+    unsigned    opLat;
+    unsigned    issueLat;
+
+    OpDesc(std::string name, OpClass c, unsigned o, unsigned i)
+        : SimObject(name), opClass(c), opLat(o), issueLat(i) {};
+};
+
+struct FUDesc : public SimObject
+{
+    std::vector<OpDesc *> opDescList;
+    unsigned         number;
+
+    FUDesc(std::string name, std::vector<OpDesc *> l, unsigned n)
+        : SimObject(name), opDescList(l), number(n) {};
+};
+
+typedef std::vector<OpDesc *>::iterator OPDDiterator;
+typedef std::vector<FUDesc *>::iterator FUDDiterator;
+
+
+
+
+////////////////////////////////////////////////////////////////////////////
+//
+//  The actual FU object
+//
+//
+//
+class FuncUnit
+{
+  private:
+    unsigned opLatencies[Num_OpClasses];
+    unsigned issueLatencies[Num_OpClasses];
+    std::bitset<Num_OpClasses> capabilityList;
+
+  public:
+    FuncUnit();
+    FuncUnit(const FuncUnit &fu);
+
+    std::string name;
+
+    void addCapability(OpClass cap, unsigned oplat, unsigned issuelat);
+
+    bool provides(OpClass capability);
+    std::bitset<Num_OpClasses> capabilities();
+
+    unsigned &opLatency(OpClass capability);
+    unsigned issueLatency(OpClass capability);
+};
+
+#endif // __FU_POOL_HH__
diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc
index 545deea9b..42e329aca 100644
--- a/src/cpu/o3/fu_pool.cc
+++ b/src/cpu/o3/fu_pool.cc
@@ -31,7 +31,7 @@
 #include <sstream>
 
 #include "cpu/o3/fu_pool.hh"
-#include "encumbered/cpu/full/fu_pool.hh"
+#include "cpu/func_unit.hh"
 #include "sim/builder.hh"
 
 using namespace std;
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
new file mode 100644
index 000000000..f61590ae9
--- /dev/null
+++ b/src/python/m5/objects/FuncUnit.py
@@ -0,0 +1,17 @@
+from m5.config import *
+
+class OpType(Enum):
+    vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
+            'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
+            'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
+
+class OpDesc(SimObject):
+    type = 'OpDesc'
+    issueLat = Param.Int(1, "cycles until another can be issued")
+    opClass = Param.OpType("type of operation")
+    opLat = Param.Int(1, "cycles until result is available")
+
+class FUDesc(SimObject):
+    type = 'FUDesc'
+    count = Param.Int("number of these FU's available")
+    opList = VectorParam.OpDesc("operation classes for this FU type")