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authorStephen Hines <hines@cs.fsu.edu>2008-02-05 23:44:13 -0500
committerStephen Hines <hines@cs.fsu.edu>2008-02-05 23:44:13 -0500
commit0ccf9a2c3751f160d7d51153ef468a60b4daf8d0 (patch)
tree3f5d77b729818492d27996adbc69b472f6fd4da7
parentca313e23033cd3f2ef827edf9a442ed1ae3d087f (diff)
downloadgem5-0ccf9a2c3751f160d7d51153ef468a60b4daf8d0.tar.xz
Add base ARM code to M5
--HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
-rw-r--r--.hgignore1
-rw-r--r--src/arch/isa_specific.hh3
-rw-r--r--src/base/loader/elf_object.cc3
-rw-r--r--src/base/loader/object_file.hh3
-rw-r--r--src/cpu/BaseCPU.py9
-rw-r--r--src/cpu/o3/dyn_inst.hh4
-rw-r--r--src/cpu/simple/timing.cc14
-rw-r--r--src/cpu/static_inst.hh1
-rw-r--r--src/sim/process.cc13
9 files changed, 45 insertions, 6 deletions
diff --git a/.hgignore b/.hgignore
index f536836de..f6a91e6e3 100644
--- a/.hgignore
+++ b/.hgignore
@@ -6,3 +6,4 @@ cscope.files
cscope.out
*.pyc
*~
+.*.swp
diff --git a/src/arch/isa_specific.hh b/src/arch/isa_specific.hh
index c241e5c62..c10ce7350 100644
--- a/src/arch/isa_specific.hh
+++ b/src/arch/isa_specific.hh
@@ -49,6 +49,7 @@
#define SPARC_ISA 42
#define MIPS_ISA 34000
#define X86_ISA 8086
+#define ARM_ISA 6
//These tell the preprocessor where to find the files of a particular
//ISA, and set the "TheISA" macro for use elsewhere.
@@ -60,6 +61,8 @@
#define TheISA MipsISA
#elif THE_ISA == X86_ISA
#define TheISA X86ISA
+#elif THE_ISA == ARM_ISA
+ #define TheISA ArmISA
#else
#error "THE_ISA not set"
#endif
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index 23df1c5ba..8e41ffd16 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -88,6 +88,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
arch = ObjectFile::X86;
} else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = ObjectFile::Alpha;
+ } else if (ehdr.e_machine == EM_ARM) {
+ arch = ObjectFile::Arm;
} else {
warn("Unknown architecture: %d\n", ehdr.e_machine);
arch = ObjectFile::UnknownArch;
@@ -98,6 +100,7 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
{
case ELFOSABI_LINUX:
+ case ELFOSABI_ARM:
opSys = ObjectFile::Linux;
break;
case ELFOSABI_SOLARIS:
diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index 4f0c17cc8..7f2bef0bf 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -50,7 +50,8 @@ class ObjectFile
SPARC64,
SPARC32,
Mips,
- X86
+ X86,
+ Arm
};
enum OpSys {
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ee5ed0774..c2a865113 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,8 @@ elif build_env['TARGET_ISA'] == 'x86':
from X86TLB import X86DTB, X86ITB
elif build_env['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
+elif build_env['TARGET_ISA'] == 'arm':
+ from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
class BaseCPU(SimObject):
type = 'BaseCPU'
@@ -76,6 +78,11 @@ class BaseCPU(SimObject):
dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
itb = Param.MipsITB(MipsITB(), "Instruction TLB")
tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
+ elif build_env['TARGET_ISA'] == 'arm':
+ UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+ dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
+ itb = Param.ArmITB(ArmITB(), "Instruction TLB")
+ tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
else:
print "Don't know what TLB to use for ISA %s" % \
build_env['TARGET_ISA']
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index c37f8007e..a1f9e0591 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -49,6 +49,10 @@
template <class Impl> class X86DynInst;
struct X86SimpleImpl;
typedef X86DynInst<X86SimpleImpl> O3DynInst;
+#elif THE_ISA == ARM_ISA
+ template <class Impl> class ArmDynInst;
+ struct ArmSimpleImpl;
+ typedef ArmDynInst<ArmSimpleImpl> O3DynInst;
#else
#error "O3DynInst not defined for this ISA"
#endif
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fc35f2666..e1fc6882f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
assert(fault == NoFault);
} else {
if (fault == NoFault) {
+ // Note that ARM can have NULL packets if the instruction gets
+ // squashed due to predication
// early fail on store conditional: complete now
- assert(dcache_pkt != NULL);
+ assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
fault = curStaticInst->completeAcc(dcache_pkt, this,
traceData);
- delete dcache_pkt->req;
- delete dcache_pkt;
- dcache_pkt = NULL;
+ if (dcache_pkt != NULL)
+ {
+ delete dcache_pkt->req;
+ delete dcache_pkt;
+ dcache_pkt = NULL;
+ }
// keep an instruction count
if (fault == NoFault)
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index d2232bab7..ceda78d90 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -259,6 +259,7 @@ class StaticInstBase : public RefCounted
bool isMicroBranch() const { return flags[IsMicroBranch]; }
//@}
+ void setLastMicroop() { flags[IsLastMicroop] = true; }
/// Operation class. Used to select appropriate function unit in issue.
OpClass opClass() const { return _opClass; }
};
diff --git a/src/sim/process.cc b/src/sim/process.cc
index d83b0247e..16037b2f4 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -61,6 +61,8 @@
#include "arch/sparc/solaris/process.hh"
#elif THE_ISA == MIPS_ISA
#include "arch/mips/linux/process.hh"
+#elif THE_ISA == ARM_ISA
+#include "arch/arm/linux/process.hh"
#elif THE_ISA == X86_ISA
#include "arch/x86/linux/process.hh"
#else
@@ -700,6 +702,17 @@ LiveProcess::create(LiveProcessParams * params)
default:
fatal("Unknown/unsupported operating system.");
}
+#elif THE_ISA == ARM_ISA
+ if (objFile->getArch() != ObjectFile::Arm)
+ fatal("Object file architecture does not match compiled ISA (ARM).");
+ switch (objFile->getOpSys()) {
+ case ObjectFile::Linux:
+ process = new ArmLinuxProcess(params, objFile);
+ break;
+
+ default:
+ fatal("Unknown/unsupported operating system.");
+ }
#else
#error "THE_ISA not set"
#endif