ruby: convert to M5 MemorySize

Converted both ruby caches and directory memory to use the M5 MemorySize python
type.

8 files changed, 26 insertions, 17 deletions

diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index e30f40bd5..33f2fd0e5 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -72,9 +72,15 @@ parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
 parser.add_option("--output", default="", help="Redirect stdout to a file.")
 parser.add_option("--errout", default="", help="Redirect stderr to a file.")
 
+# cache parameters
+parser.add_option("--l1d_size", type="string", default="32kB")
+parser.add_option("--l1i_size", type="string", default="32kB")
+parser.add_option("--l2_size", type="string", default="1MB")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=16)
+ 
 # ruby host memory experimentation
-parser.add_option("--cache_size", type="int")
-parser.add_option("--cache_assoc", type="int")
 parser.add_option("--map_levels", type="int")
 
 execfile(os.path.join(config_root, "common", "Options.py"))
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 5273f597b..dba31b8b7 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -37,17 +37,13 @@ from m5.util import addToPath
 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
 #
 class L1Cache(RubyCache):
-    assoc = 2
     latency = 3
-    size = 32768
 
 #
 # Note: the L2 Cache latency is not currently used
 #
 class L2Cache(RubyCache):
-    assoc = 16
     latency = 15
-    size = 1048576
 
 def create_system(options, phys_mem, piobus, dma_devices):
     
@@ -74,9 +70,12 @@ def create_system(options, phys_mem, piobus, dma_devices):
         #
         # First create the Ruby objects associated with this cpu
         #
-        l1i_cache = L1Cache()
-        l1d_cache = L1Cache()
-        l2_cache = L2Cache()
+        l1i_cache = L1Cache(size = options.l1i_size,
+                            assoc = options.l1i_assoc)
+        l1d_cache = L1Cache(size = options.l1d_size,
+                            assoc = options.l1d_assoc)
+        l2_cache = L2Cache(size = options.l2_size,
+                           assoc = options.l2_assoc)
 
         cpu_seq = RubySequencer(icache = l1i_cache,
                                 dcache = l1d_cache,
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index abc9a8df5..7003e6266 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -54,8 +54,12 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
     #
     network = SimpleNetwork(topology = makeCrossbar(all_cntrls))
 
-    mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
-                       for dir_cntrl in dir_cntrls])
+    #
+    # determine the total memory size of the ruby system
+    #
+    total_mem_size = MemorySize('0B')
+    for dir_cntrl in dir_cntrls:
+        total_mem_size.value += dir_cntrl.directory.size.value
 
     ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers))
     
@@ -66,7 +70,7 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
                       debug = RubyDebug(filter_string = 'none',
                                         verbosity_string = 'none',
                                         protocol_trace = False),
-                      mem_size_mb = mem_size_mb)
+                      mem_size = total_mem_size)
 
     ruby.cpu_ruby_ports = cpu_sequencers
 
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index 209d6f6e2..8098e6192 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -5,7 +5,7 @@ from Controller import RubyController
 class RubyCache(SimObject):
     type = 'RubyCache'
     cxx_class = 'CacheMemory'
-    size = Param.Int("");
+    size = Param.MemorySize("capacity in bytes");
     latency = Param.Int("");
     assoc = Param.Int("");
     replacement_policy = Param.String("PSEUDO_LRU", "");
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index e4801594c..adf63d06f 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -49,7 +49,7 @@ DirectoryMemory::DirectoryMemory(const Params *p)
     : SimObject(p)
 {
     m_version = p->version;
-    m_size_bytes = p->size_mb * static_cast<uint64>(1<<20);
+    m_size_bytes = p->size;
     m_size_bits = log_int(m_size_bytes);
 }
 
diff --git a/src/mem/ruby/system/DirectoryMemory.py b/src/mem/ruby/system/DirectoryMemory.py
index e3becc4fc..e430cede3 100644
--- a/src/mem/ruby/system/DirectoryMemory.py
+++ b/src/mem/ruby/system/DirectoryMemory.py
@@ -6,4 +6,4 @@ class RubyDirectoryMemory(SimObject):
     type = 'RubyDirectoryMemory'
     cxx_class = 'DirectoryMemory'
     version = Param.Int(0, "")
-    size_mb = Param.Int(1024, "")
+    size = Param.MemorySize("1GB", "capacity in bytes")
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index d53271e45..3b079f9c0 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -9,7 +9,7 @@ class RubySystem(SimObject):
     clock = Param.Clock('1GHz', "")
     block_size_bytes = Param.Int(64,
         "default cache block size; must be a power of two");
-    mem_size_mb = Param.Int("");
+    mem_size = Param.MemorySize("total memory size of the system");
     network = Param.RubyNetwork("")
     debug = Param.RubyDebug("the default debug object")
     profiler = Param.RubyProfiler("");
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index 3159a2888..47b53aedd 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -98,7 +98,7 @@ RubySystem::RubySystem(const Params *p)
     assert(is_power_of_2(m_block_size_bytes));
     m_block_size_bits = log_int(m_block_size_bytes);
 
-    m_memory_size_bytes = (uint64_t)p->mem_size_mb * 1024 * 1024;
+    m_memory_size_bytes = p->mem_size;
     m_memory_size_bits = log_int(m_memory_size_bytes);
 
     m_network_ptr = p->network;