diff options
| author | Steve Reinhardt <stever@gmail.com> | 2014-05-10 22:13:51 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2014-05-10 22:13:51 -0400 |
| commit | 2136feaa55af60d407fe51df5309494dd9c374fb (patch) | |
| tree | 1c0483d404f5680d328695b570ab716cd6fac4fd | |
| parent | 57e5401d954d46fea45ca3eaafa8ae655659da39 (diff) | |
| download | gem5-2136feaa55af60d407fe51df5309494dd9c374fb.tar.xz | |
tests: update eio ref outputs for new stats
Also committed reference config.json files for
the eio tests.
18 files changed, 2552 insertions, 34 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index fb0cfcac5..c59537dfb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -70,6 +71,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu.tracer diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json new file mode 100644 index 000000000..f16d8f1f9 --- /dev/null +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json @@ -0,0 +1,186 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout index 7f750f485..63ff01637 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:45 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:56:07 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index b531b1361..50004b5f6 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1916007 # Simulator instruction rate (inst/s) -host_op_rate 1915868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 957925931 # Simulator tick rate (ticks/s) -host_mem_usage 266944 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 2753718 # Simulator instruction rate (inst/s) +host_op_rate 2753463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1376691607 # Simulator tick rate (ticks/s) +host_mem_usage 219892 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 500032 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 59023 # Number of branches fetched +system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 500019 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 35221c77a..1136d541a 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -64,6 +65,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu.tracer diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json new file mode 100644 index 000000000..32695de47 --- /dev/null +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json @@ -0,0 +1,322 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 262144 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 0, + "eventq_index": 0, + "toL2Bus": { + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "name": "toL2Bus", + "header_cycles": 1, + "width": 32, + "eventq_index": 0, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.cpu.toL2Bus", + "type": "CoherentBus", + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 2, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 131072 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "l2cache": { + "assoc": 8, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "name": "l2cache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "hit_latency": 20, + "mshrs": 20, + "response_latency": 20, + "is_top_level": false, + "tgts_per_mshr": 12, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu.l2cache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 2097152 + }, + "path": "system.cpu", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout index b4917adea..584e42e77 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:45 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:55:42 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 874d16910..b7fd6736b 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu sim_ticks 727072000 # Number of ticks simulated final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056088 # Simulator instruction rate (inst/s) -host_op_rate 1056045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1535580911 # Simulator tick rate (ticks/s) -host_mem_usage 276676 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host +host_inst_rate 1291108 # Simulator instruction rate (inst/s) +host_op_rate 1291046 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1877262486 # Simulator tick rate (ticks/s) +host_mem_usage 229624 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 1454144 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 59023 # Number of branches fetched +system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 6d8e3c814..1a2af15a4 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -70,6 +71,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -185,6 +187,7 @@ system=system [system.cpu1] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 @@ -212,6 +215,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu1.tracer @@ -327,6 +331,7 @@ system=system [system.cpu2] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=2 @@ -354,6 +359,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu2.tracer @@ -469,6 +475,7 @@ system=system [system.cpu3] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=3 @@ -496,6 +503,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu3.tracer diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json new file mode 100644 index 000000000..b534dacc6 --- /dev/null +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json @@ -0,0 +1,829 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.l2c.mem_side" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "l2c": { + "assoc": 8, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.toL2Bus.master[0]", + "role": "SLAVE" + }, + "name": "l2c", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.l2c.tags", + "block_size": 64, + "type": "LRU", + "size": 4194304 + }, + "hit_latency": 20, + "mshrs": 20, + "response_latency": 20, + "is_top_level": false, + "tgts_per_mshr": 12, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.l2c", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 4194304 + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "toL2Bus": { + "slave": { + "peer": [ + "system.cpu0.icache.mem_side", + "system.cpu0.dcache.mem_side", + "system.cpu1.icache.mem_side", + "system.cpu1.dcache.mem_side", + "system.cpu2.icache.mem_side", + "system.cpu2.dcache.mem_side", + "system.cpu3.icache.mem_side", + "system.cpu3.dcache.mem_side" + ], + "role": "SLAVE" + }, + "name": "toL2Bus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.l2c.cpu_side" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.toL2Bus", + "type": "CoherentBus", + "use_default_range": false + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu0.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.cpu0.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[0]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu0.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu0.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu0.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu0.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu0", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu0.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu0.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu0", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu0.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu0.dcache.cpu_side", + "role": "MASTER" + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu0.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu0.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu0.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu0.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu1.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 1, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.cpu1.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[2]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu1.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu1.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu1.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu1.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu1", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu1.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu1.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu1", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu1.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu1.dcache.cpu_side", + "role": "MASTER" + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[3]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu1.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu1.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu1.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu1.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu2.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 2, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.cpu2.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[4]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu2.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu2.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu2.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu2.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu2", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu2.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu2.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu2", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu2.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu2.dcache.cpu_side", + "role": "MASTER" + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[5]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu2.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu2.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu2.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu2.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "simpoint_interval": 100000000, + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu3.itb", + "type": "AlphaTLB", + "size": 48 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "simpoint_profile": false, + "simulate_data_stalls": false, + "function_trace_start": 0, + "cpu_id": 3, + "width": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0.0, + "icache_port": { + "peer": "system.cpu3.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[6]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu3.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu3.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu3.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu3.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu3", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu3.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu3.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu3", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu3.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "simulate_inst_stalls": false, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu3.dcache.cpu_side", + "role": "MASTER" + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[7]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu3.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu3.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu3.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu3.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 5109cffe4..9205d04ab 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -3,7 +3,8 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything gzip: stdout: Broken pipe -stdout: Broken pipe + +gzip: stdout: Broken pipe stdout: Broken pipe gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 2b7142201..7301ae168 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:45 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:55:31 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 3c34bb9de..7757fcfab 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2195056 # Simulator instruction rate (inst/s) -host_op_rate 2195007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274386672 # Simulator tick rate (ticks/s) -host_mem_usage 288592 # Number of bytes of host memory used -host_seconds 0.91 # Real time elapsed on the host +host_inst_rate 2755592 # Simulator instruction rate (inst/s) +host_op_rate 2755527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344450673 # Simulator tick rate (ticks/s) +host_mem_usage 240516 # Number of bytes of host memory used +host_seconds 0.73 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -290,6 +290,41 @@ system.cpu0.num_busy_cycles 500032 # Nu system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 59023 # Number of branches fetched +system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. @@ -453,6 +488,41 @@ system.cpu1.num_busy_cycles 500032 # Nu system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.Branches 59023 # Number of branches fetched +system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu1.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 500019 # Class of executed instruction system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. @@ -616,6 +686,41 @@ system.cpu2.num_busy_cycles 500032 # Nu system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.Branches 59023 # Number of branches fetched +system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu2.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 500019 # Class of executed instruction system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. @@ -779,6 +884,41 @@ system.cpu3.num_busy_cycles 500032 # Nu system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.Branches 59023 # Number of branches fetched +system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu3.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 500019 # Class of executed instruction system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 8c624e3de..b4705255d 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -43,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -64,6 +65,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -178,6 +180,7 @@ system=system [system.cpu1] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 @@ -199,6 +202,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu1.tracer @@ -313,6 +317,7 @@ system=system [system.cpu2] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=2 @@ -334,6 +339,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu2.tracer @@ -448,6 +454,7 @@ system=system [system.cpu3] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=3 @@ -469,6 +476,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu3.tracer diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json new file mode 100644 index 000000000..c960fde35 --- /dev/null +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json @@ -0,0 +1,805 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "slave": { + "peer": [ + "system.system_port", + "system.l2c.mem_side" + ], + "role": "SLAVE" + }, + "name": "membus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.membus", + "type": "CoherentBus", + "use_default_range": false + }, + "l2c": { + "assoc": 8, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.toL2Bus.master[0]", + "role": "SLAVE" + }, + "name": "l2c", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.l2c.tags", + "block_size": 64, + "type": "LRU", + "size": 4194304 + }, + "hit_latency": 20, + "mshrs": 20, + "response_latency": 20, + "is_top_level": false, + "tgts_per_mshr": 12, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.l2c", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 4194304 + }, + "voltage_domain": { + "eventq_index": 0, + "path": "system.voltage_domain", + "type": "VoltageDomain", + "name": "voltage_domain", + "cxx_class": "VoltageDomain" + }, + "physmem": { + "latency": 3.0000000000000004e-08, + "name": "physmem", + "eventq_index": 0, + "latency_var": 0.0, + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "cxx_class": "System", + "load_offset": 0, + "work_end_ckpt_count": 0, + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": 1e-09, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain" + }, + "eventq_index": 0, + "toL2Bus": { + "slave": { + "peer": [ + "system.cpu0.icache.mem_side", + "system.cpu0.dcache.mem_side", + "system.cpu1.icache.mem_side", + "system.cpu1.dcache.mem_side", + "system.cpu2.icache.mem_side", + "system.cpu2.dcache.mem_side", + "system.cpu3.icache.mem_side", + "system.cpu3.dcache.mem_side" + ], + "role": "SLAVE" + }, + "name": "toL2Bus", + "header_cycles": 1, + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.l2c.cpu_side" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentBus", + "path": "system.toL2Bus", + "type": "CoherentBus", + "use_default_range": false + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": 5e-10, + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain" + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "load_addr_mask": 1099511627775, + "work_item_id": -1, + "num_work_ids": 16, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu0.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[1]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu0.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu0.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu0.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 0, + "eventq_index": 0, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu0.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[0]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu0.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu0.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu0.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu0.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu0", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu0.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu0.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu0", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu0.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu0.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu0.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu1.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[3]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu1.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu1.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu1.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 1, + "eventq_index": 0, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu1.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[2]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu1.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu1.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu1.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu1.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu1", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu1.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu1.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu1", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu1.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu1.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu1.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu2.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[5]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu2.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu2.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu2.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 2, + "eventq_index": 0, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu2.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[4]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu2.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu2.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu2.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu2.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu2", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu2.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu2.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu2", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu2.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu2.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu2.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu3.itb", + "type": "AlphaTLB", + "size": 48 + }, + "dcache": { + "assoc": 4, + "mem_side": { + "peer": "system.toL2Bus.slave[7]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu3.dcache_port", + "role": "SLAVE" + }, + "name": "dcache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu3.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu3.dcache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "function_trace_start": 0, + "cpu_id": 3, + "eventq_index": 0, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0.0, + "icache_port": { + "peer": "system.cpu3.icache.cpu_side", + "role": "MASTER" + }, + "icache": { + "assoc": 1, + "mem_side": { + "peer": "system.toL2Bus.slave[6]", + "role": "MASTER" + }, + "cpu_side": { + "peer": "system.cpu3.icache_port", + "role": "SLAVE" + }, + "name": "icache", + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "sequential_access": false, + "assoc": 1, + "cxx_class": "LRU", + "path": "system.cpu3.icache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "hit_latency": 2, + "mshrs": 4, + "response_latency": 2, + "is_top_level": true, + "tgts_per_mshr": 20, + "sequential_access": false, + "max_miss_count": 0, + "eventq_index": 0, + "prefetch_on_access": false, + "cxx_class": "BaseCache", + "path": "system.cpu3.icache", + "write_buffers": 8, + "two_queue": false, + "type": "BaseCache", + "forward_snoops": true, + "size": 32768 + }, + "interrupts": { + "eventq_index": 0, + "path": "system.cpu3.interrupts", + "type": "AlphaInterrupts", + "name": "interrupts", + "cxx_class": "AlphaISA::Interrupts" + }, + "socket_id": 0, + "max_insts_all_threads": 0, + "path": "system.cpu3", + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu3.isa", + "type": "AlphaISA", + "name": "isa", + "cxx_class": "AlphaISA::ISA" + } + ], + "switched_out": false, + "workload": [ + { + "name": "workload", + "eventq_index": 0, + "cxx_class": "EioProcess", + "path": "system.cpu3.workload", + "max_stack_size": 67108864, + "type": "EioProcess" + } + ], + "name": "cpu3", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "AlphaISA::TLB", + "path": "system.cpu3.dtb", + "type": "AlphaTLB", + "size": 64 + }, + "max_insts_any_thread": 500000, + "progress_interval": 0.0, + "dcache_port": { + "peer": "system.cpu3.dcache.cpu_side", + "role": "MASTER" + }, + "function_trace": false, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu3.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 0.1, + "eventq_index": 0, + "time_sync_spin_threshold": 9.999999999999999e-05, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 989ba8a4a..7bec60132 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -3,4 +3,9 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything gzip: stdout: Broken pipe -stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index da885936c..a49149440 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 27 2014 00:31:18 -gem5 started Jan 27 2014 00:31:56 +gem5 compiled May 10 2014 16:25:16 +gem5 started May 10 2014 16:55:53 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 5e8039570..4ed73aa2b 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000729 # Nu sim_ticks 729024000 # Number of ticks simulated final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1003743 # Simulator instruction rate (inst/s) -host_op_rate 1003733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 365876623 # Simulator tick rate (ticks/s) -host_mem_usage 288596 # Number of bytes of host memory used -host_seconds 1.99 # Real time elapsed on the host +host_inst_rate 1251613 # Simulator instruction rate (inst/s) +host_op_rate 1251599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 456227594 # Simulator tick rate (ticks/s) +host_mem_usage 240516 # Number of bytes of host memory used +host_seconds 1.60 # Real time elapsed on the host sim_insts 1999959 # Number of instructions simulated sim_ops 1999959 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -535,6 +535,41 @@ system.cpu0.num_busy_cycles 1458048 # Nu system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 59023 # Number of branches fetched +system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction +system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. @@ -781,6 +816,41 @@ system.cpu1.num_busy_cycles 1458048 # Nu system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.Branches 59022 # Number of branches fetched +system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu1.op_class::IntAlu 300381 60.07% 63.84% # Class of executed instruction +system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction +system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 500011 # Class of executed instruction system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks. @@ -1027,6 +1097,41 @@ system.cpu2.num_busy_cycles 1458048 # Nu system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.Branches 59022 # Number of branches fetched +system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu2.op_class::IntAlu 300376 60.07% 63.84% # Class of executed instruction +system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu2.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction +system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 500004 # Class of executed instruction system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks. @@ -1273,6 +1378,41 @@ system.cpu3.num_busy_cycles 1458048 # Nu system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.Branches 59020 # Number of branches fetched +system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction +system.cpu3.op_class::IntAlu 300371 60.07% 63.84% # Class of executed instruction +system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu3.op_class::MemRead 124439 24.89% 88.73% # Class of executed instruction +system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 499997 # Class of executed instruction system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks. |