Add IFT debug flags

6 files changed, 32 insertions, 11 deletions

diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index bd028e640..54ce66d50 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -71,6 +71,7 @@ if 'O3CPU' in env['CPU_MODELS']:
     DebugFlag('Scoreboard')
     DebugFlag('StoreSet')
     DebugFlag('Writeback')
+    DebugFlag('IFT')
 
     CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
         'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d3c67c4cb..22b4bb12a 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -53,6 +53,7 @@
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/reg_class.hh"
+#include "debug/IFT.hh"
 
 class Packet;
 
@@ -416,8 +417,12 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
     }
 
-    void taintDestRegs(bool istaint)
+    void taintDestRegs(bool istaint, const char *reason)
     {
+        DPRINTF(IFT, "%s dst registers of instruction PC: %s [sn:%i] because %s\n",
+                istaint?"Tainting":"Untainting",
+                this->pcState(), this->seqNum,
+                reason);
         isTainted = istaint;
         for (size_t i = 0; i < this->numDestRegs(); i++) {
             auto dstreg = _destRegIdx[i];
@@ -431,11 +436,16 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     bool srcTainted(void)
     {
+        DPRINTF(IFT, "checking instruction PC: %s [sn:%i] for tainted registers.\n",
+                this->pcState(), this->seqNum);
         bool result = false;
         for (size_t i = 0; i < this->numSrcRegs(); i++) {
             auto src = _srcRegIdx[i];
             result |= cpu->regTainted(src);
         }
+        DPRINTF(IFT, "source registers of instruction PC: %s [sn:%i] is %s\n",
+                this->pcState(), this->seqNum,
+                result?"tainted":"not tainted");
         return result;
     }
 
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 44afc9076..5b67e4c3c 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1329,11 +1329,9 @@ DefaultIEW<Impl>::executeInsts()
             }
 
             if (inst->srcTainted()) {
-                DPRINTF(IEW, "Taint instruction PC: %s [sn:%i]\n", inst->pcState(), inst->seqNum);
-                inst->taintDestRegs(true);
+                inst->taintDestRegs(true, "source is tainted");
             } else {
-                DPRINTF(IEW, "Untaint instruction PC: %s [sn:%i]\n", inst->pcState(), inst->seqNum);
-                inst->taintDestRegs(false);
+                inst->taintDestRegs(false, "source is not tainted");
             }
 
             inst->setExecuted();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index a8ec0333f..79d913175 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1055,7 +1055,7 @@ LSQUnit<Impl>::updateVisibleState()
                   inst->readyToExpose(false);
                 } else {
                   /* set taint for dst registers */
-                  inst->taintDestRegs(true);
+                  inst->taintDestRegs(true, "unsafe load");
                   /* if the load depends on tainted registers, set
                      readyToExpose to false, otherwise set it to true
                   */
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index b835a7dd8..68be3612f 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -55,6 +55,7 @@
 #include "cpu/o3/comm.hh"
 #include "debug/IEW.hh"
 #include "enums/VecRegRenameMode.hh"
+#include "debug/IFT.hh"
 
 class UnifiedFreeList;
 
@@ -202,23 +203,34 @@ class PhysRegFile
         warn_once("taint for vector registers not supported yet\n");
         break;
       }
+      DPRINTF(IFT, "register %s %d is set to %d\n",
+              phys_reg->className(), idx, taintvalue);
+
     }
 
     bool regTainted(PhysRegIdPtr phys_reg) {
       RegIndex idx = phys_reg->index();
+      bool result;
       switch (phys_reg->classValue()) {
       case IntRegClass:
-        return intTaintMap[idx];
+        result = intTaintMap[idx];
+        break;
       case FloatRegClass:
-        return floatTaintMap[idx];
+        result = floatTaintMap[idx];
+        break;
       case CCRegClass:
-        return ccTaintMap[idx];
+        result = ccTaintMap[idx];
+        break;
       case MiscRegClass:
-        return miscTaintMap[idx];
+        result = miscTaintMap[idx];
+        break;
       default:
         warn_once("taint for vector registers not supported yet\n");
         return false;
       }
+      DPRINTF(IFT, "register %s %d is %s\n",
+              phys_reg->className(), idx, result?"tained":"not tainted");
+      return result;
     }
 
     /** Reads an integer register. */
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 5705b32e8..093dd2840 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -437,7 +437,7 @@ ROB<Impl>::updateVisibleState()
 
             if (inst->isTainted) {
               if (prevBrsResolved) {
-                inst->taintDestRegs(false);
+                inst->taintDestRegs(false, "previous branches are resolved");
               }
             }