diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-01-27 12:40:01 +0000 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-01-27 12:40:01 +0000 |
commit | 2974dc7a3771e34542ed5bd1baf88e4ced8cf139 (patch) | |
tree | c60e4620b2ac61d0790c07fabdd802b1107a8976 | |
parent | e3875215270220e5142a93848f74ccde9d61b244 (diff) | |
download | gem5-2974dc7a3771e34542ed5bd1baf88e4ced8cf139.tar.xz |
python: Move native wrappers to the _m5 namespace
Swig wrappers for native objects currently share the _m5.internal name
space with Python code. This is undesirable if we ever want to switch
from Swig to some other framework for native binding (e.g., PyBind11
or Boost::Python). This changeset moves all of such wrappers to the
_m5 namespace, which is now reserved for native code.
Change-Id: I2d2bc12dbc05b57b7c5a75f072e08124413d77f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
-rwxr-xr-x | src/SConscript | 20 | ||||
-rw-r--r-- | src/python/SConscript | 19 | ||||
-rw-r--r-- | src/python/_m5/__init__.py | 39 | ||||
-rw-r--r-- | src/python/m5/SimObject.py | 6 | ||||
-rw-r--r-- | src/python/m5/__init__.py | 11 | ||||
-rw-r--r-- | src/python/m5/core.py | 5 | ||||
-rw-r--r-- | src/python/m5/debug.py | 11 | ||||
-rw-r--r-- | src/python/m5/event.py | 8 | ||||
-rw-r--r-- | src/python/m5/internal/params.py | 4 | ||||
-rw-r--r-- | src/python/m5/params.py | 12 | ||||
-rw-r--r-- | src/python/m5/simulate.py | 33 | ||||
-rw-r--r-- | src/python/m5/stats/__init__.py | 20 | ||||
-rw-r--r-- | src/python/m5/ticks.py | 4 | ||||
-rw-r--r-- | src/python/m5/trace.py | 12 | ||||
-rw-r--r-- | src/python/swig/core.i | 2 | ||||
-rw-r--r-- | src/python/swig/debug.i | 2 | ||||
-rw-r--r-- | src/python/swig/drain.i | 2 | ||||
-rw-r--r-- | src/python/swig/event.i | 2 | ||||
-rw-r--r-- | src/python/swig/pyobject.i | 2 | ||||
-rw-r--r-- | src/python/swig/range.i | 2 | ||||
-rw-r--r-- | src/python/swig/serialize.i | 2 | ||||
-rw-r--r-- | src/python/swig/stats.i | 2 | ||||
-rw-r--r-- | src/python/swig/trace.i | 2 | ||||
-rw-r--r-- | src/unittest/SConscript | 2 | ||||
-rw-r--r-- | src/unittest/stattest.i | 2 | ||||
-rw-r--r-- | src/unittest/stattestmain.py | 2 | ||||
-rw-r--r-- | tests/configs/switcheroo.py | 3 |
27 files changed, 129 insertions, 102 deletions
diff --git a/src/SConscript b/src/SConscript index 115ce24eb..521d73bac 100755 --- a/src/SConscript +++ b/src/SConscript @@ -483,7 +483,7 @@ class DictImporter(object): if fullname == 'm5.objects': return self - if fullname.startswith('m5.internal'): + if fullname.startswith('_m5'): return None source = self.modules.get(fullname, None) @@ -588,14 +588,14 @@ def makeDefinesPyFile(target, source, env): code = code_formatter() code(""" -import m5.internal +import _m5.core import m5.util buildEnv = m5.util.SmartDict($build_env) -compileDate = m5.internal.core.compileDate +compileDate = _m5.core.compileDate _globals = globals() -for key,val in m5.internal.core.__dict__.iteritems(): +for key,val in _m5.core.__dict__.iteritems(): if key.startswith('flag_'): flag = key[5:] _globals[flag] = val @@ -773,13 +773,13 @@ if GetOption('with_cxx_config'): # Generate any needed param SWIG wrapper files params_i_files = [] for name,param in sorted(params_to_swig.iteritems()): - i_file = File('python/m5/internal/%s.i' % (param.swig_module_name())) + i_file = File('python/_m5/%s.i' % (param.swig_module_name())) params_i_files.append(i_file) env.Command(i_file, Value(name), MakeAction(createParamSwigWrapper, Transform("SW PARAM"))) env.Depends(i_file, depends) env.Depends(SWIG, i_file) - SwigSource('m5.internal', i_file) + SwigSource('_m5', i_file) # Generate all enum header files for name,enum in sorted(all_enums.iteritems()): @@ -799,22 +799,22 @@ for name,enum in sorted(all_enums.iteritems()): env.Depends(hh_file, depends + extra_deps) env.Depends(SWIG, hh_file) - i_file = File('python/m5/internal/enum_%s.i' % name) + i_file = File('python/_m5/enum_%s.i' % name) env.Command(i_file, Value(name), MakeAction(createEnumSwigWrapper, Transform("ENUMSWIG"))) env.Depends(i_file, depends + extra_deps) env.Depends(SWIG, i_file) - SwigSource('m5.internal', i_file) + SwigSource('_m5', i_file) # Generate SimObject SWIG wrapper files for name,simobj in sorted(sim_objects.iteritems()): py_source = PySource.modules[simobj.__module__] extra_deps = [ py_source.tnode ] - i_file = File('python/m5/internal/param_%s.i' % name) + i_file = File('python/_m5/param_%s.i' % name) env.Command(i_file, Value(name), MakeAction(createSimObjectSwigWrapper, Transform("SO SWIG"))) env.Depends(i_file, depends + extra_deps) - SwigSource('m5.internal', i_file) + SwigSource('_m5', i_file) # Generate the main swig init file def makeEmbeddedSwigInit(package): diff --git a/src/python/SConscript b/src/python/SConscript index 503e9138d..c1868f4b8 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -63,14 +63,15 @@ PySource('m5.util', 'm5/util/smartdict.py') PySource('m5.util', 'm5/util/sorteddict.py') PySource('m5.util', 'm5/util/terminal.py') -SwigSource('m5.internal', 'swig/core.i') -SwigSource('m5.internal', 'swig/debug.i') -SwigSource('m5.internal', 'swig/drain.i') -SwigSource('m5.internal', 'swig/event.i') -SwigSource('m5.internal', 'swig/pyobject.i') -SwigSource('m5.internal', 'swig/range.i') -SwigSource('m5.internal', 'swig/serialize.i') -SwigSource('m5.internal', 'swig/stats.i') -SwigSource('m5.internal', 'swig/trace.i') +PySource('_m5', '_m5/__init__.py') +SwigSource('_m5', 'swig/core.i') +SwigSource('_m5', 'swig/debug.i') +SwigSource('_m5', 'swig/drain.i') +SwigSource('_m5', 'swig/event.i') +SwigSource('_m5', 'swig/pyobject.i') +SwigSource('_m5', 'swig/range.i') +SwigSource('_m5', 'swig/serialize.i') +SwigSource('_m5', 'swig/stats.i') +SwigSource('_m5', 'swig/trace.i') PySource('m5.internal', 'm5/internal/__init__.py') PySource('m5.internal', 'm5/internal/params.py') diff --git a/src/python/_m5/__init__.py b/src/python/_m5/__init__.py new file mode 100644 index 000000000..d3ac65e12 --- /dev/null +++ b/src/python/_m5/__init__.py @@ -0,0 +1,39 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +# This is a place holder to create a package for generated code. Don't +# add any Python code in this name space. diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 11f356204..07df44240 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -656,7 +656,7 @@ class MetaSimObject(type): # See ParamValue.swig_predecls for description. def swig_predecls(cls, code): - code('%import "python/m5/internal/param_$cls.i"') + code('%import "python/_m5/param_$cls.i"') # Hook for exporting additional C++ methods to Python via SWIG. # Default is none, override using @classmethod in class definition. @@ -686,7 +686,7 @@ class MetaSimObject(type): params = map(lambda (k, v): v, sorted(cls._params.local.items())) ports = cls._ports.local - code('%module(package="m5.internal") param_$cls') + code('%module(package="_m5") param_$cls') code() code('%{') code('#include "sim/sim_object.hh"') @@ -716,7 +716,7 @@ using std::ptrdiff_t; code() if cls._base: - code('%import "python/m5/internal/param_${{cls._base}}.i"') + code('%import "python/_m5/param_${{cls._base}}.i"') code() for ns in namespaces: diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 9df3f4bfe..1edf933f9 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -32,15 +32,16 @@ try: # Try to import something that's generated by swig - import internal.core + import _m5.core # Try to grab something from it in case demandimport is being used - internal.core.curTick + _m5.core.curTick + in_gem5 = True except ImportError: - # The import failed - internal = None + # The import failed, we're being called from the build system + in_gem5 = False -if internal: +if in_gem5: import SimObject import core import objects diff --git a/src/python/m5/core.py b/src/python/m5/core.py index 8fa3d6fac..ab0ea57ea 100644 --- a/src/python/m5/core.py +++ b/src/python/m5/core.py @@ -26,7 +26,4 @@ # # Authors: Nathan Binkert -import internal - -def setOutputDir(dir): - internal.core.setOutputDir(dir) +from _m5.core import setOutputDir diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py index 22b16aa5b..75566decd 100644 --- a/src/python/m5/debug.py +++ b/src/python/m5/debug.py @@ -28,10 +28,9 @@ from UserDict import DictMixin -import internal - -from internal.debug import SimpleFlag, CompoundFlag -from internal.debug import schedBreak, setRemoteGDBPort +import _m5.debug +from _m5.debug import SimpleFlag, CompoundFlag +from _m5.debug import schedBreak, setRemoteGDBPort from m5.util import printList def help(): @@ -61,12 +60,12 @@ class AllFlags(DictMixin): self._dict = {} def _update(self): - current_version = internal.debug.getAllFlagsVersion() + current_version = _m5.debug.getAllFlagsVersion() if self._version == current_version: return self._dict.clear() - for flag in internal.debug.getAllFlags(): + for flag in _m5.debug.getAllFlags(): self._dict[flag.name()] = flag self._version = current_version diff --git a/src/python/m5/event.py b/src/python/m5/event.py index 76fc37042..41daa8d3e 100644 --- a/src/python/m5/event.py +++ b/src/python/m5/event.py @@ -29,9 +29,9 @@ # Authors: Nathan Binkert import m5 -import internal.event +import _m5.event -from internal.event import PythonEvent, GlobalSimLoopExitEvent as SimExit +from _m5.event import PythonEvent, GlobalSimLoopExitEvent as SimExit mainq = None @@ -61,9 +61,9 @@ class ProgressEvent(Event): self.eventq.schedule(self, m5.curTick() + self.period) def getEventQueue(index): - return internal.event.getEventQueue(index) + return _m5.event.getEventQueue(index) def setEventQueue(eventq): - internal.event.curEventQueue(eventq) + _m5.event.curEventQueue(eventq) __all__ = [ 'create', 'Event', 'ProgressEvent', 'SimExit', 'mainq' ] diff --git a/src/python/m5/internal/params.py b/src/python/m5/internal/params.py index 20e62b2f7..2d3f7c1ca 100644 --- a/src/python/m5/internal/params.py +++ b/src/python/m5/internal/params.py @@ -32,6 +32,6 @@ except NameError: modules = { } for module in modules.iterkeys(): - if module.startswith('m5.internal.param_') or \ - module.startswith('m5.internal.enum_'): + if module.startswith('_m5.param_') or \ + module.startswith('_m5.enum_'): exec "from %s import *" % module diff --git a/src/python/m5/params.py b/src/python/m5/params.py index ac777fad2..ae2b74a23 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -386,7 +386,7 @@ class VectorParamDesc(ParamDesc): code('%import "${{self.swig_module_name()}}.i"') def swig_decl(self, code): - code('%module(package="m5.internal") ${{self.swig_module_name()}}') + code('%module(package="_m5") ${{self.swig_module_name()}}') code('%{') self.ptype.cxx_predecls(code) code('%}') @@ -619,7 +619,7 @@ class Cycles(CheckedInt): unsigned = True def getValue(self): - from m5.internal.core import Cycles + from _m5.core import Cycles return Cycles(self.value) @classmethod @@ -828,7 +828,7 @@ class AddrRange(ParamValue): def getValue(self): # Go from the Python class to the wrapped C++ class generated # by swig - from m5.internal.range import AddrRange + from _m5.range import AddrRange return AddrRange(long(self.start), long(self.end), int(self.intlvHighBit), int(self.xorHighBit), @@ -1378,7 +1378,7 @@ $wrapper $wrapper_name { def swig_decl(cls, code): name = cls.__name__ code('''\ -%module(package="m5.internal") enum_$name +%module(package="_m5") enum_$name %{ #include "enums/$name.hh" @@ -1419,7 +1419,7 @@ class Enum(ParamValue): @classmethod def swig_predecls(cls, code): - code('%import "python/m5/internal/enum_$0.i"', cls.__name__) + code('%import "python/_m5/enum_$0.i"', cls.__name__) @classmethod def cxx_ini_parse(cls, code, src, dest, ret): @@ -1909,7 +1909,7 @@ class PortRef(object): # Call C++ to create corresponding port connection between C++ objects def ccConnect(self): - from m5.internal.pyobject import connectPorts + from _m5.pyobject import connectPorts if self.role == 'SLAVE': # do nothing and let the master take care of it diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index b3ae367ba..af5eebded 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -45,14 +45,15 @@ import os import sys # import the SWIG-wrapped main C++ functions -import internal -import core +import _m5.drain +import _m5.core +from _m5.stats import updateEvents as updateStatEvents + import stats import SimObject import ticks import objects from m5.util.dot_writer import do_dot, do_dvfs_dot -from m5.internal.stats import updateEvents as updateStatEvents from util import fatal from util import attrdict @@ -66,7 +67,7 @@ _memory_modes = { "atomic_noncaching" : objects.params.atomic_noncaching, } -_drain_manager = internal.drain.DrainManager.instance() +_drain_manager = _m5.drain.DrainManager.instance() # The final hook to generate .ini files. Called from the user script # once the config is built. @@ -138,8 +139,8 @@ def instantiate(ckpt_dir=None): # Restore checkpoint (if any) if ckpt_dir: _drain_manager.preCheckpointRestore() - ckpt = internal.core.getCheckpoint(ckpt_dir) - internal.core.unserializeGlobals(ckpt); + ckpt = _m5.core.getCheckpoint(ckpt_dir) + _m5.core.unserializeGlobals(ckpt); for obj in root.descendants(): obj.loadState(ckpt) else: for obj in root.descendants(): obj.initState() @@ -162,7 +163,7 @@ def simulate(*args, **kwargs): atexit.register(stats.dump) # register our C++ exit callback function with Python - atexit.register(internal.core.doExitCleanup) + atexit.register(_m5.core.doExitCleanup) # Reset to put the stats in a consistent state. stats.reset() @@ -170,11 +171,7 @@ def simulate(*args, **kwargs): if _drain_manager.isDrained(): _drain_manager.resume() - return internal.event.simulate(*args, **kwargs) - -# Export curTick to user script. -def curTick(): - return internal.core.curTick() + return _m5.event.simulate(*args, **kwargs) def drain(): """Drain the simulator in preparation of a checkpoint or memory mode @@ -198,7 +195,7 @@ def drain(): # WARNING: if a valid exit event occurs while draining, it # will not get returned to the user script - exit_event = internal.event.simulate() + exit_event = _m5.event.simulate() while exit_event.getCause() != 'Finished drain': exit_event = simulate() @@ -227,7 +224,7 @@ def checkpoint(dir): drain() memWriteback(root) print "Writing checkpoint" - internal.core.serializeAll(dir) + _m5.core.serializeAll(dir) def _changeMemoryMode(system, mode): if not isinstance(system, (objects.Root, objects.System)): @@ -343,7 +340,7 @@ def fork(simout="%(parent)s.f%(fork_seq)i"): from m5 import options global fork_count - if not internal.core.listenersDisabled(): + if not _m5.core.listenersDisabled(): raise RuntimeError, "Can not fork a simulator with listeners enabled" drain() @@ -364,11 +361,11 @@ def fork(simout="%(parent)s.f%(fork_seq)i"): "fork_seq" : fork_count, "pid" : os.getpid(), } - core.setOutputDir(options.outdir) + _m5.core.setOutputDir(options.outdir) else: fork_count += 1 return pid -from internal.core import disableAllListeners -from internal.core import listenersDisabled +from _m5.core import disableAllListeners, listenersDisabled +from _m5.core import curTick diff --git a/src/python/m5/stats/__init__.py b/src/python/m5/stats/__init__.py index f3d394311..56036e040 100644 --- a/src/python/m5/stats/__init__.py +++ b/src/python/m5/stats/__init__.py @@ -29,22 +29,22 @@ import m5 -from m5 import internal +import _m5.stats from m5.objects import Root from m5.util import attrdict, fatal # Stat exports -from m5.internal.stats import schedStatEvent as schedEvent -from m5.internal.stats import periodicStatDump +from _m5.stats import schedStatEvent as schedEvent +from _m5.stats import periodicStatDump outputList = [] def initText(filename, desc=True): - output = internal.stats.initText(filename, desc) + output = _m5.stats.initText(filename, desc) outputList.append(output) def initSimStats(): - internal.stats.initSimStats() - internal.stats.registerPythonStatsHandlers() + _m5.stats.initSimStats() + _m5.stats.registerPythonStatsHandlers() names = [] stats_dict = {} @@ -55,7 +55,7 @@ def enable(): the package is enabled, no more statistics can be created.''' global stats_list - stats_list = list(internal.stats.statsList()) + stats_list = list(_m5.stats.statsList()) for stat in stats_list: if not stat.check() or not stat.baseCheck(): @@ -75,7 +75,7 @@ def enable(): stats_dict[stat.name] = stat stat.enable() - internal.stats.enable(); + _m5.stats.enable(); def prepare(): '''Prepare all stats for data access. This must be done before @@ -96,7 +96,7 @@ def dump(): return lastDump = curTick - internal.stats.processDumpQueue() + _m5.stats.processDumpQueue() prepare() @@ -119,7 +119,7 @@ def reset(): for stat in stats_list: stat.reset() - internal.stats.processResetQueue() + _m5.stats.processResetQueue() flags = attrdict({ 'none' : 0x0000, diff --git a/src/python/m5/ticks.py b/src/python/m5/ticks.py index 0d82f6edd..ce9459f2a 100644 --- a/src/python/m5/ticks.py +++ b/src/python/m5/ticks.py @@ -34,11 +34,11 @@ tps_fixed = False # once set to true, can't be changed # fix the global frequency and tell C++ about it def fixGlobalFrequency(): - import internal + import _m5.core global tps, tps_fixed if not tps_fixed: tps_fixed = True - internal.core.setClockFrequency(int(tps)) + _m5.core.setClockFrequency(int(tps)) print "Global frequency set at %d ticks per second" % int(tps) def setGlobalFrequency(ticksPerSecond): diff --git a/src/python/m5/trace.py b/src/python/m5/trace.py index a78b77fc1..ca98ebdc4 100644 --- a/src/python/m5/trace.py +++ b/src/python/m5/trace.py @@ -26,13 +26,5 @@ # # Authors: Nathan Binkert -import internal -import util - -from internal.trace import output, ignore - -def disable(): - internal.trace.disable() - -def enable(): - internal.trace.enable() +# Export native methods to Python +from _m5.trace import output, ignore, disable, enable diff --git a/src/python/swig/core.i b/src/python/swig/core.i index 08fbe01d1..45337c3a5 100644 --- a/src/python/swig/core.i +++ b/src/python/swig/core.i @@ -29,7 +29,7 @@ * Steve Reinhardt */ -%module(package="m5.internal") core +%module(package="_m5") core %{ #include "base/misc.hh" diff --git a/src/python/swig/debug.i b/src/python/swig/debug.i index c2eb3ed80..b05b66e47 100644 --- a/src/python/swig/debug.i +++ b/src/python/swig/debug.i @@ -29,7 +29,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") debug +%module(package="_m5") debug %{ #include <cassert> diff --git a/src/python/swig/drain.i b/src/python/swig/drain.i index 59474f190..8bd7ef9ef 100644 --- a/src/python/swig/drain.i +++ b/src/python/swig/drain.i @@ -37,7 +37,7 @@ * Authors: Andreas Sandberg */ -%module(package="m5.internal") drain +%module(package="_m5") drain %{ #include "sim/drain.hh" diff --git a/src/python/swig/event.i b/src/python/swig/event.i index 60a789c1a..464be8289 100644 --- a/src/python/swig/event.i +++ b/src/python/swig/event.i @@ -30,7 +30,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") event +%module(package="_m5") event %{ #include "base/types.hh" diff --git a/src/python/swig/pyobject.i b/src/python/swig/pyobject.i index a26f569ce..d4601d6a9 100644 --- a/src/python/swig/pyobject.i +++ b/src/python/swig/pyobject.i @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") pyobject +%module(package="_m5") pyobject %{ #include "python/swig/pyobject.hh" diff --git a/src/python/swig/range.i b/src/python/swig/range.i index e3a794310..7ee27679f 100644 --- a/src/python/swig/range.i +++ b/src/python/swig/range.i @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") range +%module(package="_m5") range %{ #include "base/types.hh" diff --git a/src/python/swig/serialize.i b/src/python/swig/serialize.i index 9a232fb09..2ade6157a 100644 --- a/src/python/swig/serialize.i +++ b/src/python/swig/serialize.i @@ -37,7 +37,7 @@ * Authors: Andreas Sandberg */ -%module(package="m5.internal") serialize +%module(package="_m5") serialize %{ #include "sim/serialize.hh" diff --git a/src/python/swig/stats.i b/src/python/swig/stats.i index b9da5a5ad..c22cd45a3 100644 --- a/src/python/swig/stats.i +++ b/src/python/swig/stats.i @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") stats +%module(package="_m5") stats %include <std_list.i> %include <std_string.i> diff --git a/src/python/swig/trace.i b/src/python/swig/trace.i index 48caf456a..9ea60b816 100644 --- a/src/python/swig/trace.i +++ b/src/python/swig/trace.i @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") trace +%module(package="_m5") trace %{ #include "base/trace.hh" diff --git a/src/unittest/SConscript b/src/unittest/SConscript index 0275cdb42..2737be8f5 100644 --- a/src/unittest/SConscript +++ b/src/unittest/SConscript @@ -46,7 +46,7 @@ UnitTest('strnumtest', 'strnumtest.cc') UnitTest('trietest', 'trietest.cc') stattest_py = PySource('m5', 'stattestmain.py', skip_lib=True) -stattest_swig = SwigSource('m5.internal', 'stattest.i', skip_lib=True) +stattest_swig = SwigSource('_m5', 'stattest.i', skip_lib=True) UnitTest('stattest', 'stattest.cc', stattest_py, stattest_swig, main=True) UnitTest('symtest', 'symtest.cc') diff --git a/src/unittest/stattest.i b/src/unittest/stattest.i index 0cc9192ba..66990689f 100644 --- a/src/unittest/stattest.i +++ b/src/unittest/stattest.i @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -%module(package="m5.internal") stattest +%module(package="_m5") stattest %inline %{ extern void stattest_init(); diff --git a/src/unittest/stattestmain.py b/src/unittest/stattestmain.py index 2c0a4a9aa..70fef59be 100644 --- a/src/unittest/stattestmain.py +++ b/src/unittest/stattestmain.py @@ -1,5 +1,5 @@ def main(): - from m5.internal.stattest import stattest_init, stattest_run + from _m5.stattest import stattest_init, stattest_run import m5.stats stattest_init() diff --git a/tests/configs/switcheroo.py b/tests/configs/switcheroo.py index 56eafa613..43a20353e 100644 --- a/tests/configs/switcheroo.py +++ b/tests/configs/switcheroo.py @@ -36,6 +36,7 @@ # Authors: Andreas Sandberg import m5 +import _m5 from m5.objects import * m5.util.addToPath('../configs/') from common.Caches import * @@ -104,7 +105,7 @@ def run_test(root, switcher=None, freq=1000, verbose=False): # Suppress "Entering event queue" messages since we get tons of them. # Worse yet, they include the timestamp, which makes them highly # variable and unsuitable for comparing as test outputs. - m5.internal.core.cvar.want_info = verbose + _m5.core.cvar.want_info = verbose # instantiate configuration m5.instantiate() |