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| author | Michael LeBeane <michael.lebeane@amd.com> | 2016-09-13 23:18:34 -0400 |
|---|---|---|
| committer | Michael LeBeane <michael.lebeane@amd.com> | 2016-09-13 23:18:34 -0400 |
| commit | 2c43a21687b861bae462bea555c5875a4d0a91c8 (patch) | |
| tree | e2b74d5feea830f7092a2cce9f94cf40de7cb8f0 | |
| parent | 458d4a3c7bff9365e9d732c56f105b5b7bd37739 (diff) | |
| download | gem5-2c43a21687b861bae462bea555c5875a4d0a91c8.tar.xz | |
x86: Force strict ordering for memory mapped m5ops
Normal MMAPPED_IPR requests are allowed to execute speculatively under the
assumption that they have no side effects. The special case of m5ops that are
treated like MMAPPED_IPR should not be allowed to execute speculatively, since
they can have side-effects. Adding the STRICT_ORDER flag to these requests
blocks execution until the associated instruction hits the ROB head.
| -rw-r--r-- | src/arch/x86/tlb.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index be43cb06e..0e0878669 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -235,7 +235,8 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const if (m5opRange.contains(paddr)) { if (m5opRange.contains(paddr)) { - req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); + req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | + Request::STRICT_ORDER); req->setPaddr(GenericISA::iprAddressPseudoInst( (paddr >> 8) & 0xFF, paddr & 0xFF)); |