diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-02-27 18:17:37 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-02-27 18:17:37 -0500 |
| commit | 2f41006e448a6af11dcf36b7804edd91c7710bda (patch) | |
| tree | f2aafec082f1ff9d96c605a29da09329abb1aa37 | |
| parent | e6d6adc7316cdb6e12aa6f125c60b01315147579 (diff) | |
| download | gem5-2f41006e448a6af11dcf36b7804edd91c7710bda.tar.xz | |
Update outputs for quick tests to reflect fixed cache stats.
Will update long tests later.
--HG--
extra : convert_revision : 79f66b5761a574f0c8049c1c771c353b42942993
16 files changed, 247 insertions, 247 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cd20f37b3..cd104d2c8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 425 # Nu global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted global.BPredUnit.lookups 2013 # Number of BP lookups global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44115 # Simulator instruction rate (inst/s) -host_mem_usage 194668 # Number of bytes of host memory used +host_inst_rate 44727 # Simulator instruction rate (inst/s) +host_mem_usage 151980 # Number of bytes of host memory used host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 41555653 # Simulator tick rate (ticks/s) +host_tick_rate 42091644 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. @@ -51,61 +51,61 @@ system.cpu.committedInsts 5623 # Nu system.cpu.committedInsts_total 5623 # Number of Instructions Simulated system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14760.204082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.064010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.064010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 528 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 36879.310345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.164773 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.164773 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.111765 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2059 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25162.162162 # average overall miss latency +system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.089849 # miss rate for demand accesses -system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses +system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.089849 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2059 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25162.162162 # average overall miss latency +system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1874 # number of overall hits system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.089849 # miss rate for overall accesses -system.cpu.dcache.overall_misses 185 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses +system.cpu.dcache.overall_misses 504 # number of overall misses system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.089849 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1889 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked @@ -171,16 +171,16 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10214.516129 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 310 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202614 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked @@ -190,31 +190,31 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1530 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10214.516129 # average overall miss latency +system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202614 # miss rate for demand accesses -system.cpu.icache.demand_misses 310 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses +system.cpu.icache.demand_misses 345 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202614 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1530 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10214.516129 # average overall miss latency +system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1220 # number of overall hits system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202614 # miss rate for overall accesses -system.cpu.icache.overall_misses 310 # number of overall misses +system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses +system.cpu.icache.overall_misses 345 # number of overall misses system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202614 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 26249ed90..5992f7131 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index d2d2e40dc..fc63a59a9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 13:00:08 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:52:16 +M5 started Wed Feb 27 17:56:32 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 5303000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index a5a67b31d..b9f64c44d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 209 # Nu global.BPredUnit.condPredicted 405 # Number of conditional branches predicted global.BPredUnit.lookups 821 # Number of BP lookups global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. -host_inst_rate 34209 # Simulator instruction rate (inst/s) -host_mem_usage 193660 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 38614456 # Simulator tick rate (ticks/s) +host_inst_rate 39438 # Simulator instruction rate (inst/s) +host_mem_usage 151264 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 44410086 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit. @@ -51,61 +51,61 @@ system.cpu.committedInsts 2387 # Nu system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 531 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 11663.934426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.114878 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114878 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 230 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26567.567568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.160870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.160870 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.952941 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 761 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17290.816327 # average overall miss latency +system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.128778 # miss rate for demand accesses -system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses +system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.128778 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 761 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17290.816327 # average overall miss latency +system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 663 # number of overall hits system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.128778 # miss rate for overall accesses -system.cpu.dcache.overall_misses 98 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses +system.cpu.dcache.overall_misses 173 # number of overall misses system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.128778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use -system.cpu.dcache.total_refs 676 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked @@ -171,16 +171,16 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 10041.208791 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.266862 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.266862 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked @@ -190,31 +190,31 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 682 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 10041.208791 # average overall miss latency +system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency system.cpu.icache.demand_hits 500 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.266862 # miss rate for demand accesses -system.cpu.icache.demand_misses 182 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses +system.cpu.icache.demand_misses 205 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.266862 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 682 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 10041.208791 # average overall miss latency +system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 500 # number of overall hits system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.266862 # miss rate for overall accesses -system.cpu.icache.overall_misses 182 # number of overall misses +system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses +system.cpu.icache.overall_misses 205 # number of overall misses system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.266862 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index f26dcb93f..298b6fba0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index b6bb2d255..95bc632c8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 13:00:07 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:52:16 +M5 started Wed Feb 27 17:56:33 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 2700000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 5ff297de6..4a5d707e1 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1125 # Nu global.BPredUnit.condPredicted 2392 # Number of conditional branches predicted global.BPredUnit.lookups 4127 # Number of BP lookups global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 53078 # Simulator instruction rate (inst/s) -host_mem_usage 195244 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 30008914 # Simulator tick rate (ticks/s) +host_inst_rate 41846 # Simulator instruction rate (inst/s) +host_mem_usage 152588 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 23650670 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. memdepunit.memDep.conflictingStores 33 # Number of conflicting stores. @@ -71,55 +71,55 @@ system.cpu.committedInsts_total 11247 # Nu system.cpu.cpi_0 2.263383 # CPI: Cycles Per Instruction system.cpu.cpi_1 2.262980 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.131591 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 17652.284264 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 3079 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3079 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 2792 # number of ReadReq hits system.cpu.dcache.ReadReq_hits_0 2792 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 3477500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency_0 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.065908 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 197 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 197 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate_0 0.093212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 287 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 287 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits_0 90 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 2074000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.065908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.063982 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 197 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses_0 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1183 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1183 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 32304.597701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 9139.837398 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8686.781609 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1009 # number of WriteReq hits system.cpu.dcache.WriteReq_hits_0 1009 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 5621000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency_0 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.147084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate_0 0.378695 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 615 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 441 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits_0 441 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 1511500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency_0 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.147084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.107143 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.198830 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.266082 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4172 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4172 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4703 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 24524.258760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency @@ -131,10 +131,10 @@ system.cpu.dcache.demand_miss_latency 9098500 # nu system.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.088926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 371 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 902 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hits @@ -143,7 +143,7 @@ system.cpu.dcache.demand_mshr_miss_latency 3585500 # system.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.088926 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR misses @@ -153,11 +153,11 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4172 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4172 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 24524.258760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency @@ -172,10 +172,10 @@ system.cpu.dcache.overall_miss_latency 9098500 # nu system.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.088926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 371 # number of overall misses -system.cpu.dcache.overall_misses_0 371 # number of overall misses +system.cpu.dcache.overall_misses 902 # number of overall misses +system.cpu.dcache.overall_misses_0 902 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses system.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hits @@ -184,7 +184,7 @@ system.cpu.dcache.overall_mshr_miss_latency 3585500 # system.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.088926 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR misses @@ -212,7 +212,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in use -system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 3853 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks @@ -263,22 +263,22 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 11625 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 3105 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3105 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7742.694805 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2401 # number of ReadReq hits system.cpu.icache.ReadReq_hits_0 2401 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 7161000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency_0 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.204176 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 616 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 616 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate_0 0.226731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 88 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits_0 88 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 4769500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency_0 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.204176 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.198390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 616 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses_0 616 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -289,11 +289,11 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3017 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3017 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3105 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3105 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 11625 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 10171.875000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency @@ -305,10 +305,10 @@ system.cpu.icache.demand_miss_latency 7161000 # nu system.cpu.icache.demand_miss_latency_0 7161000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.204176 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.226731 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 616 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 616 # number of demand (read+write) misses +system.cpu.icache.demand_misses 704 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_0 88 # number of demand (read+write) MSHR hits @@ -317,7 +317,7 @@ system.cpu.icache.demand_mshr_miss_latency 4769500 # system.cpu.icache.demand_mshr_miss_latency_0 4769500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.204176 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.198390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 616 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_0 616 # number of demand (read+write) MSHR misses @@ -327,11 +327,11 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3017 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3017 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3105 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3105 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 11625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 10171.875000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency @@ -346,10 +346,10 @@ system.cpu.icache.overall_miss_latency 7161000 # nu system.cpu.icache.overall_miss_latency_0 7161000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.204176 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.226731 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 616 # number of overall misses -system.cpu.icache.overall_misses_0 616 # number of overall misses +system.cpu.icache.overall_misses 704 # number of overall misses +system.cpu.icache.overall_misses_0 704 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses system.cpu.icache.overall_mshr_hits 88 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_0 88 # number of overall MSHR hits @@ -358,7 +358,7 @@ system.cpu.icache.overall_mshr_miss_latency 4769500 # system.cpu.icache.overall_mshr_miss_latency_0 4769500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.204176 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.198390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 616 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_0 616 # number of overall MSHR misses diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index d4c363b88..0ce82a0be 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,5 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -0: system.remote_gdb.listener: listening for remote gdb on port 7008 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 2035a5635..9d1a14d46 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 12:58:27 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:52:16 +M5 started Wed Feb 27 17:56:35 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 6363000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index effb5fdd8..29c5e75be 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 2011 # Nu global.BPredUnit.condPredicted 7546 # Number of conditional branches predicted global.BPredUnit.lookups 7546 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 35519 # Simulator instruction rate (inst/s) -host_mem_usage 195624 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -host_tick_rate 52488986 # Simulator tick rate (ticks/s) +host_inst_rate 33487 # Simulator instruction rate (inst/s) +host_mem_usage 153160 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +host_tick_rate 49468437 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. @@ -51,63 +51,63 @@ system.cpu.committedInsts 10411 # Nu system.cpu.committedInsts_total 10411 # Number of Instructions Simulated system.cpu.cpi 2.957065 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.957065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2271 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13053.030303 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9364.130435 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7068.181818 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 2205 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 861500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029062 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 66 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.040052 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 466500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.029062 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.028733 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1167 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 21642.857143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 9880.434783 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6966.666667 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1062 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2272500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.089974 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.178019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 230 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 125 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 731500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.657895 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.736842 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3438 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18327.485380 # average overall miss latency +system.cpu.dcache.demand_accesses 3589 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9732.919255 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency system.cpu.dcache.demand_hits 3267 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 3134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.049738 # miss rate for demand accesses -system.cpu.dcache.demand_misses 171 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.089719 # miss rate for demand accesses +system.cpu.dcache.demand_misses 322 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 151 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 1198000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.049738 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.047646 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3438 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18327.485380 # average overall miss latency +system.cpu.dcache.overall_accesses 3589 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9732.919255 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 3267 # number of overall hits system.cpu.dcache.overall_miss_latency 3134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.049738 # miss rate for overall accesses -system.cpu.dcache.overall_misses 171 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.089719 # miss rate for overall accesses +system.cpu.dcache.overall_misses 322 # number of overall misses system.cpu.dcache.overall_mshr_hits 151 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 1198000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.049738 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.047646 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -124,7 +124,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 110.780967 # Cycle average of tags in use -system.cpu.dcache.total_refs 3292 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 3304 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 4065 # Number of cycles decode is blocked @@ -158,16 +158,16 @@ system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 4860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9979.729730 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 4905 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8897.590361 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6462.162162 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4490 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 3692500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.076132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.084608 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 415 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 2391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.076132 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.075433 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked @@ -177,31 +177,31 @@ system.cpu.icache.blocked_no_targets 0 # nu system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4860 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9979.729730 # average overall miss latency +system.cpu.icache.demand_accesses 4905 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8897.590361 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency system.cpu.icache.demand_hits 4490 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 3692500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.076132 # miss rate for demand accesses -system.cpu.icache.demand_misses 370 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.084608 # miss rate for demand accesses +system.cpu.icache.demand_misses 415 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.076132 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.075433 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4860 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9979.729730 # average overall miss latency +system.cpu.icache.overall_accesses 4905 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8897.590361 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4490 # number of overall hits system.cpu.icache.overall_miss_latency 3692500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.076132 # miss rate for overall accesses -system.cpu.icache.overall_misses 370 # number of overall misses +system.cpu.icache.overall_miss_rate 0.084608 # miss rate for overall accesses +system.cpu.icache.overall_misses 415 # number of overall misses system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.076132 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.075433 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index b6c7cd528..ee061a6c6 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 12:17:27 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:54:12 +M5 started Wed Feb 27 18:07:27 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 15392500 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 9172a68f7..85a08a7e2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 737386 # Simulator instruction rate (inst/s) -host_mem_usage 319080 # Number of bytes of host memory used -host_seconds 85.79 # Real time elapsed on the host -host_tick_rate 22995378041 # Simulator tick rate (ticks/s) +host_inst_rate 647923 # Simulator instruction rate (inst/s) +host_mem_usage 252928 # Number of bytes of host memory used +host_seconds 97.63 # Real time elapsed on the host +host_tick_rate 20205445341 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63257216 # Number of instructions simulated sim_seconds 1.972680 # Number of seconds simulated @@ -622,17 +622,17 @@ system.l2c.ReadExReq_misses 307159 # nu system.l2c.ReadExReq_mshr_miss_latency 3380143000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 307159 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2746056 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 23013.053198 # average ReadReq miss latency +system.l2c.ReadReq_accesses 2746067 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 23012.790348 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 11012.812299 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_hits 1782997 # number of ReadReq hits system.l2c.ReadReq_miss_latency 22162928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.350706 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 963059 # number of ReadReq misses +system.l2c.ReadReq_miss_rate 0.350709 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 963070 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 10605988000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.350706 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate 0.350705 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 963059 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 779852500 # number of ReadReq MSHR uncacheable cycles system.l2c.UpgradeReq_accesses 127459 # number of UpgradeReq accesses(hits+misses) @@ -656,31 +656,31 @@ system.l2c.blocked_no_targets 0 # nu system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3053215 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 23010.994176 # average overall miss latency +system.l2c.demand_accesses 3053226 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 23010.794904 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency system.l2c.demand_hits 1782997 # number of demand (read+write) hits system.l2c.demand_miss_latency 29228979000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.416026 # miss rate for demand accesses -system.l2c.demand_misses 1270218 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.416028 # miss rate for demand accesses +system.l2c.demand_misses 1270229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 13986131000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.416026 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate 0.416025 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 1270218 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3053215 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 23010.994176 # average overall miss latency +system.l2c.overall_accesses 3053226 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 23010.794904 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 11010.811530 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.overall_hits 1782997 # number of overall hits system.l2c.overall_miss_latency 29228979000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.416026 # miss rate for overall accesses -system.l2c.overall_misses 1270218 # number of overall misses +system.l2c.overall_miss_rate 0.416028 # miss rate for overall accesses +system.l2c.overall_misses 1270229 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 13986131000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.416026 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate 0.416025 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 1270218 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2150633500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index ba95d24cb..b0bbb3d67 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,6 +1,6 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux -Listening for system connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -0: system.remote_gdb.listener: listening for remote gdb on port 7009 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 478619000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index a1e7d0c6d..84f4de778 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 13:18:14 -M5 started Sun Feb 24 13:19:24 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:52:52 +M5 started Wed Feb 27 18:02:58 2008 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1972679592000 because m5_exit instruction encountered diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 01cfb7bb5..f7b90230a 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 374920 # Number of bytes of host memory used -host_seconds 187.04 # Real time elapsed on the host -host_tick_rate 606647 # Simulator tick rate (ticks/s) +host_mem_usage 323140 # Number of bytes of host memory used +host_seconds 197.60 # Real time elapsed on the host +host_tick_rate 574221 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000113 # Number of seconds simulated sim_ticks 113467820 # Number of ticks simulated @@ -638,38 +638,38 @@ system.cpu7.l1c.writebacks 10985 # nu system.cpu7.num_copies 0 # number of copy accesses completed system.cpu7.num_reads 99331 # number of read accesses completed system.cpu7.num_writes 53962 # number of write accesses completed -system.l2c.ReadExReq_accesses 74680 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 20085.692461 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses 75034 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 19990.930951 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 10006.831093 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 1499999513 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 74680 # number of ReadExReq misses +system.l2c.ReadExReq_misses 75034 # number of ReadExReq misses system.l2c.ReadExReq_mshr_hits 354 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_miss_latency 747310146 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate 0.995282 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 74680 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138650 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 20215.443305 # average ReadReq miss latency +system.l2c.ReadReq_accesses 139261 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 19959.179983 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 10007.689712 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_hits 91062 # number of ReadReq hits system.l2c.ReadReq_miss_latency 962012516 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.343224 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 47588 # number of ReadReq misses +system.l2c.ReadReq_miss_rate 0.346106 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 48199 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 611 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 476245938 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.343224 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate 0.341718 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 47588 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 793404880 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18486 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11037.307260 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses 18516 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 11019.424390 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 10007.005085 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 204035662 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18486 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses 18516 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_miss_latency 184989496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate 0.998380 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 18486 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 430707040 # number of WriteReq MSHR uncacheable cycles @@ -683,31 +683,31 @@ system.l2c.blocked_no_targets 0 # nu system.l2c.blocked_cycles_no_mshrs 17459 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 213330 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 20136.192863 # average overall miss latency +system.l2c.demand_accesses 214295 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 19978.512484 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency system.l2c.demand_hits 91062 # number of demand (read+write) hits system.l2c.demand_miss_latency 2462012029 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.573140 # miss rate for demand accesses -system.l2c.demand_misses 122268 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.575062 # miss rate for demand accesses +system.l2c.demand_misses 123233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 965 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 1223556084 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.573140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate 0.570559 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 122268 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 213330 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 20136.192863 # average overall miss latency +system.l2c.overall_accesses 214295 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 19978.512484 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 10007.165276 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.overall_hits 91062 # number of overall hits system.l2c.overall_miss_latency 2462012029 # number of overall miss cycles -system.l2c.overall_miss_rate 0.573140 # miss rate for overall accesses -system.l2c.overall_misses 122268 # number of overall misses +system.l2c.overall_miss_rate 0.575062 # miss rate for overall accesses +system.l2c.overall_misses 123233 # number of overall misses system.l2c.overall_mshr_hits 965 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 1223556084 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.573140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate 0.570559 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 122268 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1224111920 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3df001a17..3088b7501 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2008 12:58:20 -M5 started Sun Feb 24 13:01:36 2008 -M5 executing on tater +M5 compiled Feb 27 2008 17:52:16 +M5 started Wed Feb 27 17:56:37 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second Exiting @ tick 113467820 because maximum number of loads reached |