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authorGabe Black <gblack@eecs.umich.edu>2007-04-14 17:07:24 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-14 17:07:24 +0000
commit3140dd88bc588ea51aadeb2dd58d33cc9a40883a (patch)
treeb86ad074a4ec1a9696c133bb0814c95b6efe7937
parente9c6012acf729ef55b37dda76e011b5a284b6988 (diff)
downloadgem5-3140dd88bc588ea51aadeb2dd58d33cc9a40883a.tar.xz
Make the fsr a serializing register. Other control registers probably need this as well.
--HG-- extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6
-rw-r--r--src/arch/sparc/isa/operands.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 58d616a7a..110b37d15 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -187,7 +187,7 @@ def operands {{
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)