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authorGabe Black <gblack@eecs.umich.edu>2007-07-24 15:07:35 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-24 15:07:35 -0700
commit340ce8e680596b420095cb9d15bd544866a5a718 (patch)
tree6034d16708baa6fb8d6ef26b98480e5edfd1153b
parent28614addffabd2bd8c12b7fdd97815e1579f11bb (diff)
downloadgem5-340ce8e680596b420095cb9d15bd544866a5a718.tar.xz
Implement cmov.
--HG-- extra : convert_revision : 2e92623b53c1fe8b4da3fef3486c0dcd8d5ef9f5
-rw-r--r--src/arch/x86/isa/insts/data_transfer/conditional_move.py294
1 files changed, 289 insertions, 5 deletions
diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
index 513e90c4e..17f8841f2 100644
--- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
@@ -53,8 +53,292 @@
#
# Authors: Gabe Black
-microcode = ""
-#let {{
-# class CMOVcc(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop CMOVZ_R_R
+{
+ mov reg, reg, regm, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVNZ_R_R
+{
+ mov reg, reg, regm, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVB_R_R
+{
+ mov reg, reg, regm, flags=(CCF,)
+};
+
+def macroop CMOVB_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVB_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVNB_R_R
+{
+ mov reg, reg, regm, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVBE_R_R
+{
+ mov reg, reg, regm, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVNBE_R_R
+{
+ mov reg, reg, regm, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVS_R_R
+{
+ mov reg, reg, regm, flags=(CSF,)
+};
+
+def macroop CMOVS_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVS_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVNS_R_R
+{
+ mov reg, reg, regm, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVP_R_R
+{
+ mov reg, reg, regm, flags=(CPF,)
+};
+
+def macroop CMOVP_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVP_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVNP_R_R
+{
+ mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVL_R_R
+{
+ mov reg, reg, regm, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVNL_R_R
+{
+ mov reg, reg, regm, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVLE_R_R
+{
+ mov reg, reg, regm, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVNLE_R_R
+{
+ mov reg, reg, regm, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVO_R_R
+{
+ mov reg, reg, regm, flags=(COF,)
+};
+
+def macroop CMOVO_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVO_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVNO_R_R
+{
+ mov reg, reg, regm, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_M
+{
+ ld t1, ds, [scale, index, base], disp
+ mov reg, reg, t1, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ mov reg, reg, t1, flags=(nCOF,)
+};
+'''