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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:18 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:18 -0500 |
| commit | 35e35fc825ac1297ba5e1334ac177b0a40329110 (patch) | |
| tree | 8bf8f486447837839a0d6662f3320569b7781639 | |
| parent | 0abec5356427798568cc0008add4a4038443c548 (diff) | |
| download | gem5-35e35fc825ac1297ba5e1334ac177b0a40329110.tar.xz | |
ARM: Make some of the trace code more compact
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 3dde0aa35..552803b6a 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -60,18 +60,10 @@ MemoryReg::printOffset(std::ostream &os) const ccprintf(os, " LSL #%d", shiftAmt); break; case LSR: - if (shiftAmt == 0) { - ccprintf(os, " LSR #%d", 32); - } else { - ccprintf(os, " LSR #%d", shiftAmt); - } + ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt); break; case ASR: - if (shiftAmt == 0) { - ccprintf(os, " ASR #%d", 32); - } else { - ccprintf(os, " ASR #%d", shiftAmt); - } + ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt); break; case ROR: if (shiftAmt == 0) { |