diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
236 files changed, 34322 insertions, 34511 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9e5305367..94dc81bdc 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:31:55 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:55 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107002000 -Exiting @ tick 1899401490000 because m5_exit instruction encountered +info: Launching CPU 1 @ 106801000 +Exiting @ tick 1896395899500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e3ecd4b02..0c462a770 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899401 # Number of seconds simulated -sim_ticks 1899401490000 # Number of ticks simulated -final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.896396 # Number of seconds simulated +sim_ticks 1896395899500 # Number of ticks simulated +final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124517 # Simulator instruction rate (inst/s) -host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4182952627 # Simulator tick rate (ticks/s) -host_mem_usage 300876 # Number of bytes of host memory used -host_seconds 454.08 # Real time elapsed on the host -sim_insts 56540749 # Number of instructions simulated -sim_ops 56540749 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory -system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory -system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory -system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397771 # number of replacements -system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use -system.l2c.total_refs 2469954 # Total number of references to valid blocks. -system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits -system.l2c.Writeback_hits::total 806294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits -system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits -system.l2c.overall_hits::cpu0.data 822730 # number of overall hits -system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits -system.l2c.overall_hits::cpu1.data 135531 # number of overall hits -system.l2c.overall_hits::total 2042553 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses -system.l2c.demand_misses::total 434620 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses -system.l2c.overall_misses::cpu0.data 397745 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses -system.l2c.overall_misses::cpu1.data 19147 # number of overall misses -system.l2c.overall_misses::total 434620 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 707237500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20745010000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 220139500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 998215500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22670602500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 707237500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20745010000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 220139500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 998215500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22670602500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 924232 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 957077 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 177788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 121001 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2180098 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 806294 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 806294 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 824 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3932 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 286 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 324 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 610 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 263398 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 33677 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 297075 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 924232 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1220475 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 177788 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 154678 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2477173 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 924232 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1220475 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 177788 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 154678 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2477173 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency +host_inst_rate 196112 # Simulator instruction rate (inst/s) +host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6628227410 # Simulator tick rate (ticks/s) +host_mem_usage 302056 # Number of bytes of host memory used +host_seconds 286.11 # Real time elapsed on the host +sim_insts 56109524 # Number of instructions simulated +sim_ops 56109524 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory +system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147792 # 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number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11257998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11257998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559437998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570695996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8814586 # DTB read hits -system.cpu0.dtb.read_misses 32972 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 619797 # DTB read accesses -system.cpu0.dtb.write_hits 5858085 # DTB write hits -system.cpu0.dtb.write_misses 6892 # DTB write misses -system.cpu0.dtb.write_acv 315 # DTB write access violations -system.cpu0.dtb.write_accesses 207416 # DTB write accesses -system.cpu0.dtb.data_hits 14672671 # DTB hits -system.cpu0.dtb.data_misses 39864 # DTB misses -system.cpu0.dtb.data_acv 833 # DTB access violations -system.cpu0.dtb.data_accesses 827213 # DTB accesses -system.cpu0.itb.fetch_hits 1034325 # ITB hits -system.cpu0.itb.fetch_misses 27665 # ITB misses -system.cpu0.itb.fetch_acv 1025 # ITB acv -system.cpu0.itb.fetch_accesses 1061990 # ITB accesses +system.cpu0.dtb.read_hits 9453856 # DTB read hits +system.cpu0.dtb.read_misses 36184 # DTB read misses +system.cpu0.dtb.read_acv 571 # DTB read access violations +system.cpu0.dtb.read_accesses 675976 # DTB read accesses +system.cpu0.dtb.write_hits 6300368 # DTB write hits +system.cpu0.dtb.write_misses 8347 # DTB write misses +system.cpu0.dtb.write_acv 346 # DTB write access violations +system.cpu0.dtb.write_accesses 234133 # DTB write accesses +system.cpu0.dtb.data_hits 15754224 # DTB hits +system.cpu0.dtb.data_misses 44531 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 910109 # DTB accesses +system.cpu0.itb.fetch_hits 1108660 # ITB hits +system.cpu0.itb.fetch_misses 28136 # ITB misses +system.cpu0.itb.fetch_acv 1047 # ITB acv +system.cpu0.itb.fetch_accesses 1136796 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,279 +483,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 105407779 # number of cpu cycles simulated +system.cpu0.numCycles 111705884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued -system.cpu0.iq.rate 0.482387 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued +system.cpu0.iq.rate 0.489657 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3218084 # number of nop insts executed -system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7980527 # Number of branches executed -system.cpu0.iew.exec_stores 5879131 # Number of stores executed -system.cpu0.iew.exec_rate 0.477396 # Inst execution rate -system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24623982 # num instructions producing a value -system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value +system.cpu0.iew.exec_nop 3462690 # number of nop insts executed +system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8639850 # Number of branches executed +system.cpu0.iew.exec_stores 6323117 # Number of stores executed +system.cpu0.iew.exec_rate 0.485366 # Inst execution rate +system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26624302 # num instructions producing a value +system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50284711 # Number of instructions committed -system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54183968 # Number of instructions committed +system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13762834 # Number of memory references committed -system.cpu0.commit.loads 8083571 # Number of loads committed -system.cpu0.commit.membars 205088 # Number of memory barriers committed -system.cpu0.commit.branches 7564309 # Number of branches committed -system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. -system.cpu0.commit.function_calls 644133 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14789754 # Number of memory references committed +system.cpu0.commit.loads 8697139 # Number of loads committed +system.cpu0.commit.membars 219715 # Number of memory barriers committed +system.cpu0.commit.branches 8176675 # Number of branches committed +system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. +system.cpu0.commit.function_calls 709743 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126892294 # The number of ROB reads -system.cpu0.rob.rob_writes 115369853 # The number of ROB writes -system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47376653 # Number of Instructions Simulated -system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated -system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads -system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes -system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads -system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes +system.cpu0.rob.rob_reads 136054419 # The number of ROB reads +system.cpu0.rob.rob_writes 123888625 # The number of ROB writes +system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51051860 # Number of Instructions Simulated +system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated +system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads +system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes +system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads +system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 923652 # number of replacements -system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use -system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits -system.cpu0.icache.overall_hits::total 6902434 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses -system.cpu0.icache.overall_misses::total 973969 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked +system.cpu0.icache.replacements 991395 # number of replacements +system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use +system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits +system.cpu0.icache.overall_hits::total 7272203 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses +system.cpu0.icache.overall_misses::total 1045096 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 196 # number of writebacks -system.cpu0.icache.writebacks::total 196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 253 # number of writebacks +system.cpu0.icache.writebacks::total 253 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1225027 # number of replacements -system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits -system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses -system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 1352160 # number of replacements +system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits +system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses +system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks -system.cpu0.dcache.writebacks::total 689568 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks +system.cpu0.dcache.writebacks::total 805259 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1967803 # DTB read hits -system.cpu1.dtb.read_misses 13979 # DTB read misses -system.cpu1.dtb.read_acv 50 # DTB read access violations -system.cpu1.dtb.read_accesses 344857 # DTB read accesses -system.cpu1.dtb.write_hits 1156959 # DTB write hits -system.cpu1.dtb.write_misses 3426 # DTB write misses -system.cpu1.dtb.write_acv 86 # DTB write access violations -system.cpu1.dtb.write_accesses 133134 # DTB write accesses -system.cpu1.dtb.data_hits 3124762 # DTB hits -system.cpu1.dtb.data_misses 17405 # DTB misses -system.cpu1.dtb.data_acv 136 # DTB access violations -system.cpu1.dtb.data_accesses 477991 # DTB accesses -system.cpu1.itb.fetch_hits 421916 # ITB hits -system.cpu1.itb.fetch_misses 9109 # ITB misses -system.cpu1.itb.fetch_acv 356 # ITB acv -system.cpu1.itb.fetch_accesses 431025 # ITB accesses +system.cpu1.dtb.read_hits 1211336 # DTB read hits +system.cpu1.dtb.read_misses 9865 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 283619 # DTB read accesses +system.cpu1.dtb.write_hits 674221 # DTB write hits +system.cpu1.dtb.write_misses 1908 # DTB write misses +system.cpu1.dtb.write_acv 40 # DTB write access violations +system.cpu1.dtb.write_accesses 107232 # DTB write accesses +system.cpu1.dtb.data_hits 1885557 # DTB hits +system.cpu1.dtb.data_misses 11773 # DTB misses +system.cpu1.dtb.data_acv 46 # DTB access violations +system.cpu1.dtb.data_accesses 390851 # DTB accesses +system.cpu1.itb.fetch_hits 332989 # ITB hits +system.cpu1.itb.fetch_misses 6158 # ITB misses +system.cpu1.itb.fetch_acv 143 # ITB acv +system.cpu1.itb.fetch_accesses 339147 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16642884 # number of cpu cycles simulated +system.cpu1.numCycles 8872891 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued -system.cpu1.iq.rate 0.613946 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued +system.cpu1.iq.rate 0.635693 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 532071 # number of nop insts executed -system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1559516 # Number of branches executed -system.cpu1.iew.exec_stores 1165063 # Number of stores executed -system.cpu1.iew.exec_rate 0.606457 # Inst execution rate -system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4916782 # num instructions producing a value -system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value +system.cpu1.iew.exec_nop 240621 # number of nop insts executed +system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed +system.cpu1.iew.exec_branches 816845 # Number of branches executed +system.cpu1.iew.exec_stores 679274 # Number of stores executed +system.cpu1.iew.exec_rate 0.628773 # Inst execution rate +system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2655801 # num instructions producing a value +system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9615778 # Number of instructions committed -system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5260797 # Number of instructions committed +system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2823987 # Number of memory references committed -system.cpu1.commit.loads 1739300 # Number of loads committed -system.cpu1.commit.membars 35653 # Number of memory barriers committed -system.cpu1.commit.branches 1422938 # Number of branches committed -system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. -system.cpu1.commit.function_calls 153476 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1687646 # Number of memory references committed +system.cpu1.commit.loads 1056770 # Number of loads committed +system.cpu1.commit.membars 18284 # Number of memory barriers committed +system.cpu1.commit.branches 746127 # Number of branches committed +system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. +system.cpu1.commit.function_calls 83297 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25542136 # The number of ROB reads -system.cpu1.rob.rob_writes 23473924 # The number of ROB writes -system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9164096 # Number of Instructions Simulated -system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated -system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads -system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes -system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads -system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes -system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads -system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes -system.cpu1.icache.replacements 177236 # number of replacements -system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use -system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits -system.cpu1.icache.overall_hits::total 1491482 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses -system.cpu1.icache.overall_misses::total 188398 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked +system.cpu1.rob.rob_reads 14229924 # The number of ROB reads +system.cpu1.rob.rob_writes 12929135 # The number of ROB writes +system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5057664 # Number of Instructions Simulated +system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated +system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads +system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes +system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads +system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes +system.cpu1.icache.replacements 103776 # number of replacements +system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use +system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits +system.cpu1.icache.overall_hits::total 841895 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses +system.cpu1.icache.overall_misses::total 109497 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 52 # number of writebacks -system.cpu1.icache.writebacks::total 52 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 39 # number of writebacks +system.cpu1.icache.writebacks::total 39 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 5150 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 156190 # number of replacements -system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # 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number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses -system.cpu1.dcache.overall_misses::total 460887 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked +system.cpu1.dcache.replacements 49122 # number of replacements +system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits +system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses +system.cpu1.dcache.overall_misses::total 193505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1323211000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3353600320 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 16083500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7995500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4676811320 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4676811320 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4676811320 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 52059498 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks -system.cpu1.dcache.writebacks::total 116478 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks +system.cpu1.dcache.writebacks::total 27321 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1589,166 +1589,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed -system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed -system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed -system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed -system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed +system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 175342 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 186310 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1161 -system.cpu0.kern.mode_good::user 1162 +system.cpu0.kern.mode_good::kernel 1345 +system.cpu0.kern.mode_good::user 1346 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3714 # number of times the context was actually changed +system.cpu0.kern.swap_context 3894 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed -system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed -system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed -system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed -system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed -system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed +system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed -system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed -system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed -system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed -system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed -system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed +system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 42196 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 747 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 169 -system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 30107 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches +system.cpu1.kern.mode_switch::user 392 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 420 +system.cpu1.kern.mode_good::user 392 +system.cpu1.kern.mode_good::idle 28 +system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 735 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f3bacddca..3b2f5c4a1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:16:04 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858684403000 because m5_exit instruction encountered +Exiting @ tick 1858879782500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index d7b6a1ccb..90f62bf97 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,146 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858684 # Number of seconds simulated -sim_ticks 1858684403000 # Number of ticks simulated -final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.858880 # Number of seconds simulated +sim_ticks 1858879782500 # Number of ticks simulated +final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125153 # Simulator instruction rate (inst/s) -host_op_rate 125153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4381630644 # Simulator tick rate (ticks/s) -host_mem_usage 297044 # Number of bytes of host memory used -host_seconds 424.20 # Real time elapsed on the host -sim_insts 53089851 # Number of instructions simulated -sim_ops 53089851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory -system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory -system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391653 # number of replacements -system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use -system.l2c.total_refs 2427420 # Total number of references to valid blocks. -system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits -system.l2c.Writeback_hits::total 834721 # number of Writeback hits +host_inst_rate 196297 # Simulator instruction rate (inst/s) +host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6876664069 # Simulator tick rate (ticks/s) +host_mem_usage 298988 # Number of bytes of host memory used +host_seconds 270.32 # Real time elapsed on the host +sim_insts 53062487 # Number of instructions simulated +sim_ops 53062487 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338457 # number of replacements +system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use +system.l2c.total_refs 2557615 # Total number of references to valid blocks. +system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. +system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits +system.l2c.Writeback_hits::total 841169 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits -system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits -system.l2c.overall_hits::cpu.data 994510 # number of overall hits -system.l2c.overall_hits::total 2003843 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses -system.l2c.demand_misses::total 425412 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 16915 # 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number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency +system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits +system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits +system.l2c.overall_hits::cpu.data 1012304 # number of overall hits +system.l2c.overall_hits::total 2018690 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses +system.l2c.demand_misses::total 404446 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15144 # number of overall misses +system.l2c.overall_misses::cpu.data 389302 # number of overall misses +system.l2c.overall_misses::total 404446 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,80 +145,72 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117800 # number of writebacks -system.l2c.writebacks::total 117800 # number of writebacks +system.l2c.writebacks::writebacks 76064 # number of writebacks +system.l2c.writebacks::total 76064 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273879 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289022 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404445 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404445 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 606782500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10958767000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11565549500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1142000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4653345000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 606782500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15612112000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16218894500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 606782500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15612112000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16218894500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 810071000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114787998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924858998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248824 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.136188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.642857 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383575 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166910 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166910 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -231,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266745 # Cycle average of tags in use +system.iocache.tagsinuse 1.268378 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +237,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721900806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721900806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741838804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741838804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741838804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741838804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +261,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +287,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +303,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +326,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10017178 # DTB read hits -system.cpu.dtb.read_misses 45828 # DTB read misses -system.cpu.dtb.read_acv 561 # DTB read access violations -system.cpu.dtb.read_accesses 954843 # DTB read accesses -system.cpu.dtb.write_hits 6639084 # DTB write hits -system.cpu.dtb.write_misses 10800 # DTB write misses -system.cpu.dtb.write_acv 415 # DTB write access violations -system.cpu.dtb.write_accesses 340295 # DTB write accesses -system.cpu.dtb.data_hits 16656262 # DTB hits -system.cpu.dtb.data_misses 56628 # DTB misses -system.cpu.dtb.data_acv 976 # DTB access violations -system.cpu.dtb.data_accesses 1295138 # DTB accesses -system.cpu.itb.fetch_hits 1345400 # ITB hits -system.cpu.itb.fetch_misses 36691 # ITB misses -system.cpu.itb.fetch_acv 1385 # ITB acv -system.cpu.itb.fetch_accesses 1382091 # ITB accesses +system.cpu.dtb.read_hits 9957395 # DTB read hits +system.cpu.dtb.read_misses 44300 # DTB read misses +system.cpu.dtb.read_acv 564 # DTB read access violations +system.cpu.dtb.read_accesses 948872 # DTB read accesses +system.cpu.dtb.write_hits 6634412 # DTB write hits +system.cpu.dtb.write_misses 10394 # DTB write misses +system.cpu.dtb.write_acv 384 # DTB write access violations +system.cpu.dtb.write_accesses 338929 # DTB write accesses +system.cpu.dtb.data_hits 16591807 # DTB hits +system.cpu.dtb.data_misses 54694 # DTB misses +system.cpu.dtb.data_acv 948 # DTB access violations +system.cpu.dtb.data_accesses 1287801 # DTB accesses +system.cpu.itb.fetch_hits 1332166 # ITB hits +system.cpu.itb.fetch_misses 40283 # ITB misses +system.cpu.itb.fetch_acv 1114 # ITB acv +system.cpu.itb.fetch_accesses 1372449 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,147 +354,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 115937106 # number of cpu cycles simulated +system.cpu.numCycles 114963877 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits +system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued @@ -529,116 +517,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued -system.cpu.iq.rate 0.495930 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued +system.cpu.iq.rate 0.497364 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3587167 # number of nop insts executed -system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed -system.cpu.iew.exec_branches 9006504 # Number of branches executed -system.cpu.iew.exec_stores 6665235 # Number of stores executed -system.cpu.iew.exec_rate 0.490534 # Inst execution rate -system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27888094 # num instructions producing a value -system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value +system.cpu.iew.exec_nop 3561304 # number of nop insts executed +system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed +system.cpu.iew.exec_branches 8986521 # Number of branches executed +system.cpu.iew.exec_stores 6660022 # Number of stores executed +system.cpu.iew.exec_rate 0.492808 # Inst execution rate +system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27828941 # num instructions producing a value +system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back +system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56284358 # Number of instructions committed -system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56255888 # Number of instructions committed +system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15505080 # Number of memory references committed -system.cpu.commit.loads 9112848 # Number of loads committed -system.cpu.commit.membars 227858 # Number of memory barriers committed -system.cpu.commit.branches 8462387 # Number of branches committed +system.cpu.commit.refs 15498262 # Number of memory references committed +system.cpu.commit.loads 9108436 # Number of loads committed +system.cpu.commit.membars 227920 # Number of memory barriers committed +system.cpu.commit.branches 8459857 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. -system.cpu.commit.function_calls 744427 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. +system.cpu.commit.function_calls 744157 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142888950 # The number of ROB reads -system.cpu.rob.rob_writes 130907900 # The number of ROB writes -system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53089851 # Number of Instructions Simulated -system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated -system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74514493 # number of integer regfile reads -system.cpu.int_regfile_writes 40703979 # number of integer regfile writes -system.cpu.fp_regfile_reads 166152 # number of floating regfile reads -system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads -system.cpu.misc_regfile_writes 949957 # number of misc regfile writes +system.cpu.rob.rob_reads 141652037 # The number of ROB reads +system.cpu.rob.rob_writes 129738562 # The number of ROB writes +system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53062487 # Number of Instructions Simulated +system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated +system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads +system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74266984 # number of integer regfile reads +system.cpu.int_regfile_writes 40553865 # number of integer regfile writes +system.cpu.fp_regfile_reads 166054 # number of floating regfile reads +system.cpu.fp_regfile_writes 167450 # number of floating regfile writes +system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads +system.cpu.misc_regfile_writes 950331 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -670,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1025621 # number of replacements -system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use -system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits -system.cpu.icache.overall_hits::total 7915590 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked +system.cpu.icache.replacements 1020915 # number of replacements +system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use +system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits +system.cpu.icache.overall_hits::total 7681838 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses +system.cpu.icache.overall_misses::total 1079605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 238 # number of writebacks -system.cpu.icache.writebacks::total 238 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 236 # number of writebacks +system.cpu.icache.writebacks::total 236 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57973 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57973 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57973 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57973 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57973 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021632 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1021632 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1021632 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402627 # number of replacements -system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use -system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1401226 # number of replacements +system.cpu.dcache.tagsinuse 511.995976 # Cycle average of tags in use +system.cpu.dcache.total_refs 11915698 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401738 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.500660 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19319000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995976 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits -system.cpu.dcache.overall_hits::total 11537532 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses -system.cpu.dcache.overall_misses::total 3747076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25559.559314 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 805076325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99334 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834483 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks +system.cpu.dcache.writebacks::total 840933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # 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number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32542701825 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32542701825 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904540000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234101998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138641998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -919,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -979,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192407 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 192549 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 5d60c7bc8..ea1e9a4d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index e36bf2017..570320fa8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,17 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8 -warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013 +warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented +warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 086d512f2..494cdd6ff 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:58:44 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:32:52 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2501685689500 because m5_exit instruction encountered +Exiting @ tick 2500827052500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e9f646cad..655a3d26b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.501686 # Number of seconds simulated -sim_ticks 2501685689500 # Number of ticks simulated -final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.500827 # Number of seconds simulated +sim_ticks 2500827052500 # Number of ticks simulated +final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49441 # Simulator instruction rate (inst/s) -host_op_rate 63837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075989543 # Simulator tick rate (ticks/s) -host_mem_usage 387400 # Number of bytes of host memory used -host_seconds 1205.06 # Real time elapsed on the host -sim_insts 59579009 # Number of instructions simulated -sim_ops 76926775 # Number of ops (including micro ops) simulated +host_inst_rate 76093 # Simulator instruction rate (inst/s) +host_op_rate 98249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3194009596 # Simulator tick rate (ticks/s) +host_mem_usage 386968 # Number of bytes of host memory used +host_seconds 782.97 # Real time elapsed on the host +sim_insts 59579144 # Number of instructions simulated +sim_ops 76926734 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +23,191 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory -system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory +system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119797 # number of replacements -system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use -system.l2c.total_refs 1834134 # Total number of references to valid blocks. -system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1536133 # 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number of overall hits -system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits -system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits -system.l2c.overall_hits::cpu.data 484171 # number of overall hits -system.l2c.overall_hits::total 1642008 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1331 # 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Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64425 # number of replacements +system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use +system.l2c.total_refs 2029411 # Total number of references to valid blocks. +system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # 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number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits +system.l2c.overall_hits::cpu.inst 977061 # number of overall hits +system.l2c.overall_hits::cpu.data 497363 # number of overall hits +system.l2c.overall_hits::total 1608896 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140292 # 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mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -339,26 +336,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048343 # DTB read hits -system.cpu.checker.dtb.read_misses 7305 # DTB read misses -system.cpu.checker.dtb.write_hits 11293933 # DTB write hits +system.cpu.checker.dtb.read_hits 15048239 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11293838 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15055547 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296029 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26342276 # DTB hits -system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26351772 # DTB accesses -system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits +system.cpu.checker.dtb.hits 26342077 # DTB hits +system.cpu.checker.dtb.misses 9499 # DTB misses +system.cpu.checker.dtb.accesses 26351576 # DTB accesses +system.cpu.checker.itb.inst_hits 60745761 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -375,36 +372,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses -system.cpu.checker.itb.hits 60745631 # DTB hits +system.cpu.checker.itb.inst_accesses 60750232 # ITB inst accesses +system.cpu.checker.itb.hits 60745761 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60750102 # DTB accesses -system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60750232 # DTB accesses +system.cpu.checker.numCycles 77205158 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52103903 # DTB read hits -system.cpu.dtb.read_misses 93079 # DTB read misses -system.cpu.dtb.write_hits 11946241 # DTB write hits -system.cpu.dtb.write_misses 25022 # DTB write misses +system.cpu.dtb.read_hits 51785537 # DTB read hits +system.cpu.dtb.read_misses 81591 # DTB read misses +system.cpu.dtb.write_hits 11872923 # DTB write hits +system.cpu.dtb.write_misses 18231 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52196982 # DTB read accesses -system.cpu.dtb.write_accesses 11971263 # DTB write accesses +system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51867128 # DTB read accesses +system.cpu.dtb.write_accesses 11891154 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64050144 # DTB hits -system.cpu.dtb.misses 118101 # DTB misses -system.cpu.dtb.accesses 64168245 # DTB accesses -system.cpu.itb.inst_hits 13717584 # ITB inst hits -system.cpu.itb.inst_misses 12272 # ITB inst misses +system.cpu.dtb.hits 63658460 # DTB hits +system.cpu.dtb.misses 99822 # DTB misses +system.cpu.dtb.accesses 63758282 # DTB accesses +system.cpu.itb.inst_hits 13022422 # ITB inst hits +system.cpu.itb.inst_misses 12153 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -413,542 +410,542 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5249 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13729856 # ITB inst accesses -system.cpu.itb.hits 13717584 # DTB hits -system.cpu.itb.misses 12272 # DTB misses -system.cpu.itb.accesses 13729856 # DTB accesses -system.cpu.numCycles 411352060 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13034575 # ITB inst accesses +system.cpu.itb.hits 13022422 # DTB hits +system.cpu.itb.misses 12153 # DTB misses +system.cpu.itb.accesses 13034575 # DTB accesses +system.cpu.numCycles 408047924 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits +system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued -system.cpu.iq.rate 0.307159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued +system.cpu.iq.rate 0.305615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 261908 # number of nop insts executed -system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed -system.cpu.iew.exec_branches 11601340 # Number of branches executed -system.cpu.iew.exec_stores 12455688 # Number of stores executed -system.cpu.iew.exec_rate 0.299278 # Inst execution rate -system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47546734 # num instructions producing a value -system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value +system.cpu.iew.exec_nop 254480 # number of nop insts executed +system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed +system.cpu.iew.exec_branches 11392260 # Number of branches executed +system.cpu.iew.exec_stores 12383469 # Number of stores executed +system.cpu.iew.exec_rate 0.298278 # Inst execution rate +system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46962413 # num instructions producing a value +system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729390 # Number of instructions committed -system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59729525 # Number of instructions committed +system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513639 # Number of memory references committed -system.cpu.commit.loads 15715354 # Number of loads committed -system.cpu.commit.membars 413068 # Number of memory barriers committed -system.cpu.commit.branches 9904424 # Number of branches committed +system.cpu.commit.refs 27513492 # Number of memory references committed +system.cpu.commit.loads 15715290 # Number of loads committed +system.cpu.commit.membars 413064 # Number of memory barriers committed +system.cpu.commit.branches 9904425 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617835 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. +system.cpu.commit.function_calls 995959 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 245922084 # The number of ROB reads -system.cpu.rob.rob_writes 212744706 # The number of ROB writes -system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579009 # Number of Instructions Simulated -system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated -system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558200785 # number of integer regfile reads -system.cpu.int_regfile_writes 89400907 # number of integer regfile writes -system.cpu.fp_regfile_reads 8900 # number of floating regfile reads -system.cpu.fp_regfile_writes 2982 # number of floating regfile writes -system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads -system.cpu.misc_regfile_writes 912729 # number of misc regfile writes -system.cpu.icache.replacements 1019271 # number of replacements -system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use -system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits -system.cpu.icache.overall_hits::total 12598089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses -system.cpu.icache.overall_misses::total 1111711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked +system.cpu.rob.rob_reads 240802540 # The number of ROB reads +system.cpu.rob.rob_writes 206662154 # The number of ROB writes +system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59579144 # Number of Instructions Simulated +system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated +system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 552215112 # number of integer regfile reads +system.cpu.int_regfile_writes 88113132 # number of integer regfile writes +system.cpu.fp_regfile_reads 8314 # number of floating regfile reads +system.cpu.fp_regfile_writes 2878 # number of floating regfile writes +system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads +system.cpu.misc_regfile_writes 912736 # number of misc regfile writes +system.cpu.icache.replacements 990445 # number of replacements +system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use +system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits +system.cpu.icache.overall_hits::total 11943122 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses +system.cpu.icache.overall_misses::total 1075156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 60091 # number of writebacks -system.cpu.icache.writebacks::total 60091 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67776 # number of writebacks +system.cpu.icache.writebacks::total 67776 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84152 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits -system.cpu.dcache.overall_hits::total 21500114 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses -system.cpu.dcache.overall_misses::total 3714520 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits +system.cpu.dcache.overall_hits::total 21203803 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses +system.cpu.dcache.overall_misses::total 3698116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks -system.cpu.dcache.writebacks::total 574932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks +system.cpu.dcache.writebacks::total 608100 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -970,16 +967,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index aff8253f7..8259e7988 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..c3484784a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,9 +10,11 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index c0177ee1d..02c5cc88a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:58:50 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:33:16 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2570833934500 because m5_exit instruction encountered +Exiting @ tick 2569716290500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6e759f59e..038e4aa5b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.570834 # Number of seconds simulated -sim_ticks 2570833934500 # Number of ticks simulated -final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.569716 # Number of seconds simulated +sim_ticks 2569716290500 # Number of ticks simulated +final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53678 # Simulator instruction rate (inst/s) -host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2225327298 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 1155.26 # Real time elapsed on the host -sim_insts 62012062 # Number of instructions simulated -sim_ops 80088895 # Number of ops (including micro ops) simulated +host_inst_rate 91215 # Simulator instruction rate (inst/s) +host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3779331614 # Simulator tick rate (ticks/s) +host_mem_usage 391064 # Number of bytes of host memory used +host_seconds 679.94 # Real time elapsed on the host +sim_insts 62020337 # Number of instructions simulated +sim_ops 80105642 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory +system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -80,259 +80,259 @@ system.realview.nvmem.num_reads::cpu0.inst 1 # system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130926 # number of replacements -system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use -system.l2c.total_refs 1855308 # Total number of references to valid blocks. -system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. +system.l2c.replacements 72902 # number of replacements +system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use +system.l2c.total_refs 2024041 # Total number of references to valid blocks. +system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.006762 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2177.920948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1032.752170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 22.717912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.014158 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4068.026765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5070.431306 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231738 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000269 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.033232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.015759 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000347 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.062073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.077369 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420786 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 51294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 335682 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 133493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 112013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 702787 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 231603 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1579905 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606768 # number of Writeback hits -system.l2c.Writeback_hits::total 606768 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 925 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2064 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 217 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 388 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 605 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 35350 # 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number of ReadReq misses -system.l2c.ReadReq_misses::total 40353 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5201 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11020 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 788 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 600 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1388 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65908 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 81633 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 84 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8376 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74713 # 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number of overall misses -system.l2c.overall_misses::total 187894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4383500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 438009000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 459487500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3183500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 533470500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 669975500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2108822500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 18089500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 38874000 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7530160 # DTB read hits -system.cpu0.dtb.read_misses 32787 # DTB read misses -system.cpu0.dtb.write_hits 4446652 # DTB write hits -system.cpu0.dtb.write_misses 6213 # DTB write misses +system.cpu0.dtb.read_hits 12222008 # DTB read hits +system.cpu0.dtb.read_misses 34799 # DTB read misses +system.cpu0.dtb.write_hits 5155654 # DTB write hits +system.cpu0.dtb.write_misses 4970 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2035 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4401 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 226 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7562947 # DTB read accesses -system.cpu0.dtb.write_accesses 4452865 # DTB write accesses +system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12256807 # DTB read accesses +system.cpu0.dtb.write_accesses 5160624 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11976812 # DTB hits -system.cpu0.dtb.misses 39000 # DTB misses -system.cpu0.dtb.accesses 12015812 # DTB accesses -system.cpu0.itb.inst_hits 3834120 # ITB inst hits -system.cpu0.itb.inst_misses 4594 # ITB inst misses +system.cpu0.dtb.hits 17377662 # DTB hits +system.cpu0.dtb.misses 39769 # DTB misses +system.cpu0.dtb.accesses 17417431 # DTB accesses +system.cpu0.itb.inst_hits 4312814 # ITB inst hits +system.cpu0.itb.inst_misses 5659 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,542 +566,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1800 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 3838714 # ITB inst accesses -system.cpu0.itb.hits 3834120 # DTB hits -system.cpu0.itb.misses 4594 # DTB misses -system.cpu0.itb.accesses 3838714 # DTB accesses -system.cpu0.numCycles 55537360 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses +system.cpu0.itb.hits 4312814 # DTB hits +system.cpu0.itb.misses 5659 # DTB misses +system.cpu0.itb.accesses 4318473 # DTB accesses +system.cpu0.numCycles 91755333 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5204671 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 3944570 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 296840 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3413720 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2557176 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 459948 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 62294 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 10542481 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 27454720 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5204671 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3017124 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6462624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1388283 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64249 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 17511747 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6585 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 32170 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 74952 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 3831976 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 163321 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.003010 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.394306 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 29226357 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 522599 1.46% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 706764 1.98% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 578503 1.62% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 534782 1.50% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 477839 1.34% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 574033 1.61% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 347894 0.97% 92.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2713823 7.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093715 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.494347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 10901751 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17564449 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 5807943 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 476099 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 932352 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 836954 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 56324 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34505102 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 181228 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 932352 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11416627 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4596309 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11321409 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 5748941 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1666956 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33335658 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 999 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 358087 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 883877 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 110 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 33439844 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 151572898 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 151532196 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 25794881 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7644963 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 390853 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 354451 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4284069 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6465672 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4994701 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 841470 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 890235 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 31482040 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 658671 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 31606585 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 78774 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5676384 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13082280 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 117406 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 35682594 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.885770 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514582 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 22866556 64.08% 64.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4972769 13.94% 78.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2602679 7.29% 85.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 1960706 5.49% 90.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1807368 5.07% 95.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 768762 2.15% 98.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 499053 1.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 158868 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 45833 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 35682594 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26479 2.83% 2.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.05% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 724595 77.49% 80.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 183504 19.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 18849345 59.64% 59.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42325 0.13% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7946092 25.14% 84.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4753870 15.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 31606585 # Type of FU issued -system.cpu0.iq.rate 0.569105 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 935032 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029583 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 99937037 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 37821084 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 28987180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10596 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5532 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4395 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 32521589 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5747 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 248744 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued +system.cpu0.iq.rate 0.437871 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1245744 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3732 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10021 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 530307 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1901421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5034 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 932352 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3503280 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 78441 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 32200235 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 121893 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6465672 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4994701 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 398658 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37609 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4704 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10021 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 177778 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116282 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 294060 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 31219910 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7794602 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386675 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 59524 # number of nop insts executed -system.cpu0.iew.exec_refs 12495671 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4074655 # Number of branches executed -system.cpu0.iew.exec_stores 4701069 # Number of stores executed -system.cpu0.iew.exec_rate 0.562142 # Inst execution rate -system.cpu0.iew.wb_sent 31018630 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 28991575 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15563441 # num instructions producing a value -system.cpu0.iew.wb_consumers 30561631 # num instructions consuming a value +system.cpu0.iew.exec_nop 116326 # number of nop insts executed +system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4780864 # Number of branches executed +system.cpu0.iew.exec_stores 5426948 # Number of stores executed +system.cpu0.iew.exec_rate 0.433525 # Inst execution rate +system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18213937 # num instructions producing a value +system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.522019 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.509248 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 19778635 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 26259365 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5789320 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541265 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 257580 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 34779040 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.755034 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.721723 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 24914736 71.64% 71.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 4928764 14.17% 85.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1604217 4.61% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 793137 2.28% 92.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 618967 1.78% 94.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 369015 1.06% 95.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397376 1.14% 96.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 185067 0.53% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 967761 2.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 34779040 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 19778635 # Number of instructions committed -system.cpu0.commit.committedOps 26259365 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23601687 # Number of instructions committed +system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 9684322 # Number of memory references committed -system.cpu0.commit.loads 5219928 # Number of loads committed -system.cpu0.commit.membars 194188 # Number of memory barriers committed -system.cpu0.commit.branches 3591028 # Number of branches committed -system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 23338580 # Number of committed integer instructions. -system.cpu0.commit.function_calls 422336 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 967761 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11516347 # Number of memory references committed +system.cpu0.commit.loads 6366744 # Number of loads committed +system.cpu0.commit.membars 228774 # Number of memory barriers committed +system.cpu0.commit.branches 4268909 # Number of branches committed +system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 492618 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 65245448 # The number of ROB reads -system.cpu0.rob.rob_writes 65031517 # The number of ROB writes -system.cpu0.timesIdled 363170 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 19854766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085481268 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 19754081 # Number of Instructions Simulated -system.cpu0.committedOps 26234811 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 19754081 # Number of Instructions Simulated -system.cpu0.cpi 2.811437 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.811437 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.355690 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.355690 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 145547438 # number of integer regfile reads -system.cpu0.int_regfile_writes 28450023 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4554 # number of floating regfile reads -system.cpu0.fp_regfile_writes 434 # number of floating regfile writes -system.cpu0.misc_regfile_reads 38991088 # number of misc regfile reads -system.cpu0.misc_regfile_writes 443778 # number of misc regfile writes -system.cpu0.icache.replacements 345092 # number of replacements -system.cpu0.icache.tagsinuse 511.631515 # Cycle average of tags in use -system.cpu0.icache.total_refs 3456613 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 345604 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.001658 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6336390000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.631515 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3456613 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3456613 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3456613 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3456613 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3456613 # number of overall hits -system.cpu0.icache.overall_hits::total 3456613 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 375216 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 375216 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 375216 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 375216 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 375216 # number of overall misses -system.cpu0.icache.overall_misses::total 375216 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5700257984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked +system.cpu0.rob.rob_reads 80832744 # The number of ROB reads +system.cpu0.rob.rob_writes 75665562 # The number of ROB writes +system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23536584 # Number of Instructions Simulated +system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated +system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads +system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads +system.cpu0.fp_regfile_writes 934 # number of floating regfile writes +system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads +system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes +system.cpu0.icache.replacements 402234 # number of replacements +system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use +system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits +system.cpu0.icache.overall_hits::total 3875529 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses +system.cpu0.icache.overall_misses::total 435289 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 19422 # number of writebacks -system.cpu0.icache.writebacks::total 19422 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29600 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 29600 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 29600 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 29600 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 345616 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 345616 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 345616 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 345616 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks +system.cpu0.icache.writebacks::total 31582 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 232498 # number of replacements -system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use -system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4805960 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4805960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2599019 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2599019 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154744 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 154744 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152410 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 152410 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7404979 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7404979 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7404979 # number of overall hits -system.cpu0.dcache.overall_hits::total 7404979 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 332693 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 332693 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1446995 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1446995 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8853 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8853 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7938 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7938 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1779688 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1779688 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1779688 # number of overall misses -system.cpu0.dcache.overall_misses::total 1779688 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 64309791899 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 64309791899 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 272390 # number of replacements +system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits +system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses +system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 208397 # number of writebacks -system.cpu0.dcache.writebacks::total 208397 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1502667 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1502667 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 277021 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277021 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks +system.cpu0.dcache.writebacks::total 253456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1111,27 +1111,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 45335988 # DTB read hits -system.cpu1.dtb.read_misses 67766 # DTB read misses -system.cpu1.dtb.write_hits 7974825 # DTB write hits -system.cpu1.dtb.write_misses 20571 # DTB write misses +system.cpu1.dtb.read_hits 40314372 # DTB read hits +system.cpu1.dtb.read_misses 47835 # DTB read misses +system.cpu1.dtb.write_hits 7207214 # DTB write hits +system.cpu1.dtb.write_misses 14308 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2707 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7654 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 597 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1825 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45403754 # DTB read accesses -system.cpu1.dtb.write_accesses 7995396 # DTB write accesses +system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 40362207 # DTB read accesses +system.cpu1.dtb.write_accesses 7221522 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 53310813 # DTB hits -system.cpu1.dtb.misses 88337 # DTB misses -system.cpu1.dtb.accesses 53399150 # DTB accesses -system.cpu1.itb.inst_hits 10447082 # ITB inst hits -system.cpu1.itb.inst_misses 7775 # ITB inst misses +system.cpu1.dtb.hits 47521586 # DTB hits +system.cpu1.dtb.misses 62143 # DTB misses +system.cpu1.dtb.accesses 47583729 # DTB accesses +system.cpu1.itb.inst_hits 9199147 # ITB inst hits +system.cpu1.itb.inst_misses 6537 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1140,546 +1140,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1562 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 5028 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10454857 # ITB inst accesses -system.cpu1.itb.hits 10447082 # DTB hits -system.cpu1.itb.misses 7775 # DTB misses -system.cpu1.itb.accesses 10454857 # DTB accesses -system.cpu1.numCycles 361402922 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses +system.cpu1.itb.hits 9199147 # DTB hits +system.cpu1.itb.misses 6537 # DTB misses +system.cpu1.itb.accesses 9205684 # DTB accesses +system.cpu1.numCycles 321589455 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 11186826 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8978228 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 659649 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7702930 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6115228 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 914050 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 143881 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 24238168 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 79362685 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 11186826 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7029278 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 17037334 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5514806 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 104106 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 74528918 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 113982 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 165536 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10441784 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 854309 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4213 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.807329 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.185858 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102950411 85.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 1027065 0.86% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1252290 1.04% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2222542 1.85% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1450508 1.21% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 763655 0.64% 91.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2450140 2.04% 93.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 546027 0.46% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7314832 6.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030954 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.219596 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25932861 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 74439661 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15341871 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 600655 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3662422 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1558576 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 123600 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90136794 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 402223 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3662422 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 27545183 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32824542 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 37049772 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14316379 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4579172 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 83629464 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2956 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 679775 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3317472 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46248 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 88354418 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 386338466 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 386288470 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 49996 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 54988347 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 33366070 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 602019 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 524737 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8626692 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 16066963 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9656417 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1282659 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1811239 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 75062782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1031692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 98462898 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 155624 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 21632122 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 61142717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 223849 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 119977470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.820678 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.544702 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 85994383 71.68% 71.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9640016 8.03% 79.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5133014 4.28% 83.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4263453 3.55% 87.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11149849 9.29% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2119505 1.77% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1269612 1.06% 99.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 309202 0.26% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 98436 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 119977470 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 44202 0.54% 0.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 979 0.01% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7732056 95.26% 95.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 339451 4.18% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 43271411 43.95% 44.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 69911 0.07% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 29 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 39 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1782 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46626317 47.35% 91.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8400570 8.53% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 98462898 # Type of FU issued -system.cpu1.iq.rate 0.272446 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8116688 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.082434 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 325251459 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 97743765 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 61686980 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12182 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6832 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5554 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 106480420 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6347 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 431690 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued +system.cpu1.iq.rate 0.274443 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4883583 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7497 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24780 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1835710 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32214526 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149867 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3662422 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25277331 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367624 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 76304263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 229674 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 16066963 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9656417 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 636963 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63488 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8504 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24780 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 400468 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 244624 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 645092 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 95561838 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45782046 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2901060 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 209789 # number of nop insts executed -system.cpu1.iew.exec_refs 54078244 # number of memory reference insts executed -system.cpu1.iew.exec_branches 8068913 # Number of branches executed -system.cpu1.iew.exec_stores 8296198 # Number of stores executed -system.cpu1.iew.exec_rate 0.264419 # Inst execution rate -system.cpu1.iew.wb_sent 94191755 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 61692534 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 33977338 # num instructions producing a value -system.cpu1.iew.wb_consumers 61891561 # num instructions consuming a value +system.cpu1.iew.exec_nop 145081 # number of nop insts executed +system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7143156 # Number of branches executed +system.cpu1.iew.exec_stores 7512980 # Number of stores executed +system.cpu1.iew.exec_rate 0.266206 # Inst execution rate +system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30755357 # num instructions producing a value +system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.170703 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.548982 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 42383808 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 53979911 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 22261112 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 807843 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 569017 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 116371049 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.463860 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.434767 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97273421 83.59% 83.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9394437 8.07% 91.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2575050 2.21% 93.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1580988 1.36% 95.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1207821 1.04% 96.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 698590 0.60% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1120414 0.96% 97.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 516932 0.44% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 2003396 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 116371049 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 42383808 # Number of instructions committed -system.cpu1.commit.committedOps 53979911 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38569031 # Number of instructions committed +system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 19004087 # Number of memory references committed -system.cpu1.commit.loads 11183380 # Number of loads committed -system.cpu1.commit.membars 242516 # Number of memory barriers committed -system.cpu1.commit.branches 6784179 # Number of branches committed -system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 48067133 # Number of committed integer instructions. -system.cpu1.commit.function_calls 633379 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 2003396 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17180057 # Number of memory references committed +system.cpu1.commit.loads 10040109 # Number of loads committed +system.cpu1.commit.membars 207982 # Number of memory barriers committed +system.cpu1.commit.branches 6108113 # Number of branches committed +system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. +system.cpu1.commit.function_calls 563417 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 189385035 # The number of ROB reads -system.cpu1.rob.rob_writes 156267900 # The number of ROB writes -system.cpu1.timesIdled 1564769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 241425452 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4780203327 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 42257981 # Number of Instructions Simulated -system.cpu1.committedOps 53854084 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 42257981 # Number of Instructions Simulated -system.cpu1.cpi 8.552300 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.552300 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.116928 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.116928 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 430079753 # number of integer regfile reads -system.cpu1.int_regfile_writes 64515100 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4419 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2066 # number of floating regfile writes -system.cpu1.misc_regfile_reads 102262967 # number of misc regfile reads -system.cpu1.misc_regfile_writes 513108 # number of misc regfile writes -system.cpu1.icache.replacements 714529 # number of replacements -system.cpu1.icache.tagsinuse 498.761723 # Cycle average of tags in use -system.cpu1.icache.total_refs 9665211 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 715041 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.517003 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74296656000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.761723 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9665211 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9665211 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9665211 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9665211 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9665211 # number of overall hits -system.cpu1.icache.overall_hits::total 9665211 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 776521 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 776521 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 776521 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 776521 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 776521 # number of overall misses -system.cpu1.icache.overall_misses::total 776521 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11390030990 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked +system.cpu1.rob.rob_reads 168322862 # The number of ROB reads +system.cpu1.rob.rob_writes 139443210 # The number of ROB writes +system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38483753 # Number of Instructions Simulated +system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated +system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads +system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads +system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes +system.cpu1.icache.replacements 628575 # number of replacements +system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use +system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits +system.cpu1.icache.overall_hits::total 8518604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses +system.cpu1.icache.overall_misses::total 678443 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9197047 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 32858 # 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Cycle average of tags in use +system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 346093 # number of writebacks -system.cpu1.dcache.writebacks::total 346093 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1751452 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1751452 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 447928 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 447928 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5551338067 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5551338067 # 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks +system.cpu1.dcache.writebacks::total 330007 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1701,18 +1697,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 911c40f55..027fdffc2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 9a28ceb37..ab2c07a7f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c37c93eb0..9c5baf3db 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:55:16 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:31:55 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2501685689500 because m5_exit instruction encountered +Exiting @ tick 2500827052500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 93f3afbea..2b0eb45e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.501686 # Number of seconds simulated -sim_ticks 2501685689500 # Number of ticks simulated -final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.500827 # Number of seconds simulated +sim_ticks 2500827052500 # Number of ticks simulated +final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57858 # Simulator instruction rate (inst/s) -host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2429415836 # Simulator tick rate (ticks/s) -host_mem_usage 387132 # Number of bytes of host memory used -host_seconds 1029.75 # Real time elapsed on the host -sim_insts 59579009 # Number of instructions simulated -sim_ops 76926775 # Number of ops (including micro ops) simulated +host_inst_rate 90125 # Simulator instruction rate (inst/s) +host_op_rate 116367 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3783000939 # Simulator tick rate (ticks/s) +host_mem_usage 386964 # Number of bytes of host memory used +host_seconds 661.07 # Real time elapsed on the host +sim_insts 59579144 # Number of instructions simulated +sim_ops 76926734 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +23,191 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory -system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory +system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119797 # number of replacements -system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use -system.l2c.total_refs 1834134 # Total number of references to valid blocks. -system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits -system.l2c.Writeback_hits::total 635023 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits -system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits -system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits -system.l2c.overall_hits::cpu.data 484171 # number of overall hits -system.l2c.overall_hits::total 1642008 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses +system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64425 # number of replacements +system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use +system.l2c.total_refs 2029411 # Total number of references to valid blocks. +system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits +system.l2c.Writeback_hits::total 675876 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits +system.l2c.overall_hits::cpu.inst 977061 # number of overall hits +system.l2c.overall_hits::cpu.data 497363 # number of overall hits +system.l2c.overall_hits::total 1608896 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses -system.l2c.demand_misses::total 177053 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu.inst 17378 # number of overall misses -system.l2c.overall_misses::cpu.data 159472 # number of overall misses -system.l2c.overall_misses::total 177053 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # 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number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7093247500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -339,27 +336,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52103903 # DTB read hits -system.cpu.dtb.read_misses 93079 # DTB read misses -system.cpu.dtb.write_hits 11946241 # DTB write hits -system.cpu.dtb.write_misses 25022 # DTB write misses +system.cpu.dtb.read_hits 51785537 # DTB read hits +system.cpu.dtb.read_misses 81591 # DTB read misses +system.cpu.dtb.write_hits 11872923 # DTB write hits +system.cpu.dtb.write_misses 18231 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4506 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52196982 # DTB read accesses -system.cpu.dtb.write_accesses 11971263 # DTB write accesses +system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51867128 # DTB read accesses +system.cpu.dtb.write_accesses 11891154 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64050144 # DTB hits -system.cpu.dtb.misses 118101 # DTB misses -system.cpu.dtb.accesses 64168245 # DTB accesses -system.cpu.itb.inst_hits 13717584 # ITB inst hits -system.cpu.itb.inst_misses 12272 # ITB inst misses +system.cpu.dtb.hits 63658460 # DTB hits +system.cpu.dtb.misses 99822 # DTB misses +system.cpu.dtb.accesses 63758282 # DTB accesses +system.cpu.itb.inst_hits 13022422 # ITB inst hits +system.cpu.itb.inst_misses 12153 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -368,542 +365,542 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2627 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13729856 # ITB inst accesses -system.cpu.itb.hits 13717584 # DTB hits -system.cpu.itb.misses 12272 # DTB misses -system.cpu.itb.accesses 13729856 # DTB accesses -system.cpu.numCycles 411352060 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13034575 # ITB inst accesses +system.cpu.itb.hits 13022422 # DTB hits +system.cpu.itb.misses 12153 # DTB misses +system.cpu.itb.accesses 13034575 # DTB accesses +system.cpu.numCycles 408047924 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits +system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued -system.cpu.iq.rate 0.307159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued +system.cpu.iq.rate 0.305615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 261908 # number of nop insts executed -system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed -system.cpu.iew.exec_branches 11601340 # Number of branches executed -system.cpu.iew.exec_stores 12455688 # Number of stores executed -system.cpu.iew.exec_rate 0.299278 # Inst execution rate -system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47546734 # num instructions producing a value -system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value +system.cpu.iew.exec_nop 254480 # number of nop insts executed +system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed +system.cpu.iew.exec_branches 11392260 # Number of branches executed +system.cpu.iew.exec_stores 12383469 # Number of stores executed +system.cpu.iew.exec_rate 0.298278 # Inst execution rate +system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46962413 # num instructions producing a value +system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729390 # Number of instructions committed -system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59729525 # Number of instructions committed +system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513639 # Number of memory references committed -system.cpu.commit.loads 15715354 # Number of loads committed -system.cpu.commit.membars 413068 # Number of memory barriers committed -system.cpu.commit.branches 9904424 # Number of branches committed +system.cpu.commit.refs 27513492 # Number of memory references committed +system.cpu.commit.loads 15715290 # Number of loads committed +system.cpu.commit.membars 413064 # Number of memory barriers committed +system.cpu.commit.branches 9904425 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617835 # Number of committed integer instructions. -system.cpu.commit.function_calls 995976 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. +system.cpu.commit.function_calls 995959 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 245922084 # The number of ROB reads -system.cpu.rob.rob_writes 212744706 # The number of ROB writes -system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579009 # Number of Instructions Simulated -system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated -system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558200782 # number of integer regfile reads -system.cpu.int_regfile_writes 89400906 # number of integer regfile writes -system.cpu.fp_regfile_reads 8900 # number of floating regfile reads -system.cpu.fp_regfile_writes 2982 # number of floating regfile writes -system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads -system.cpu.misc_regfile_writes 912729 # number of misc regfile writes -system.cpu.icache.replacements 1019271 # number of replacements -system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use -system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits -system.cpu.icache.overall_hits::total 12598089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses -system.cpu.icache.overall_misses::total 1111711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked +system.cpu.rob.rob_reads 240802540 # The number of ROB reads +system.cpu.rob.rob_writes 206662154 # The number of ROB writes +system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59579144 # Number of Instructions Simulated +system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated +system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 552215109 # number of integer regfile reads +system.cpu.int_regfile_writes 88113131 # number of integer regfile writes +system.cpu.fp_regfile_reads 8314 # number of floating regfile reads +system.cpu.fp_regfile_writes 2878 # number of floating regfile writes +system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads +system.cpu.misc_regfile_writes 912736 # number of misc regfile writes +system.cpu.icache.replacements 990445 # number of replacements +system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use +system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999248 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks -system.cpu.dcache.writebacks::total 574932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # 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number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks +system.cpu.dcache.writebacks::total 608100 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -925,16 +922,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index a9da64c54..fefd6bd25 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 17:03:49 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:25:59 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5157514159500 because m5_exit instruction encountered +Exiting @ tick 5147413032500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index bfc607b4f..674b1d778 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.157514 # Number of seconds simulated -sim_ticks 5157514159500 # Number of ticks simulated -final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.147413 # Number of seconds simulated +sim_ticks 5147413032500 # Number of ticks simulated +final_tick 5147413032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123762 # Simulator instruction rate (inst/s) -host_op_rate 243888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1496586873 # Simulator tick rate (ticks/s) -host_mem_usage 369148 # Number of bytes of host memory used -host_seconds 3446.18 # Real time elapsed on the host -sim_insts 426506235 # Number of instructions simulated -sim_ops 840483958 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory -system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory -system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory -system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 167142 # number of replacements -system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use -system.l2c.total_refs 3843284 # Total number of references to valid blocks. -system.l2c.sampled_refs 202399 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.988651 # Average number of references to valid blocks. +host_inst_rate 192321 # Simulator instruction rate (inst/s) +host_op_rate 378987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2320932369 # Simulator tick rate (ticks/s) +host_mem_usage 367552 # Number of bytes of host memory used +host_seconds 2217.82 # Real time elapsed on the host +sim_insts 426532736 # Number of instructions simulated +sim_ops 840526050 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2503168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1073280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10624512 # Number of bytes read from this memory +system.physmem.bytes_read::total 14204736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1073280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1073280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9409088 # Number of bytes written to this memory +system.physmem.bytes_written::total 9409088 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 221949 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 147017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 147017 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 208509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2064049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2759587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1827926 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1827926 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1827926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2064049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4587513 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 110659 # number of replacements +system.l2c.tagsinuse 64846.009272 # Cycle average of tags in use +system.l2c.total_refs 3990913 # Total number of references to valid blocks. +system.l2c.sampled_refs 174907 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.817343 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.043125 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2426.285000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8680.262415 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.407441 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000122 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.037022 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.132450 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.577037 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 109565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1063948 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1334758 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2517075 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1600724 # number of Writeback hits -system.l2c.Writeback_hits::total 1600724 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 336 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 151728 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151728 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 109565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1063948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1486486 # number of demand (read+write) hits -system.l2c.demand_hits::total 2668803 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 109565 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8804 # number of overall hits -system.l2c.overall_hits::cpu.inst 1063948 # number of overall hits -system.l2c.overall_hits::cpu.data 1486486 # number of overall hits -system.l2c.overall_hits::total 2668803 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 105 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 19652 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 45660 # number of ReadReq misses -system.l2c.ReadReq_misses::total 65434 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2521 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2521 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141129 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141129 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 19652 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 186789 # number of demand (read+write) misses -system.l2c.demand_misses::total 206563 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 105 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 17 # number of overall misses -system.l2c.overall_misses::cpu.inst 19652 # number of overall misses -system.l2c.overall_misses::cpu.data 186789 # number of overall misses -system.l2c.overall_misses::total 206563 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5480500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 886000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 1027000000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 2399872000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3433238500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39054500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39054500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7349617000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7349617000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 5480500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 886000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 1027000000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 9749489000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10782855500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 5480500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 886000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 1027000000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 9749489000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10782855500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 109670 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1083600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380418 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2582509 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1600724 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1600724 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2857 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2857 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292857 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292857 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 109670 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8821 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1083600 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1673275 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2875366 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 109670 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59976004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59976004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230258000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1230258000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206262500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61206262500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026162 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020565 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.847162 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847162 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.447176 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.447176 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.064162 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000633 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015640 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099921 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064162 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47578 # number of replacements -system.iocache.tagsinuse 0.166155 # Cycle average of tags in use +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.147452 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47594 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.010385 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.010385 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.warmup_cycle 4996357767000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.147452 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009216 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009216 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses -system.iocache.demand_misses::total 47633 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses -system.iocache.overall_misses::total 47633 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114379932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 114379932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6373400160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6373400160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6487780092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6487780092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6487780092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6487780092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 113343932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 113343932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6309295160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6309295160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6422639092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6422639092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6422639092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6422639092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125380.455752 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 135044.845034 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134861.395347 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134861.395347 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 66555216 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5928.138951 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66880982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66312982 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66312982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3879551568 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3879551568 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3945864550 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3945864550 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,413 +393,413 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 461333918 # number of cpu cycles simulated +system.cpu.numCycles 459902894 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90003796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90003796 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1173183 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84315614 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81694619 # Number of BTB hits +system.cpu.BPredUnit.lookups 90033870 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90033870 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1172024 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84304215 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81702749 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29624871 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446885817 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90003796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81694619 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169759235 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5280537 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141697 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98681847 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37869 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9366803 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 526850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4968 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 302354351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.908315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29359737 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 447000113 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90033870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81702749 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169792580 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290860 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 149776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97806900 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 36600 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 214 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9375679 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523969 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5232 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 301265833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.919513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.390338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 133032171 44.00% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1767192 0.58% 44.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72774261 24.07% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988290 0.33% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1636300 0.54% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3666710 1.21% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1141173 0.38% 71.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1450765 0.48% 71.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85897489 28.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131910949 43.79% 43.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1767278 0.59% 44.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72780383 24.16% 68.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 988082 0.33% 68.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1637864 0.54% 69.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3667894 1.22% 70.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1147346 0.38% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1446143 0.48% 71.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85919894 28.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 302354351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195095 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.968682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34659888 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94852238 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163950875 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4820336 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4071014 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876062076 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 946 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4071014 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38916721 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39863124 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10415671 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 164017891 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45069930 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872218550 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9888 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34551329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3873333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31844673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1393807250 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2487751490 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2487750754 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 736 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347499622 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46307621 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 471559 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 478592 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46419855 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18887370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10441908 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1295912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1023550 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865497785 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1720774 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864256485 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25797308 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 52868100 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205226 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 302354351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.858423 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.389396 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 301265833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195767 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.971945 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34474494 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93907388 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163990791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4810664 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4082496 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876264710 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4082496 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38727929 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39278399 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10114969 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 164053704 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45008336 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872424503 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9763 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34576608 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3790570 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31863881 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394114241 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488384373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488383477 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347565425 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46548809 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469868 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476809 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46309775 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18907776 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10445518 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1298255 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1025454 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865635268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1719822 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864337626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112774 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25913081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53108345 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 204185 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 301265833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.869020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.387854 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 95961753 31.74% 31.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22210791 7.35% 39.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 18920489 6.26% 45.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7861035 2.60% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80643891 26.67% 74.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3288348 1.09% 75.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72804040 24.08% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 531965 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 94932773 31.51% 31.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22142074 7.35% 38.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 18888671 6.27% 45.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7860945 2.61% 47.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80656411 26.77% 74.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3302785 1.10% 75.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72810465 24.17% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 540656 0.18% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 131053 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 302354351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 301265833 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 168781 8.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1775830 84.20% 92.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 164454 7.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 170381 8.07% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1776523 84.09% 92.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 165648 7.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 295147 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829365416 95.96% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25156928 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9438994 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 297256 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829421724 95.96% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25169917 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9448729 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864256485 # Type of FU issued -system.cpu.iq.rate 1.873386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2109065 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002440 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2033227215 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893026339 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853844323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 314 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 348 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866070258 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1582954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864337626 # Type of FU issued +system.cpu.iq.rate 1.879392 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2112552 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2032304206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893278706 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853918308 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 381 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 98 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866152744 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1572054 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3588586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21998 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11829 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2035325 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3603717 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21501 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11898 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2033136 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821677 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821637 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2389 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4071014 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26002336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1398631 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867218559 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 301512 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18887370 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10441908 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 882377 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 699130 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12813 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11829 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 701390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323826 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862338984 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24725426 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1917500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4082496 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25489851 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1396862 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867355090 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297196 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18907776 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10445518 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 881207 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 698514 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12367 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11898 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 698869 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624345 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1323214 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862415633 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24733940 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1921992 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33920026 # number of memory reference insts executed -system.cpu.iew.exec_branches 86488789 # Number of branches executed -system.cpu.iew.exec_stores 9194600 # Number of stores executed -system.cpu.iew.exec_rate 1.869230 # Inst execution rate -system.cpu.iew.wb_sent 861878608 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853844403 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669889230 # num instructions producing a value -system.cpu.iew.wb_consumers 1919047361 # num instructions consuming a value +system.cpu.iew.exec_refs 33937040 # number of memory reference insts executed +system.cpu.iew.exec_branches 86496224 # Number of branches executed +system.cpu.iew.exec_stores 9203100 # Number of stores executed +system.cpu.iew.exec_rate 1.875212 # Inst execution rate +system.cpu.iew.wb_sent 861954133 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853918406 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669978264 # num instructions producing a value +system.cpu.iew.wb_consumers 1919317191 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.850816 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.349074 # average fanout of values written-back +system.cpu.iew.wb_rate 1.856736 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.349071 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426506235 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840483958 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26630365 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515546 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1177301 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 298298866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.817590 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864095 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426532736 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840526050 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26723975 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515635 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1176103 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 297198870 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.828160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 117621447 39.43% 39.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14371375 4.82% 44.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4300832 1.44% 45.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76665686 25.70% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3908070 1.31% 72.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1784515 0.60% 73.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1116090 0.37% 73.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984342 24.13% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6546509 2.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 116541377 39.21% 39.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14339767 4.82% 44.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4295097 1.45% 45.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76671720 25.80% 71.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3910835 1.32% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1786901 0.60% 73.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1117084 0.38% 73.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71988132 24.22% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6547957 2.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 298298866 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426506235 # Number of instructions committed -system.cpu.commit.committedOps 840483958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 297198870 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426532736 # Number of instructions committed +system.cpu.commit.committedOps 840526050 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23705364 # Number of memory references committed -system.cpu.commit.loads 15298781 # Number of loads committed -system.cpu.commit.membars 781557 # Number of memory barriers committed -system.cpu.commit.branches 85502209 # Number of branches committed +system.cpu.commit.refs 23716438 # Number of memory references committed +system.cpu.commit.loads 15304056 # Number of loads committed +system.cpu.commit.membars 781569 # Number of memory barriers committed +system.cpu.commit.branches 85505804 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768310964 # Number of committed integer instructions. +system.cpu.commit.int_insts 768351683 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6546509 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6547957 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1158787398 # The number of ROB reads -system.cpu.rob.rob_writes 1738314967 # The number of ROB writes -system.cpu.timesIdled 2905540 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 158979567 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9853691832 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426506235 # Number of Instructions Simulated -system.cpu.committedOps 840483958 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426506235 # Number of Instructions Simulated -system.cpu.cpi 1.081658 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.081658 # CPI: Total CPI of All Threads -system.cpu.ipc 0.924507 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.924507 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163093750 # number of integer regfile reads -system.cpu.int_regfile_writes 1362601470 # number of integer regfile writes -system.cpu.fp_regfile_reads 80 # number of floating regfile reads -system.cpu.misc_regfile_reads 281025584 # number of misc regfile reads -system.cpu.misc_regfile_writes 403474 # number of misc regfile writes -system.cpu.icache.replacements 1083149 # number of replacements -system.cpu.icache.tagsinuse 510.211811 # Cycle average of tags in use -system.cpu.icache.total_refs 8213603 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1083661 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579495 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56616978000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.211811 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996507 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996507 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8213603 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8213603 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8213603 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8213603 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8213603 # number of overall hits -system.cpu.icache.overall_hits::total 8213603 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1153196 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1153196 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1153196 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1153196 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1153196 # number of overall misses -system.cpu.icache.overall_misses::total 1153196 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17226505491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17226505491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17226505491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17226505491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17226505491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1157821631 # The number of ROB reads +system.cpu.rob.rob_writes 1738597524 # The number of ROB writes +system.cpu.timesIdled 2901104 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 158637061 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9834920608 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426532736 # Number of Instructions Simulated +system.cpu.committedOps 840526050 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426532736 # Number of Instructions Simulated +system.cpu.cpi 1.078236 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.078236 # CPI: Total CPI of All Threads +system.cpu.ipc 0.927441 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.927441 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163268420 # number of integer regfile reads +system.cpu.int_regfile_writes 1362711366 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.misc_regfile_reads 281060274 # number of misc regfile reads +system.cpu.misc_regfile_writes 403581 # number of misc regfile writes +system.cpu.icache.replacements 1071746 # number of replacements +system.cpu.icache.tagsinuse 509.688073 # Cycle average of tags in use +system.cpu.icache.total_refs 8235470 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072258 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.680493 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56594855000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.688073 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8235470 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8235470 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8235470 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8235470 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8235470 # number of overall hits +system.cpu.icache.overall_hits::total 8235470 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1140205 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9375675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9375675 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9375675 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9375675 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9375675 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121613 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121613 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121613 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121613 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121613 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121613 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14836.572363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14836.572363 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2216492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9197.062241 # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1084802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1084802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1084802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1572 # number of writebacks +system.cpu.icache.writebacks::total 1572 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67614 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67614 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67614 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67614 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67614 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67614 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072591 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072591 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114401 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114401 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114401 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114401 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11978.669868 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11978.669868 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10825 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375712 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375712 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27407 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27407 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 12981 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.013322 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25373 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 12993 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.952821 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5123561713000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.013322 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375833 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375833 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25418 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25418 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27410 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27410 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27410 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27410 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11687 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11687 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11687 # 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average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11935.985286 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11935.985286 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1456 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1456 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11687 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11687 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11687 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11687 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11687 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1460 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1460 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13864 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13864 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13864 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 13864 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13864 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 13864 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 123445500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 123445500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 123445500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 123445500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 123445500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 123445500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352935 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352935 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352908 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352908 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8904.032025 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 116553 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866227 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866227 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135961 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135961 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135961 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135961 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135961 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135961 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117570 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 117570 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117570 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 117570 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117570 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 117570 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1642151000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1642151000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1642151000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1642151000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1642151000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 120380 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.933344 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 133363 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 120396 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.107703 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5104613509000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.933344 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133363 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 133363 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133363 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 133363 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133363 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 133363 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 121457 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 121457 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 121457 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 121457 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 121457 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 121457 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1679660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1679660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1679660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1679660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1679660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1679660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 254820 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 254820 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 254820 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 254820 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 254820 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 254820 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.476638 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.476638 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.476638 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.476638 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.476638 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.476638 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36817 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36817 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117570 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117570 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117570 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 117570 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117570 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 37082 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 37082 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 121457 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 121457 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 121457 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 121457 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 121457 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 121457 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1312360500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1312360500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1312360500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.476638 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.476638 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.476638 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673290 # number of replacements -system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use -system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1670972 # number of replacements +system.cpu.dcache.tagsinuse 511.998179 # Cycle average of tags in use +system.cpu.dcache.total_refs 19056575 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1671484 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.400992 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10943323 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10943323 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8079241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8079241 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19022564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19022564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19022564 # number of overall hits -system.cpu.dcache.overall_hits::total 19022564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2411423 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2411423 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318003 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318003 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2729426 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2729426 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2729426 # number of overall misses -system.cpu.dcache.overall_misses::total 2729426 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36183001500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36183001500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10564799496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10564799496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46747800996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46747800996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46747800996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46747800996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13354746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.998179 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10967822 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10967822 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085914 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085914 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19053736 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19053736 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19053736 # number of overall hits +system.cpu.dcache.overall_hits::total 19053736 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2407391 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2407391 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724500 # number of overall misses +system.cpu.dcache.overall_misses::total 2724500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35545734500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35545734500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10083377990 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10083377990 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45629112490 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45629112490 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45629112490 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45629112490 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13375213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13375213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8403023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21778236 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21778236 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21778236 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21778236 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.179989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.179989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037737 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037737 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.125102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.125102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.125102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.125102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.251885 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.251885 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31797.829737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31797.829737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16747.701409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16747.701409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16747.701409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19144990 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3356 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5704.705006 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560881 # number of writebacks -system.cpu.dcache.writebacks::total 1560881 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1029888 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1029888 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22394 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1052282 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1052282 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1052282 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1052282 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381535 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381535 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 295609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18178804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18178804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9348322497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9348322497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27527126997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27527126997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27527126997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1570390 # number of writebacks +system.cpu.dcache.writebacks::total 1570390 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1028077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1028077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22422 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22422 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1050499 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1050499 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1050499 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1050499 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1379314 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1379314 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294687 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294687 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1674001 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1674001 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1674001 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1674001 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17753874500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17753874500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8876538990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8876538990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26630413490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26630413490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26630413490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26630413490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208379000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208379000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393915000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393915000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602294000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602294000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103125 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103125 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076866 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076866 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076866 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.524903 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.524903 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30121.922548 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30121.922548 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15908.242283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15908.242283 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index c1fb80fc3..201ee02a7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index b4ecd43cf..4b4f6933d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:43:43 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:24 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274300226500 because target called exit() +Exiting @ tick 271948359500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index e5597cd29..c0f2578f2 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274300 # Number of seconds simulated -sim_ticks 274300226500 # Number of ticks simulated -final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271948 # Number of seconds simulated +sim_ticks 271948359500 # Number of ticks simulated +final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112537 # Simulator instruction rate (inst/s) -host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51289289 # Simulator tick rate (ticks/s) -host_mem_usage 215256 # Number of bytes of host memory used -host_seconds 5348.10 # Real time elapsed on the host +host_inst_rate 167086 # Simulator instruction rate (inst/s) +host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75497413 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 3602.09 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory -system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory +system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory +system.physmem.bytes_written::total 57024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory +system.physmem.num_writes::total 891 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517577 # DTB read hits +system.cpu.dtb.read_hits 114517207 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520208 # DTB read accesses -system.cpu.dtb.write_hits 39666608 # DTB write hits +system.cpu.dtb.read_accesses 114519838 # DTB read accesses +system.cpu.dtb.write_hits 39661898 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668910 # DTB write accesses -system.cpu.dtb.data_hits 154184185 # DTB hits +system.cpu.dtb.write_accesses 39664200 # DTB write accesses +system.cpu.dtb.data_hits 154179105 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189118 # DTB accesses -system.cpu.itb.fetch_hits 25020502 # ITB hits +system.cpu.dtb.data_accesses 154184038 # DTB accesses +system.cpu.itb.fetch_hits 25013413 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25020524 # ITB accesses +system.cpu.itb.fetch_accesses 25013435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548600454 # number of cpu cycles simulated +system.cpu.numCycles 543896720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits +system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155051949 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155049936 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. -system.cpu.activity 89.165242 # Percentage of cycles cpu is active +system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. +system.cpu.activity 89.936283 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,72 +114,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads +system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use -system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use +system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits -system.cpu.icache.overall_hits::total 25019479 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits +system.cpu.icache.overall_hits::total 25012389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,70 +188,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits -system.cpu.dcache.overall_hits::total 152394215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses -system.cpu.dcache.overall_misses::total 1571148 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits +system.cpu.dcache.overall_hits::total 152406141 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses +system.cpu.dcache.overall_misses::total 1559222 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,65 +318,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 01ebbe1c7..53e4b73f0 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ef914e93c..21003a7f0 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:29 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 134621123500 because target called exit() +Exiting @ tick 133563007500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index aa861e979..38226af10 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134621 # Number of seconds simulated -sim_ticks 134621123500 # Number of ticks simulated -final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133563 # Number of seconds simulated +sim_ticks 133563007500 # Number of ticks simulated +final_tick 133563007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192359 # Simulator instruction rate (inst/s) -host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45788058 # Simulator tick rate (ticks/s) -host_mem_usage 216172 # Number of bytes of host memory used -host_seconds 2940.09 # Real time elapsed on the host +host_inst_rate 301381 # Simulator instruction rate (inst/s) +host_op_rate 301381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71175252 # Simulator tick rate (ticks/s) +host_mem_usage 220044 # Number of bytes of host memory used +host_seconds 1876.54 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory -system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58688 # Number of bytes written to this memory +system.physmem.bytes_written::total 58688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26383 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 917 # Number of write requests responded to by this memory +system.physmem.num_writes::total 917 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 457612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12184452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12642063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 439403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 457612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12184452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13081466 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123836708 # DTB read hits -system.cpu.dtb.read_misses 23555 # DTB read misses +system.cpu.dtb.read_hits 123849413 # DTB read hits +system.cpu.dtb.read_misses 20691 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123860263 # DTB read accesses -system.cpu.dtb.write_hits 40831838 # DTB write hits -system.cpu.dtb.write_misses 31545 # DTB write misses +system.cpu.dtb.read_accesses 123870104 # DTB read accesses +system.cpu.dtb.write_hits 40835064 # DTB write hits +system.cpu.dtb.write_misses 30091 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40863383 # DTB write accesses -system.cpu.dtb.data_hits 164668546 # DTB hits -system.cpu.dtb.data_misses 55100 # DTB misses +system.cpu.dtb.write_accesses 40865155 # DTB write accesses +system.cpu.dtb.data_hits 164684477 # DTB hits +system.cpu.dtb.data_misses 50782 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164723646 # DTB accesses -system.cpu.itb.fetch_hits 66483943 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 164735259 # DTB accesses +system.cpu.itb.fetch_hits 66492910 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66483980 # ITB accesses +system.cpu.itb.fetch_accesses 66492948 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 269242248 # number of cpu cycles simulated +system.cpu.numCycles 267126016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits +system.cpu.BPredUnit.lookups 78502606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72859176 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3048930 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42879233 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41644328 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1629564 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 215 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68435581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710898129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78502606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43273892 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119207604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12936161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69569484 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66492910 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.661634 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.464377 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147883255 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10367188 3.88% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11844651 4.43% 63.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10612793 3.97% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990815 2.62% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2667876 1.00% 71.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3494727 1.31% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104174 1.16% 73.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70125380 26.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293879 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.661284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85625908 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53897418 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104721883 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12969411 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9876239 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3910148 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702131172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4692 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9876239 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93864195 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11132886 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104174566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48041540 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690226135 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36911224 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4900299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527321421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906904042 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906901104 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2938 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63466532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 116 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106984731 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129019631 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42434130 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14712304 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9648397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626510721 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 98 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608418192 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 334492 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60261200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33473416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 81 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267090859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.835634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52595450 19.69% 19.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54748440 20.50% 40.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53400082 19.99% 60.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36696955 13.74% 73.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30804090 11.53% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24162728 9.05% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10693904 4.00% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3328381 1.25% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 660829 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267090859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2950080 75.40% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 582636 14.89% 90.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 379789 9.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441018930 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7345 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued @@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126131577 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41260299 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued -system.cpu.iq.rate 2.259665 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608418192 # Type of FU issued +system.cpu.iq.rate 2.277645 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3912544 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1488170355 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686774500 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598832188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2359 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612328769 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1967 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12182137 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14505589 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4885 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2982809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6785 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 71183 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9876239 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 295412 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670453714 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691855 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129019631 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42434130 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 98 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 899 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7278 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4885 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1348504 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2206028 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3554532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602596052 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123870207 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5822140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43926324 # number of nop insts executed -system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed -system.cpu.iew.exec_branches 67006670 # Number of branches executed -system.cpu.iew.exec_stores 40880471 # Number of stores executed -system.cpu.iew.exec_rate 2.238049 # Inst execution rate -system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417486240 # num instructions producing a value -system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value +system.cpu.iew.exec_nop 43942895 # number of nop insts executed +system.cpu.iew.exec_refs 164752686 # number of memory reference insts executed +system.cpu.iew.exec_branches 67005259 # Number of branches executed +system.cpu.iew.exec_stores 40882479 # Number of stores executed +system.cpu.iew.exec_rate 2.255849 # Inst execution rate +system.cpu.iew.wb_sent 600080079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598833907 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417539542 # num instructions producing a value +system.cpu.iew.wb_consumers 531416482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back +system.cpu.iew.wb_rate 2.241766 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785711 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68437583 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3047922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257214620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.339902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78375558 30.47% 30.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72865724 28.33% 58.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26619590 10.35% 69.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8074736 3.14% 72.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10311668 4.01% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20443429 7.95% 84.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6319286 2.46% 86.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3488714 1.36% 88.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30715915 11.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257214620 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30715915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 898866221 # The number of ROB reads -system.cpu.rob.rob_writes 1350401622 # The number of ROB writes -system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 896728862 # The number of ROB reads +system.cpu.rob.rob_writes 1350487768 # The number of ROB writes +system.cpu.timesIdled 758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35157 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads -system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848641681 # number of integer regfile reads -system.cpu.int_regfile_writes 492726607 # number of integer regfile writes -system.cpu.fp_regfile_reads 387 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cpi 0.472328 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.472328 # CPI: Total CPI of All Threads +system.cpu.ipc 2.117175 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.117175 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848664377 # number of integer regfile reads +system.cpu.int_regfile_writes 492741272 # number of integer regfile writes +system.cpu.fp_regfile_reads 384 # number of floating regfile reads +system.cpu.fp_regfile_writes 47 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 49 # number of replacements -system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use -system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.496665 # Cycle average of tags in use +system.cpu.icache.total_refs 66491540 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 975 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 68196.451282 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits -system.cpu.icache.overall_hits::total 66482496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses -system.cpu.icache.overall_misses::total 1447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 827.496665 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404051 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404051 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66491540 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66491540 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66491540 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66491540 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66491540 # number of overall hits +system.cpu.icache.overall_hits::total 66491540 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1370 # number of overall misses +system.cpu.icache.overall_misses::total 1370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47830500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47830500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47830500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47830500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66492910 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66492910 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66492910 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66492910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34912.773723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,293 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 395 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 395 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 395 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 395 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits -system.cpu.dcache.overall_hits::total 149091370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses -system.cpu.dcache.overall_misses::total 2023111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31385446422 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999456 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111034129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111034129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38205852 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38205852 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 59 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 59 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149239981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149239981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149239981 # number of overall hits +system.cpu.dcache.overall_hits::total 149239981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 620415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 620415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1245469 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1245469 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1865884 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1865884 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1865884 # number of overall misses +system.cpu.dcache.overall_misses::total 1865884 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17349599733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17349599733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111654544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111654544 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151105865 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151105865 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151105865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151105865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.012348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.012348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.012348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.012348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7598.426054 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7598.426054 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 113496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 187500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4934.608696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks -system.cpu.dcache.writebacks::total 415225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444730 # number of writebacks +system.cpu.dcache.writebacks::total 444730 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410277 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 410277 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 991041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 991041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1401318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1401318 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210138 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254428 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254428 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74480 # number of replacements -system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use -system.cpu.l2cache.total_refs 461925 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90375 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.111203 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 947 # number of replacements +system.cpu.l2cache.tagsinuse 22959.894157 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555227 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23376 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.752011 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15915.661195 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.497783 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1695.845621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.485707 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.538666 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 178382 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 178382 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 415225 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 415225 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194684 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 373066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 373066 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 373066 # number of overall hits -system.cpu.l2cache.overall_hits::total 373066 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1002 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31935 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32937 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 59838 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 59838 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1002 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91773 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92775 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1002 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91773 # number of overall misses -system.cpu.l2cache.overall_misses::total 92775 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34422500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1098528500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1132951000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34422500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3165359000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3199781500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34422500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3165359000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3199781500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1002 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210317 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464839 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465841 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464839 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 955 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26383 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 133026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 162752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801450000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831176000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801450000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831176000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f4efff3d6..265a2a956 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index fcee7bced..be37b32c1 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:36 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 765623032000 because target called exit() +Exiting @ tick 762853846000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4082e04ad..a7b4a0a92 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.765623 # Number of seconds simulated -sim_ticks 765623032000 # Number of ticks simulated -final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762854 # Number of seconds simulated +sim_ticks 762853846000 # Number of ticks simulated +final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675799 # Simulator instruction rate (inst/s) -host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2131786057 # Simulator tick rate (ticks/s) -host_mem_usage 214908 # Number of bytes of host memory used -host_seconds 359.15 # Real time elapsed on the host +host_inst_rate 2331221 # Simulator instruction rate (inst/s) +host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2954822927 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 258.17 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory -system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory +system.physmem.bytes_written::total 56512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory +system.physmem.num_writes::total 883 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numCycles 1525707692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_busy_cycles 1525707692 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,65 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73734 # number of replacements -system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 903 # number of replacements +system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits -system.cpu.l2cache.overall_hits::total 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92031 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses @@ -325,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 456190 # n system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -355,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks -system.cpu.l2cache.writebacks::total 59341 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks +system.cpu.l2cache.writebacks::total 883 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index c1e9b189c..d26a36061 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 1edb7f5fa..2a1e3a459 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:39 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:13 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164248292500 because target called exit() +Exiting @ tick 163291004000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index ed106fd55..4e7834f0d 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164248 # Number of seconds simulated -sim_ticks 164248292500 # Number of ticks simulated -final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.163291 # Number of seconds simulated +sim_ticks 163291004000 # Number of ticks simulated +final_tick 163291004000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143439 # Simulator instruction rate (inst/s) -host_op_rate 151568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41328806 # Simulator tick rate (ticks/s) -host_mem_usage 231960 # Number of bytes of host memory used -host_seconds 3974.18 # Real time elapsed on the host -sim_insts 570052728 # Number of instructions simulated -sim_ops 602360935 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory -system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory -system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory -system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 225808 # Simulator instruction rate (inst/s) +host_op_rate 238605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64682367 # Simulator tick rate (ticks/s) +host_mem_usage 234804 # Number of bytes of host memory used +host_seconds 2524.51 # Real time elapsed on the host +sim_insts 570052735 # Number of instructions simulated +sim_ops 602360941 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1770240 # Number of bytes read from this memory +system.physmem.bytes_read::total 1818112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 203264 # Number of bytes written to this memory +system.physmem.bytes_written::total 203264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27660 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3176 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3176 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 293170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10841014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11134183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 293170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 293170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1244796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1244796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1244796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 293170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10841014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12378980 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328496586 # number of cpu cycles simulated +system.cpu.numCycles 326582009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits +system.cpu.BPredUnit.lookups 85496783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80297868 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2361759 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47129611 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46810915 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1442822 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 939 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68930661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669745010 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85496783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48253737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130048027 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13475244 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 116341672 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 687 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67499108 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807540 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 326356874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.186850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.203825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 196309073 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20957347 6.42% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4946491 1.52% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317000 4.39% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8978746 2.75% 75.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9407391 2.88% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4385745 1.34% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814869 1.78% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61240212 18.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 326356874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261793 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.050771 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93064197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93574356 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108736934 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19947205 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11034182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784985 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1738 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706036905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6288 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11034182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107346412 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13092326 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114338400 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80498732 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697255622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59224108 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19051405 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 625 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723858007 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241539667 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241539539 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419213 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96438794 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6457 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169431016 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172916819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80629893 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21434071 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27751379 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682016489 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646845145 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424192 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79472523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197906343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1840 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 326356874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.982018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.741007 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67525997 20.69% 20.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84702389 25.95% 46.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74951613 22.97% 69.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40526195 12.42% 82.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28606192 8.77% 90.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15221367 4.66% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5979021 1.83% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6497584 1.99% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2346516 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 326356874 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204976 4.99% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2983992 72.63% 77.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 919347 22.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403923414 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166112206 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76802956 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued -system.cpu.iq.rate 1.969049 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646845145 # Type of FU issued +system.cpu.iq.rate 1.980651 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4108315 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1625579635 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761505232 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638567907 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650953440 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30447417 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23963996 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129674 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10408650 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12812 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13814 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11034182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 314683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 40041 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682087415 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 655237 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172916819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80629893 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12514 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1312850 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582780 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2895630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642706502 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163991051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4138643 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66233 # number of nop insts executed -system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed -system.cpu.iew.exec_branches 74668739 # Number of branches executed -system.cpu.iew.exec_stores 76003427 # Number of stores executed -system.cpu.iew.exec_rate 1.956404 # Inst execution rate -system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420151811 # num instructions producing a value -system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value +system.cpu.iew.exec_nop 66152 # number of nop insts executed +system.cpu.iew.exec_refs 240011876 # number of memory reference insts executed +system.cpu.iew.exec_branches 74666851 # Number of branches executed +system.cpu.iew.exec_stores 76020825 # Number of stores executed +system.cpu.iew.exec_rate 1.967979 # Inst execution rate +system.cpu.iew.wb_sent 640060409 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638567923 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420584081 # num instructions producing a value +system.cpu.iew.wb_consumers 656222195 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back +system.cpu.iew.wb_rate 1.955306 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.640917 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570052786 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602360992 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79735934 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2934 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2422217 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 315322693 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910300 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.242360 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91618801 29.06% 29.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103774162 32.91% 61.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42992063 13.63% 75.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8898067 2.82% 78.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25658030 8.14% 86.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13146506 4.17% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7589457 2.41% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157745 0.37% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20487862 6.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052779 # Number of instructions committed -system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 315322693 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052786 # Number of instructions committed +system.cpu.commit.committedOps 602360992 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174061 # Number of memory references committed -system.cpu.commit.loads 148952821 # Number of loads committed +system.cpu.commit.refs 219174066 # Number of memory references committed +system.cpu.commit.loads 148952823 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828828 # Number of branches committed +system.cpu.commit.branches 70828830 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523551 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20487862 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978192675 # The number of ROB reads -system.cpu.rob.rob_writes 1375166180 # The number of ROB writes -system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052728 # Number of Instructions Simulated -system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated -system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads -system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads -system.cpu.int_regfile_writes 664199500 # number of integer regfile writes +system.cpu.rob.rob_reads 976931145 # The number of ROB reads +system.cpu.rob.rob_writes 1375260810 # The number of ROB writes +system.cpu.timesIdled 9894 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 225135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052735 # Number of Instructions Simulated +system.cpu.committedOps 602360941 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052735 # Number of Instructions Simulated +system.cpu.cpi 0.572898 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.572898 # CPI: Total CPI of All Threads +system.cpu.ipc 1.745512 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.745512 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210543463 # number of integer regfile reads +system.cpu.int_regfile_writes 664223214 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 66 # number of replacements -system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use -system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905101471 # number of misc regfile reads +system.cpu.misc_regfile_writes 3116 # number of misc regfile writes +system.cpu.icache.replacements 67 # number of replacements +system.cpu.icache.tagsinuse 689.277263 # Cycle average of tags in use +system.cpu.icache.total_refs 67498009 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 823 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 689.277263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.336561 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.336561 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67498009 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67498009 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67498009 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67498009 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1705 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1705 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1557 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1557 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201716410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201716410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201716410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201716410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001726 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001726 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018592 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018592 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012903 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012903 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007530 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007530 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007530 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007530 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7179.592820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7179.592820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9552.873883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9552.873883 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 7636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 7636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9196.023814 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9196.023814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9196.023814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9196.023814 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9916851 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2339 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4239.782386 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks -system.cpu.dcache.writebacks::total 394908 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51828 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51828 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1320801 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1320801 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1372629 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1372629 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 869866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 893163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 869866000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 893163500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089712 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089712 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063779 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063779 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31146.390374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.367942 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.655659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.472260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.472260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index c0d4f8993..ad449ce69 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 3264273f7..2afc8e322 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:49 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:38:20 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 301191370000 because target called exit() +Exiting @ tick 301191365000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index ab951a1c0..d2a90d0bb 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.301191 # Number of seconds simulated -sim_ticks 301191370000 # Number of ticks simulated -final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 301191365000 # Number of ticks simulated +final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2291609 # Simulator instruction rate (inst/s) -host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1210789798 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 248.76 # Real time elapsed on the host -sim_insts 570051644 # Number of instructions simulated -sim_ops 602359851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory -system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory +host_inst_rate 3330708 # Simulator instruction rate (inst/s) +host_op_rate 3519478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1759805795 # Simulator tick rate (ticks/s) +host_mem_usage 224176 # Number of bytes of host memory used +host_seconds 171.15 # Real time elapsed on the host +sim_insts 570051636 # Number of instructions simulated +sim_ops 602359842 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 399862020 # Number of bytes read from this memory +system.physmem.bytes_read::total 2680160120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2280298100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2280298100 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory -system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 570074525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147793178 # Number of read requests responded to by this memory +system.physmem.num_reads::total 717867703 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7570927872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1327601208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8898529080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7570927872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7570927872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 784748962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 784748962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 602382741 # number of cpu cycles simulated +system.cpu.numCycles 602382731 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 570051644 # Number of instructions committed -system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.committedInsts 570051636 # Number of instructions committed +system.cpu.committedOps 602359842 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_func_calls 1995305 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written +system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173607 # number of memory refs -system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173606 # number of memory refs +system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 602382741 # Number of busy cycles +system.cpu.num_busy_cycles 602382731 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 81852cb71..02db72141 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index dd5e622ba..b63306c7d 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:51 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:38:23 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 796762926000 because target called exit() +Exiting @ tick 794147534000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 44a2387d1..759b7639a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.796763 # Number of seconds simulated -sim_ticks 796762926000 # Number of ticks simulated -final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.794148 # Number of seconds simulated +sim_ticks 794147534000 # Number of ticks simulated +final_tick 794147534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154549 # Simulator instruction rate (inst/s) -host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618008338 # Simulator tick rate (ticks/s) -host_mem_usage 230404 # Number of bytes of host memory used -host_seconds 492.43 # Real time elapsed on the host -sim_insts 568539343 # Number of instructions simulated -sim_ops 600398281 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory -system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory -system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory -system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1549107 # Simulator instruction rate (inst/s) +host_op_rate 1635914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2163825213 # Simulator tick rate (ticks/s) +host_mem_usage 232760 # Number of bytes of host memory used +host_seconds 367.01 # Real time elapsed on the host +sim_insts 568539335 # Number of instructions simulated +sim_ops 600398272 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory +system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory +system.physmem.bytes_written::total 194752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2184783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2234023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 245234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 245234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 245234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2184783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2479257 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1593525852 # number of cpu cycles simulated +system.cpu.numCycles 1588295068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 568539343 # Number of instructions committed -system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.committedInsts 568539335 # Number of instructions committed +system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_func_calls 1995305 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written +system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173607 # number of memory refs -system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173606 # number of memory refs +system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1593525852 # Number of busy cycles +system.cpu.num_busy_cycles 1588295068 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use -system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 577.753136 # Cycle average of tags in use +system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits -system.cpu.icache.overall_hits::total 570073892 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 577.753136 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282106 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282106 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits +system.cpu.icache.overall_hits::total 570073883 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53909.797823 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use -system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.217417 # Cycle average of tags in use +system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits +system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 536853000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.217417 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999565 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999565 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits -system.cpu.dcache.overall_hits::total 216771819 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits +system.cpu.dcache.overall_hits::total 216771818 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2865114000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2865114000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4399402000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4399402000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7264516000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7264516000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7264516000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7264516000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16602.179338 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16602.179338 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks -system.cpu.dcache.writebacks::total 392392 # number of writebacks +system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks +system.cpu.dcache.writebacks::total 418219 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295666000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295666000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5951824000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5951824000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5951824000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5951824000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 71804 # number of replacements -system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use -system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 3963 # number of replacements +system.cpu.l2cache.tagsinuse 21581.956920 # Cycle average of tags in use +system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits -system.cpu.l2cache.overall_hits::total 348215 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.658629 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits +system.cpu.l2cache.overall_hits::total 410486 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses +system.cpu.l2cache.overall_misses::total 27721 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 438207 # n system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks -system.cpu.l2cache.writebacks::total 57886 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks +system.cpu.l2cache.writebacks::total 3043 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 6dd839e0e..3fe84dba1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index b261460cd..476c2fbae 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:35 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:22 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 388554296500 because target called exit() +Exiting @ tick 387353399000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 042ffd7cf..aefb16cc5 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,174 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.388554 # Number of seconds simulated -sim_ticks 388554296500 # Number of ticks simulated -final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387353 # Number of seconds simulated +sim_ticks 387353399000 # Number of ticks simulated +final_tick 387353399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160259 # Simulator instruction rate (inst/s) -host_op_rate 160764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44440455 # Simulator tick rate (ticks/s) -host_mem_usage 224388 # Number of bytes of host memory used -host_seconds 8743.26 # Real time elapsed on the host +host_inst_rate 249730 # Simulator instruction rate (inst/s) +host_op_rate 250517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69036992 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 5610.81 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory -system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory -system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679296 # Number of bytes read from this memory +system.physmem.bytes_read::total 1758080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163648 # Number of bytes written to this memory +system.physmem.bytes_written::total 163648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26239 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4335307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4538698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 422477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4335307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4961175 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 777108594 # number of cpu cycles simulated +system.cpu.numCycles 774706799 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits +system.cpu.BPredUnit.lookups 98185703 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88410338 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3780922 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66067142 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65660680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1350 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165873006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648740209 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98185703 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65662030 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330401804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21677633 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 260655576 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2710 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162813671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.134374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150186 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 444223632 57.35% 57.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74371089 9.60% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37975725 4.90% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9081691 1.17% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28157593 3.63% 76.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18825345 2.43% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11518334 1.49% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3870567 0.50% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146601460 18.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126739 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.128212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217582243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211191171 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285367331 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42792485 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17692206 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642537043 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17692206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241610870 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34893000 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51906533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303032306 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125490521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631238728 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30863889 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72608286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3100712 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755863339 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721765470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34097869 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116182244 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679261 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271420357 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438695813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180248477 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255317958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83005231 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517026367 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2634412 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460842230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78451 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113716292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136734652 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 390741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774625436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.885869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145113160 18.73% 18.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184290714 23.79% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210981910 27.24% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131056815 16.92% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70797961 9.14% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20401058 2.63% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7831654 1.01% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3987119 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 165045 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774625436 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 85311 4.91% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 160602 9.25% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164457 67.05% 81.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326416 18.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867158495 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649765 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -194,86 +193,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419768740 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171265230 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued -system.cpu.iq.rate 1.879873 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460842230 # Type of FU issued +system.cpu.iq.rate 1.885671 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1736786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3680238914 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624378157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444420049 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17886219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9235235 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8548145 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453389871 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9189145 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215326368 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36182969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244807 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13400335 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3669 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 64278 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17692206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 786779 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 100697 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613841065 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4120499 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438695813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180248477 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2548675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22528 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11302 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244807 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356307 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1558704 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3915011 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455294659 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417049506 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547571 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94187571 # number of nop insts executed -system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed -system.cpu.iew.exec_branches 89112581 # Number of branches executed -system.cpu.iew.exec_stores 170576694 # Number of stores executed -system.cpu.iew.exec_rate 1.872734 # Inst execution rate -system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154378236 # num instructions producing a value -system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value +system.cpu.iew.exec_nop 94180286 # number of nop insts executed +system.cpu.iew.exec_refs 587622925 # number of memory reference insts executed +system.cpu.iew.exec_branches 89107301 # Number of branches executed +system.cpu.iew.exec_stores 170573419 # Number of stores executed +system.cpu.iew.exec_rate 1.878510 # Inst execution rate +system.cpu.iew.wb_sent 1453892295 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452968194 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154379658 # num instructions producing a value +system.cpu.iew.wb_consumers 1205415324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back +system.cpu.iew.wb_rate 1.875507 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957661 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124212585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3780922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756933841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.967838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506392 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 238474723 31.51% 31.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276385043 36.51% 68.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43107077 5.69% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54927770 7.26% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677668 2.60% 83.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341628 1.76% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30470034 4.03% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10497412 1.39% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70052486 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756933841 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,70 +283,70 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70052486 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2302721032 # The number of ROB reads -system.cpu.rob.rob_writes 3245242057 # The number of ROB writes -system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2300552365 # The number of ROB reads +system.cpu.rob.rob_writes 3245186964 # The number of ROB writes +system.cpu.timesIdled 3424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads -system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads -system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes -system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads -system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes -system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads +system.cpu.cpi 0.552892 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552892 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808670 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980590719 # number of integer regfile reads +system.cpu.int_regfile_writes 1276263729 # number of integer regfile writes +system.cpu.fp_regfile_reads 16980710 # number of floating regfile reads +system.cpu.fp_regfile_writes 10502370 # number of floating regfile writes +system.cpu.misc_regfile_reads 593296241 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use -system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. +system.cpu.icache.replacements 213 # number of replacements +system.cpu.icache.tagsinuse 1045.821443 # Cycle average of tags in use +system.cpu.icache.total_refs 162811755 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1361 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119626.565026 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits -system.cpu.icache.overall_hits::total 162821549 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses -system.cpu.icache.overall_misses::total 1976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1045.821443 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510655 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510655 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162811755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162811755 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162811755 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162811755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162811755 # number of overall hits +system.cpu.icache.overall_hits::total 162811755 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1916 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1916 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1916 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1916 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1916 # number of overall misses +system.cpu.icache.overall_misses::total 1916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62211500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62211500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62211500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62211500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162813671 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162813671 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162813671 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162813671 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32469.467641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 32469.467641 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32469.467641 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,144 +355,144 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 554 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 554 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 554 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1362 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1362 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1362 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1362 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1362 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1362 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43838000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43838000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43838000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43838000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43838000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43838000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458031 # number of replacements -system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use -system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.replacements 458023 # number of replacements +system.cpu.dcache.tagsinuse 4095.115270 # Cycle average of tags in use +system.cpu.dcache.total_refs 365885511 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462119 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.756043 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115270 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200904892 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200904892 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164979300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164979300 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits -system.cpu.dcache.overall_hits::total 365777354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365884192 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365884192 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365884192 # number of overall hits +system.cpu.dcache.overall_hits::total 365884192 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1867516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1867516 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses -system.cpu.dcache.overall_misses::total 2675956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2634603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2634603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2634603 # number of overall misses +system.cpu.dcache.overall_misses::total 2634603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082670000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5082670000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23201861832 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23201861832 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28284531832 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28284531832 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201671979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201671979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368518795 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368518795 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368518795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368518795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011193 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007149 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007149 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6625.936823 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6625.936823 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12423.915957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12423.915957 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks -system.cpu.dcache.writebacks::total 413195 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 442952 # number of writebacks +system.cpu.dcache.writebacks::total 442952 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 567019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 567019 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1605472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1605472 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2172491 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2172491 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2172491 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2172491 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200068 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200068 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262044 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3244717853 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3244717853 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses @@ -504,100 +503,100 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9834.609276 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6857.142857 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6857.142857 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7021.496635 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7021.496635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7021.496635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7021.496635 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75325 # number of replacements -system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 440162 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26239 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27470 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38155500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 137662500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38155500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 818744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 856900000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38155500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 818744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 856900000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028149 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30995.532088 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31012.052264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31008.465608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 577b4c1d7..e273f1b51 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 4517a277e..a6ed8a59a 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:45 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:27 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2064258667000 because target called exit() +Exiting @ tick 2061521023000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 0ce23ef70..921624c02 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.064259 # Number of seconds simulated -sim_ticks 2064258667000 # Number of ticks simulated -final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061521 # Number of seconds simulated +sim_ticks 2061521023000 # Number of ticks simulated +final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371910 # Simulator instruction rate (inst/s) -host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1906915769 # Simulator tick rate (ticks/s) -host_mem_usage 223048 # Number of bytes of host memory used -host_seconds 1082.51 # Real time elapsed on the host +host_inst_rate 2065708 # Simulator instruction rate (inst/s) +host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2867468443 # Simulator tick rate (ticks/s) +host_mem_usage 221124 # Number of bytes of host memory used +host_seconds 718.93 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory -system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory +system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory +system.physmem.bytes_written::total 161472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numCycles 4123042046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108101 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_busy_cycles 4123042046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks -system.cpu.dcache.writebacks::total 407009 # number of writebacks +system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks +system.cpu.dcache.writebacks::total 435341 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74112 # number of replacements -system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use -system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2614 # number of replacements +system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use +system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits -system.cpu.l2cache.overall_hits::total 361985 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses -system.cpu.l2cache.overall_misses::total 92343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.254810 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026168 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015236 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677090 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 237875 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 237875 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 427087 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 427167 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 80 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 427087 # number of overall hits +system.cpu.l2cache.overall_hits::total 427167 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1027 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5301 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21860 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21860 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27161 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses +system.cpu.l2cache.overall_misses::total 27161 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses @@ -316,17 +316,17 @@ system.cpu.l2cache.demand_accesses::total 454328 # n system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -346,41 +346,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks -system.cpu.l2cache.writebacks::total 59035 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks +system.cpu.l2cache.writebacks::total 2523 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 54d39141c..994a9cc44 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 5eab9f73c..486e549a7 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:07:25 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:06:37 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -21,7 +21,6 @@ Uncompressed data compared correctly Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data -info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -40,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636988382500 because target called exit() +Exiting @ tick 636762784500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 26e1be238..608862386 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636988 # Number of seconds simulated -sim_ticks 636988382500 # Number of ticks simulated -final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.636763 # Number of seconds simulated +sim_ticks 636762784500 # Number of ticks simulated +final_tick 636762784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63436 # Simulator instruction rate (inst/s) -host_op_rate 116883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45916521 # Simulator tick rate (ticks/s) -host_mem_usage 227532 # Number of bytes of host memory used -host_seconds 13872.75 # Real time elapsed on the host +host_inst_rate 102830 # Simulator instruction rate (inst/s) +host_op_rate 189469 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74404788 # Simulator tick rate (ticks/s) +host_mem_usage 230588 # Number of bytes of host memory used +host_seconds 8558.09 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory -system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory -system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory -system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694912 # Number of bytes read from this memory +system.physmem.bytes_read::total 1753728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162944 # Number of bytes written to this memory +system.physmem.bytes_written::total 162944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26483 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2546 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2546 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2661764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2754131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 255894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 255894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 255894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2661764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3010025 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273976766 # number of cpu cycles simulated +system.cpu.numCycles 1273525570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154678064 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154678064 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26667110 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77406078 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 77035710 # Number of BTB hits +system.cpu.BPredUnit.lookups 155344135 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 155344135 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26655607 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77245204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76889704 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180711057 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1490230522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154678064 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 77035710 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402278451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93695646 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 624053491 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1298 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186830267 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9529255 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273914012 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.999814 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.235188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180802236 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1488442027 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155344135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76889704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402274046 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93385401 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 623851243 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1029 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186094276 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8755292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1273499648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.998943 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.233820 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878853214 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24303546 1.91% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15677834 1.23% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17928928 1.41% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26735770 2.10% 75.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18262172 1.43% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28765750 2.26% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39797773 3.12% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 223589025 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878442365 68.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24602632 1.93% 70.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15260428 1.20% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18256548 1.43% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26724815 2.10% 75.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18280477 1.44% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29063774 2.28% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39873032 3.13% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 222995577 17.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273914012 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121414 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169747 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300082895 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537078967 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281798821 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88083788 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66869541 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2368899404 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66869541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352603459 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124071504 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2838 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302490800 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427875870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2273771459 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293326885 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103161675 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 640 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3463149697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7120628194 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7120621014 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7180 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1273499648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121980 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168757 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300474409 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 536583689 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281514067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88356524 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66570959 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2368586772 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66570959 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352813558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123796819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302654861 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427661779 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2273830132 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293323791 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 102919235 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3464511326 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7120107939 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7120100187 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 969288727 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 110 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 746079760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 546341437 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222247757 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352469730 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147023702 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027529381 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 546 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785574895 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118982 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405869160 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1051620727 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273914012 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.401645 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311838 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 970650356 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 98 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745542263 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 545308074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222233244 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 351719357 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 147016761 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2026127683 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 554 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785922004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 133826 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 404499601 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1046828617 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1273499648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.402373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.312278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347011244 27.24% 27.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447440186 35.12% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243114046 19.08% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151317631 11.88% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40944695 3.21% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32410749 2.54% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9957171 0.78% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1368147 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 350143 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 346409167 27.20% 27.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447658448 35.15% 62.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243252093 19.10% 81.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151077765 11.86% 93.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40789672 3.20% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32618177 2.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9933898 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1410310 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 350118 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273914012 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1273499648 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 237387 9.29% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2138623 83.73% 93.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178205 6.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 252918 9.83% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2142956 83.30% 93.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 176798 6.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46809715 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1066790690 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46813783 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1067070411 59.75% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued @@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479501542 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192472948 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479563179 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192474631 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785574895 # Type of FU issued -system.cpu.iq.rate 1.401576 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2554215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4847736227 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2433580235 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1726806271 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 772 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741319146 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208956586 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785922004 # Type of FU issued +system.cpu.iq.rate 1.402345 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2572672 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001441 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4848049464 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2430808619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1727155501 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 690 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2256 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741680668 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208913373 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 127299312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36681 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 190307 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34061700 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 126265949 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36209 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 190191 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34047187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1845 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1764 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66869541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 356934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88692 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027529927 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63849570 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 546341437 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222247757 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 103 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48888 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 421 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 190307 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2139656 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24653796 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26793452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767588629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473898164 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17986266 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66570959 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 346337 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 84829 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2026128237 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63751416 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 545308074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222233244 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49329 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 412 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 190191 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2137841 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24642910 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26780751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767814472 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473818516 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18107532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665742013 # number of memory reference insts executed -system.cpu.iew.exec_branches 109684623 # Number of branches executed -system.cpu.iew.exec_stores 191843849 # Number of stores executed -system.cpu.iew.exec_rate 1.387458 # Inst execution rate -system.cpu.iew.wb_sent 1728148485 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1726806355 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262041827 # num instructions producing a value -system.cpu.iew.wb_consumers 2984894243 # num instructions consuming a value +system.cpu.iew.exec_refs 665662363 # number of memory reference insts executed +system.cpu.iew.exec_branches 109724389 # Number of branches executed +system.cpu.iew.exec_stores 191843847 # Number of stores executed +system.cpu.iew.exec_rate 1.388126 # Inst execution rate +system.cpu.iew.wb_sent 1728501294 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1727155577 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262384078 # num instructions producing a value +system.cpu.iew.wb_consumers 2985492726 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.422810 # average fanout of values written-back +system.cpu.iew.wb_rate 1.356200 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.422839 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 406040141 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 404636626 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26667277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207044471 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343359 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.660546 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26655738 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1206928689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343488 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.659364 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437250010 36.22% 36.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432641487 35.84% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93464877 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134893392 11.18% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35716518 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23306370 1.93% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25727632 2.13% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8874629 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15169556 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 436768152 36.19% 36.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432905754 35.87% 72.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93527824 7.75% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134952786 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35694459 2.96% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23721563 1.97% 95.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25354378 2.10% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8867881 0.73% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15135892 1.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207044471 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1206928689 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,68 +284,68 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15169556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15135892 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3219409038 # The number of ROB reads -system.cpu.rob.rob_writes 4121954747 # The number of ROB writes -system.cpu.timesIdled 1354 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 62754 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3217923405 # The number of ROB reads +system.cpu.rob.rob_writes 4118849074 # The number of ROB writes +system.cpu.timesIdled 528 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25922 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.447659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447659 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473469252 # number of integer regfile reads -system.cpu.int_regfile_writes 2589680881 # number of integer regfile writes -system.cpu.fp_regfile_reads 84 # number of floating regfile reads -system.cpu.misc_regfile_reads 911429698 # number of misc regfile reads -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 827.099302 # Cycle average of tags in use -system.cpu.icache.total_refs 186828876 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201324.219828 # Average number of references to valid blocks. +system.cpu.cpi 1.447147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.691015 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.691015 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4473867691 # number of integer regfile reads +system.cpu.int_regfile_writes 2590130278 # number of integer regfile writes +system.cpu.fp_regfile_reads 76 # number of floating regfile reads +system.cpu.misc_regfile_reads 911455321 # number of misc regfile reads +system.cpu.icache.replacements 19 # number of replacements +system.cpu.icache.tagsinuse 827.665584 # Cycle average of tags in use +system.cpu.icache.total_refs 186092930 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 926 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 200964.287257 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.099302 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403857 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403857 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186828882 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186828882 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186828882 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186828882 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186828882 # number of overall hits -system.cpu.icache.overall_hits::total 186828882 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses -system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 46636000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 46636000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 46636000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 46636000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 46636000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 46636000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186830267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186830267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186830267 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186830267 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 827.665584 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404134 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404134 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186092930 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186092930 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186092930 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186092930 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186092930 # number of overall hits +system.cpu.icache.overall_hits::total 186092930 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1346 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1346 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1346 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1346 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1346 # number of overall misses +system.cpu.icache.overall_misses::total 1346 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45797000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45797000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45797000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45797000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45797000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45797000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186094276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186094276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186094276 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186094276 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186094276 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186094276 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.517088 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34024.517088 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34024.517088 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34024.517088 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 450 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 450 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 450 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 450 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 450 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 935 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 935 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 935 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 935 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 935 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 935 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 420 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 420 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 420 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 420 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 420 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 926 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 926 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 926 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 926 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35165.766739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445407 # number of replacements -system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use -system.cpu.dcache.total_refs 452671406 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449503 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.048687 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 723816000 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264901979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264901979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453124365 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453124365 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 453088036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453088036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453088036 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453088036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000779 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5997.299811 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5997.299811 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8181.910862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8181.910862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7185.489429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7185.489429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,136 +450,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 400713 # number of writebacks -system.cpu.dcache.writebacks::total 400713 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3434 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3434 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3459 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3459 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3459 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2485166000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3996172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 428484 # number of writebacks +system.cpu.dcache.writebacks::total 428484 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3123 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # 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average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 20810.359304 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 736.556866 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 675.930273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022478 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020628 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.678187 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198774 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198781 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428484 # 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number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26483 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27402 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 919 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26483 # number of overall misses +system.cpu.l2cache.overall_misses::total 27402 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31495500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157147500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 188643000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 753146000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 753146000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31495500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 910293500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 941789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31495500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 910293500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 941789000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 926 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203334 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204260 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 926 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449532 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450458 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 926 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 449532 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450458 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992441 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022426 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089046 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089046 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060831 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060831 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34271.490751 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34462.171053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34430.187991 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34354.148611 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34354.148611 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34271.490751 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34372.748556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34369.352602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34271.490751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34372.748556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34369.352602 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,52 +584,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58308 # number of writebacks -system.cpu.l2cache.writebacks::total 58308 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31911 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32836 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58321 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58321 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90232 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90232 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28735500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989353500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1018089000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1807989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1807989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28735500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2797343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2826078500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28735500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2546 # number of writebacks +system.cpu.l2cache.writebacks::total 2546 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5479 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21923 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21923 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27402 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26483 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27402 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28532500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141346000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 169878500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 679632500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 679632500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28532500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 820978500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 849511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28532500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 820978500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 849511000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022426 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060831 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060831 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31047.334059 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30996.929825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.384194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.889477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.889477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31047.334059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31000.207680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31001.788191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31047.334059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31000.207680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31001.788191 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 30e9071fd..3c1333558 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 7f0dbded6..9e79ba165 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:13:02 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:10:36 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1803258587000 because target called exit() +Exiting @ tick 1800635309000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 00ab9a331..a3d141ce0 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.803259 # Number of seconds simulated -sim_ticks 1803258587000 # Number of ticks simulated -final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.800635 # Number of seconds simulated +sim_ticks 1800635309000 # Number of ticks simulated +final_tick 1800635309000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 587265 # Simulator instruction rate (inst/s) -host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1203364849 # Simulator tick rate (ticks/s) -host_mem_usage 225604 # Number of bytes of host memory used -host_seconds 1498.51 # Real time elapsed on the host +host_inst_rate 904173 # Simulator instruction rate (inst/s) +host_op_rate 1665987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1850044030 # Simulator tick rate (ticks/s) +host_mem_usage 228536 # Number of bytes of host memory used +host_seconds 973.29 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory -system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory -system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory +system.physmem.bytes_written::total 160640 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 959981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 89213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049194 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numCycles 3601270618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025313 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228182 # nu system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.num_busy_cycles 3601270618 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.189072 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 660.189072 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322358 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322358 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.895332 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4094.895332 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999730 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999730 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2943878000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2943878000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4348848000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4348848000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7292726000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7292726000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7292726000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7292726000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16497.588497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16497.588497 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks -system.cpu.dcache.writebacks::total 396372 # number of writebacks +system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks +system.cpu.dcache.writebacks::total 422980 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3614682000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3614682000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5966582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5966582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5966582000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5966582000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 71208 # number of replacements -system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2581 # number of replacements +system.cpu.l2cache.tagsinuse 22163.019096 # Cycle average of tags in use +system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits -system.cpu.l2cache.overall_hits::total 353302 # number of overall hits +system.cpu.l2cache.occ_blocks::writebacks 21019.596332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.850673 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.572092 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.676362 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits +system.cpu.l2cache.overall_hits::total 415761 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses -system.cpu.l2cache.overall_misses::total 89468 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses +system.cpu.l2cache.overall_misses::total 27009 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses @@ -294,16 +294,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 722 system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks -system.cpu.l2cache.writebacks::total 58007 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks +system.cpu.l2cache.writebacks::total 2510 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 878800000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 878800000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1051480000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1080360000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index dcc46b583..354c87304 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 60efd00ac..e2beccd27 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:32:09 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:41:22 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 25988864000 because target called exit() +Exiting @ tick 25878583500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 90f8077ba..507566fcc 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025989 # Number of seconds simulated -sim_ticks 25988864000 # Number of ticks simulated -final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025879 # Number of seconds simulated +sim_ticks 25878583500 # Number of ticks simulated +final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141606 # Simulator instruction rate (inst/s) -host_op_rate 142623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40620332 # Simulator tick rate (ticks/s) -host_mem_usage 364696 # Number of bytes of host memory used -host_seconds 639.80 # Real time elapsed on the host -sim_insts 90599356 # Number of instructions simulated -sim_ops 91249910 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory -system.physmem.bytes_read::total 999040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory -system.physmem.bytes_written::total 2048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory -system.physmem.num_writes::total 32 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 220420 # Simulator instruction rate (inst/s) +host_op_rate 222002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62960153 # Simulator tick rate (ticks/s) +host_mem_usage 367872 # Number of bytes of host memory used +host_seconds 411.03 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory +system.physmem.bytes_read::total 992960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +70,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 51977729 # number of cpu cycles simulated +system.cpu.numCycles 51757168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits +system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued -system.cpu.iq.rate 2.032290 # Inst issue rate -system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued +system.cpu.iq.rate 2.037533 # Inst issue rate +system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36610 # number of nop insts executed -system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed -system.cpu.iew.exec_branches 21355608 # Number of branches executed -system.cpu.iew.exec_stores 5092913 # Number of stores executed -system.cpu.iew.exec_rate 2.011600 # Inst execution rate -system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62202150 # num instructions producing a value -system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value +system.cpu.iew.exec_nop 36387 # number of nop insts executed +system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed +system.cpu.iew.exec_branches 21334984 # Number of branches executed +system.cpu.iew.exec_stores 5074541 # Number of stores executed +system.cpu.iew.exec_rate 2.017760 # Inst execution rate +system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62142858 # num instructions producing a value +system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back +system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17393373 36.45% 36.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13510296 28.32% 64.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4501215 9.43% 74.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3866271 8.10% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1517173 3.18% 85.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 785983 1.65% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 854820 1.79% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253298 0.53% 89.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5031296 10.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611965 # Number of instructions committed -system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 47713725 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322631 # Number of memory references committed -system.cpu.commit.loads 22575877 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722471 # Number of branches committed +system.cpu.commit.branches 18722472 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5031296 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162161169 # The number of ROB reads -system.cpu.rob.rob_writes 242671240 # The number of ROB writes -system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599356 # Number of Instructions Simulated -system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated -system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads -system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497076309 # number of integer regfile reads -system.cpu.int_regfile_writes 120895703 # number of integer regfile writes -system.cpu.fp_regfile_reads 198 # number of floating regfile reads -system.cpu.fp_regfile_writes 527 # number of floating regfile writes -system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads -system.cpu.misc_regfile_writes 11604 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use -system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 161680438 # The number of ROB reads +system.cpu.rob.rob_writes 242031234 # The number of ROB writes +system.cpu.timesIdled 1832 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.571275 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.571275 # CPI: Total CPI of All Threads +system.cpu.ipc 1.750470 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.750470 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496537855 # number of integer regfile reads +system.cpu.int_regfile_writes 120784900 # number of integer regfile writes +system.cpu.fp_regfile_reads 199 # number of floating regfile reads +system.cpu.fp_regfile_writes 517 # number of floating regfile writes +system.cpu.misc_regfile_reads 183129525 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 635.708091 # Cycle average of tags in use +system.cpu.icache.total_refs 14075225 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 737 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19097.998643 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits -system.cpu.icache.overall_hits::total 14155750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses -system.cpu.icache.overall_misses::total 972 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.708091 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310404 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310404 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14075225 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14075225 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14075225 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14075225 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14075225 # number of overall hits +system.cpu.icache.overall_hits::total 14075225 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.icache.overall_misses::total 965 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33626500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33626500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33626500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33626500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33626500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33626500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14076190 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14076190 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14076190 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14076190 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14076190 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14076190 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34846.113990 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34846.113990 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34846.113990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34846.113990 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 228 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 228 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 228 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 228 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 228 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25265000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25265000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25265000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25265000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25265000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25265000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34280.868385 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34280.868385 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943602 # number of replacements -system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use -system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits -system.cpu.dcache.overall_hits::total 28425179 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 176055 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943587 # number of replacements +system.cpu.dcache.tagsinuse 3648.438272 # Cycle average of tags in use +system.cpu.dcache.total_refs 28413602 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947683 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.982180 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8139620000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3648.438272 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.890732 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.890732 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23842486 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23842486 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559459 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5858 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5858 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28401945 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28401945 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28401945 # number of overall hits +system.cpu.dcache.overall_hits::total 28401945 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1005618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1005618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175522 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175522 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1181140 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1181140 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1181140 # number of overall misses +system.cpu.dcache.overall_misses::total 1181140 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5786835500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5786835500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4609409990 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4609409990 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10396245490 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10396245490 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10396245490 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10396245490 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24848104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24848104 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5865 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5865 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29583085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29583085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29583085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29583085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037069 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037069 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001194 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001194 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039926 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039926 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5754.506681 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5754.506681 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26261.152391 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26261.152391 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8801.874028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8801.874028 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23117548 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8084 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2859.666997 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks -system.cpu.dcache.writebacks::total 942908 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43513 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947698 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947698 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947698 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947698 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2402147500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22414000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 33488500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14536 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14536 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 711 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 711 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22107000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8364000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452118500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452118500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22107000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460482500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 482589500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460482500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482589500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.327779 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.327779 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 394878465..0837df787 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 6025dc422..f567cacf4 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:36:14 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:44:35 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 54240666000 because target called exit() +Exiting @ tick 54240661000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index cb9066ccb..6111a0118 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.054241 # Number of seconds simulated -sim_ticks 54240666000 # Number of ticks simulated -final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 54240661000 # Number of ticks simulated +final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2223712 # Simulator instruction rate (inst/s) -host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1331261387 # Simulator tick rate (ticks/s) -host_mem_usage 354056 # Number of bytes of host memory used -host_seconds 40.74 # Real time elapsed on the host -sim_insts 90602415 # Number of instructions simulated -sim_ops 91252969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory +host_inst_rate 3184418 # Simulator instruction rate (inst/s) +host_op_rate 3207282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1906403630 # Simulator tick rate (ticks/s) +host_mem_usage 357244 # Number of bytes of host memory used +host_seconds 28.45 # Real time elapsed on the host +sim_insts 90602407 # Number of instructions simulated +sim_ops 91252960 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108481333 # number of cpu cycles simulated +system.cpu.numCycles 108481323 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602415 # Number of instructions committed -system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses +system.cpu.committedInsts 90602407 # Number of instructions committed +system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525682 # number of integer instructions +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written +system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read +system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318811 # number of memory refs -system.cpu.num_load_insts 22573967 # Number of load instructions +system.cpu.num_mem_refs 27318810 # number of memory refs +system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108481333 # Number of busy cycles +system.cpu.num_busy_cycles 108481323 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 227acc83b..8e4e9dec7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index b972e2aeb..78b502a64 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:37:05 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:44:41 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 148086239000 because target called exit() +Exiting @ tick 148083373000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index dd28872f6..63806d746 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148086 # Number of seconds simulated -sim_ticks 148086239000 # Number of ticks simulated -final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148083 # Number of seconds simulated +sim_ticks 148083373000 # Number of ticks simulated +final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056603 # Simulator instruction rate (inst/s) -host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1727464138 # Simulator tick rate (ticks/s) -host_mem_usage 363220 # Number of bytes of host memory used -host_seconds 85.72 # Real time elapsed on the host -sim_insts 90576869 # Number of instructions simulated -sim_ops 91226321 # Number of ops (including micro ops) simulated +host_inst_rate 1433979 # Simulator instruction rate (inst/s) +host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2344399916 # Simulator tick rate (ticks/s) +host_mem_usage 365828 # Number of bytes of host memory used +host_seconds 63.16 # Real time elapsed on the host +sim_insts 90576861 # Number of instructions simulated +sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory -system.physmem.bytes_read::total 986112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory +system.physmem.bytes_read::total 981760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory -system.physmem.bytes_written::total 2048 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory -system.physmem.num_writes::total 32 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 296172478 # number of cpu cycles simulated +system.cpu.numCycles 296166746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576869 # Number of instructions committed -system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses +system.cpu.committedInsts 90576861 # Number of instructions committed +system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525682 # number of integer instructions +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written +system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read +system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318811 # number of memory refs -system.cpu.num_load_insts 22573967 # Number of load instructions +system.cpu.num_mem_refs 27318810 # number of memory refs +system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 296172478 # Number of busy cycles +system.cpu.num_busy_cycles 296166746 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use -system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use +system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits -system.cpu.icache.overall_hits::total 107830181 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits +system.cpu.icache.overall_hits::total 107830172 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses @@ -126,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 32662000 system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses @@ -178,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use -system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use +system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits +system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits -system.cpu.dcache.overall_hits::total 26337591 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits +system.cpu.dcache.overall_hits::total 26337590 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses @@ -206,26 +199,26 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses @@ -234,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +243,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks -system.cpu.dcache.writebacks::total 942309 # number of writebacks +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses @@ -260,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798 system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -276,68 +269,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 634 # number of replacements -system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits -system.cpu.l2cache.overall_hits::total 931989 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits +system.cpu.l2cache.overall_hits::total 932057 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses -system.cpu.l2cache.overall_misses::total 15408 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses +system.cpu.l2cache.overall_misses::total 15340 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses @@ -347,16 +340,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 599 system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks -system.cpu.l2cache.writebacks::total 32 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index e29268380..8e6bba913 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 2436d9105..8432da315 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:55:10 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:55:42 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 362430887000 because target called exit() +Exiting @ tick 362428997000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 9186661e0..75faf8d15 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.362431 # Number of seconds simulated -sim_ticks 362430887000 # Number of ticks simulated -final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.362429 # Number of seconds simulated +sim_ticks 362428997000 # Number of ticks simulated +final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1267775 # Simulator instruction rate (inst/s) -host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1884467398 # Simulator tick rate (ticks/s) -host_mem_usage 355400 # Number of bytes of host memory used -host_seconds 192.33 # Real time elapsed on the host +host_inst_rate 1801112 # Simulator instruction rate (inst/s) +host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2677225778 # Simulator tick rate (ticks/s) +host_mem_usage 354292 # Number of bytes of host memory used +host_seconds 135.37 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory -system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory +system.physmem.bytes_read::total 998592 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory -system.physmem.bytes_written::total 2560 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory -system.physmem.num_writes::total 40 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 724861774 # number of cpu cycles simulated +system.cpu.numCycles 724857994 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825163 # Number of instructions committed @@ -54,16 +47,16 @@ system.cpu.num_mem_refs 105711442 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 724861774 # Number of busy cycles +system.cpu.num_busy_cycles 724857994 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use +system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits @@ -136,12 +129,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits @@ -164,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -194,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +205,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks -system.cpu.dcache.writebacks::total 935237 # number of writebacks +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses @@ -224,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -244,70 +237,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 865 # number of replacements -system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits -system.cpu.l2cache.overall_hits::total 924805 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits +system.cpu.l2cache.overall_hits::total 924850 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses -system.cpu.l2cache.overall_misses::total 15648 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses +system.cpu.l2cache.overall_misses::total 15603 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses @@ -317,16 +310,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 882 system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -346,41 +339,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks -system.cpu.l2cache.writebacks::total 40 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 084c1a30a..4ff330a09 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 5c8d95ce9..ec0229a1c 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:14:48 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:13:04 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ flow value : 3080014995 info: Increasing stack size by one page. checksum : 68389 optimal -Exiting @ tick 67388458000 because target called exit() +Exiting @ tick 66545720000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a6e1946c5..1baa4dbca 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,174 +1,174 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.067388 # Number of seconds simulated -sim_ticks 67388458000 # Number of ticks simulated -final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066546 # Number of seconds simulated +sim_ticks 66545720000 # Number of ticks simulated +final_tick 66545720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84988 # Simulator instruction rate (inst/s) -host_op_rate 149650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36250631 # Simulator tick rate (ticks/s) -host_mem_usage 363056 # Number of bytes of host memory used -host_seconds 1858.96 # Real time elapsed on the host +host_inst_rate 128459 # Simulator instruction rate (inst/s) +host_op_rate 226196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54107733 # Simulator tick rate (ticks/s) +host_mem_usage 365700 # Number of bytes of host memory used +host_seconds 1229.87 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory -system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory -system.physmem.bytes_written::total 897536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory -system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892992 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20032 # Number of bytes written to this memory +system.physmem.bytes_written::total 20032 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29578 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 313 # Number of write requests responded to by this memory +system.physmem.num_writes::total 313 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1027143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28446488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29473631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1027143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1027143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 301026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 301026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 301026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1027143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28446488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29774657 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 134776917 # number of cpu cycles simulated +system.cpu.numCycles 133091441 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36128556 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 36128556 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1088012 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25661198 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25550813 # Number of BTB hits +system.cpu.BPredUnit.lookups 36127369 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 36127369 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1087558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25661122 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25550646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27997413 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 196488492 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36128556 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25550813 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59432634 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8416233 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 39238726 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 27995643 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 196446977 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36127369 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25550646 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59425857 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8408654 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38346383 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27278821 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 142192 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 133966907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.578141 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.358289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 123 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27275955 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 142407 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 133058866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.362713 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77274639 57.68% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2166516 1.62% 59.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2997281 2.24% 61.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4102912 3.06% 64.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8026102 5.99% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5043006 3.76% 74.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2893464 2.16% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1468336 1.10% 77.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29994651 22.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76373838 57.40% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2167538 1.63% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2997061 2.25% 61.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4104688 3.08% 64.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8024100 6.03% 70.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5043618 3.79% 74.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2895035 2.18% 76.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1466845 1.10% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29986143 22.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 133966907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.268062 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.457879 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40465112 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 30125694 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46506148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9571987 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7297966 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 341297669 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7297966 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45865108 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5065508 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9277 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50351191 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25377857 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 337406380 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3712 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 23187560 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 79157 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 414755881 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1009935094 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1009932394 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2700 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 133058866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271448 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.476030 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40459991 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 29238616 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46513629 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9555795 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7290835 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 341218691 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7290835 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45832356 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4342736 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50371616 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25212314 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 337359064 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3751 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 23039182 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 70135 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 414697998 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1009810700 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1009808348 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2352 # Number of floating rename lookups system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73744941 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56192967 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108162580 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37173372 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46311356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7909478 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331723465 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 311412241 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185399 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53269773 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 92543278 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2170 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 133966907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.324546 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.724461 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 73687058 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55957632 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108146065 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37162932 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46284047 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7887005 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331670931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2660 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 311367761 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 187011 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53218475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 92468498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 133058866 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.340075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.723307 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 27936582 20.85% 20.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17254518 12.88% 33.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25564521 19.08% 52.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31166509 23.26% 76.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17676068 13.19% 89.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9033591 6.74% 96.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3761456 2.81% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1501105 1.12% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 72557 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 27262165 20.49% 20.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17087897 12.84% 33.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25427949 19.11% 52.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31141299 23.40% 75.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17714013 13.31% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9070422 6.82% 95.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3766330 2.83% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1516401 1.14% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 72390 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 133966907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 133058866 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 23354 1.11% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1960413 92.78% 93.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 129107 6.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 23137 1.10% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1959411 92.81% 93.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 128735 6.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177196652 56.90% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177167866 56.90% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 103 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued @@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99714062 32.02% 88.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34470040 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99703270 32.02% 88.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34465151 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 311412241 # Type of FU issued -system.cpu.iq.rate 2.310575 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2112874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006785 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 759088710 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 385026224 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 308270248 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 952 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1427 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 313493303 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 441 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52569930 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 311367761 # Type of FU issued +system.cpu.iq.rate 2.339503 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2111283 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006781 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 758091805 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 384922588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 308230879 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 877 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1235 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 313447268 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 405 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52556752 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17383192 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 98849 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32443 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5733621 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17366677 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 97430 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32398 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5723181 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3316 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3845 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3328 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3855 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7297966 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 891871 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 89086 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331726081 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 45756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108162580 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37173372 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 224 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 43423 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32443 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 615219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578970 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1194189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 309448819 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 99181332 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1963422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7290835 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 316808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29284 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331673591 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 45940 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108146065 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37162932 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 478 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 230 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5075 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32398 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 615271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 578255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1193526 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 309404440 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 99168969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1963321 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 133262430 # number of memory reference insts executed -system.cpu.iew.exec_branches 31528913 # Number of branches executed -system.cpu.iew.exec_stores 34081098 # Number of stores executed -system.cpu.iew.exec_rate 2.296008 # Inst execution rate -system.cpu.iew.wb_sent 308818207 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 308270562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227514859 # num instructions producing a value -system.cpu.iew.wb_consumers 467066838 # num instructions consuming a value +system.cpu.iew.exec_refs 133248637 # number of memory reference insts executed +system.cpu.iew.exec_branches 31530009 # Number of branches executed +system.cpu.iew.exec_stores 34079668 # Number of stores executed +system.cpu.iew.exec_rate 2.324751 # Inst execution rate +system.cpu.iew.wb_sent 308773966 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 308231167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227547609 # num instructions producing a value +system.cpu.iew.wb_consumers 467201547 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.287265 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.487114 # average fanout of values written-back +system.cpu.iew.wb_rate 2.315935 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.487044 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 53537768 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 53483171 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1088027 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126668941 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.196217 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674380 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1087573 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125768031 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.211949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.676987 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 46359304 36.60% 36.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24201081 19.11% 55.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16849760 13.30% 69.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12619079 9.96% 78.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3360251 2.65% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3556898 2.81% 84.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2707142 2.14% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1157073 0.91% 87.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15858353 12.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45423361 36.12% 36.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24208560 19.25% 55.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16905668 13.44% 68.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12615481 10.03% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3337463 2.65% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3557456 2.83% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2707212 2.15% 86.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156864 0.92% 87.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15855966 12.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126668941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125768031 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988582 # Number of instructions committed system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,69 +284,69 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15858353 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15855966 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 442540875 # The number of ROB reads -system.cpu.rob.rob_writes 670767297 # The number of ROB writes -system.cpu.timesIdled 23993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 810010 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 441587755 # The number of ROB reads +system.cpu.rob.rob_writes 670650798 # The number of ROB writes +system.cpu.timesIdled 771 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32575 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988582 # Number of Instructions Simulated system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated -system.cpu.cpi 0.853080 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.853080 # CPI: Total CPI of All Threads -system.cpu.ipc 1.172223 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.172223 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 705322547 # number of integer regfile reads -system.cpu.int_regfile_writes 373244258 # number of integer regfile writes -system.cpu.fp_regfile_reads 361 # number of floating regfile reads -system.cpu.fp_regfile_writes 193 # number of floating regfile writes -system.cpu.misc_regfile_reads 197929880 # number of misc regfile reads -system.cpu.icache.replacements 97 # number of replacements -system.cpu.icache.tagsinuse 846.508998 # Cycle average of tags in use -system.cpu.icache.total_refs 27277404 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24956.453797 # Average number of references to valid blocks. +system.cpu.cpi 0.842412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.842412 # CPI: Total CPI of All Threads +system.cpu.ipc 1.187068 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.187068 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 705256530 # number of integer regfile reads +system.cpu.int_regfile_writes 373197329 # number of integer regfile writes +system.cpu.fp_regfile_reads 323 # number of floating regfile reads +system.cpu.fp_regfile_writes 179 # number of floating regfile writes +system.cpu.misc_regfile_reads 197910485 # number of misc regfile reads +system.cpu.icache.replacements 89 # number of replacements +system.cpu.icache.tagsinuse 845.508761 # Cycle average of tags in use +system.cpu.icache.total_refs 27274550 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1079 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25277.618165 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 846.508998 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.413334 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.413334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27277408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27277408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27277408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27277408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27277408 # number of overall hits -system.cpu.icache.overall_hits::total 27277408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1413 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1413 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1413 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1413 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1413 # number of overall misses -system.cpu.icache.overall_misses::total 1413 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50201500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50201500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50201500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50201500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50201500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50201500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27278821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27278821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27278821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27278821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35528.308563 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35528.308563 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 845.508761 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412846 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412846 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27274554 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27274554 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27274554 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27274554 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27274554 # number of overall hits +system.cpu.icache.overall_hits::total 27274554 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1401 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1401 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1401 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1401 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1401 # number of overall misses +system.cpu.icache.overall_misses::total 1401 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49669500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49669500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49669500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49669500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49669500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49669500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27275955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27275955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27275955 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27275955 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27275955 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27275955 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35452.890792 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35452.890792 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35452.890792 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35452.890792 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1098 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1098 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1098 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1098 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1098 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1098 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38330500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38330500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38330500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38330500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 317 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 317 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 317 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 317 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 317 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 317 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1084 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1084 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1084 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1084 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1084 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1084 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37853000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37853000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37853000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37853000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37853000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37853000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34919.741697 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34919.741697 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34919.741697 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34919.741697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34919.741697 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34919.741697 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072128 # number of replacements -system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use -system.cpu.dcache.total_refs 75623437 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076224 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.423544 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2072094 # number of replacements +system.cpu.dcache.tagsinuse 4072.411380 # Cycle average of tags in use +system.cpu.dcache.total_refs 75633227 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076190 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.428856 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 22601159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.706371 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994313 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994313 # 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number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2377027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2377027 # number of overall misses -system.cpu.dcache.overall_misses::total 2377027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13818885500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13818885500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502429791 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1502429791 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15321315291 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15321315291 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15321315291 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15321315291 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46560697 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46560697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4072.411380 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994241 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994241 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 44275835 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 44275835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31357376 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31357376 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 75633211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 75633211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 75633211 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13589072788 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13589072788 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13589072788 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13589072788 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46561466 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46561466 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 78000448 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 78000448 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049205 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002736 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030475 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6031.763813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 6445.578990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 6445.578990 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 78001217 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 78001217 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 78001217 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 78001217 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049088 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049088 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.030359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030359 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030359 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5336.794084 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5336.794084 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16887.778914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16887.778914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 5738.614171 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 5738.614171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 5738.614171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 5738.614171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,140 +451,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1878988 # number of writebacks -system.cpu.dcache.writebacks::total 1878988 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 296886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 296886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3910 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3910 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300796 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300796 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300796 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300796 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994133 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994133 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82098 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076231 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076231 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076231 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5596231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5596231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158803791 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158803791 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6755035291 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6755035291 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # 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number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291809 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994116 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994116 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82081 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82081 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076197 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076197 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4625699000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4625699000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1142906788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1142906788 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5768605788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5768605788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5768605788 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5768605788 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042828 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042828 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2806.348172 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026617 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026617 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2319.673981 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2319.673981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13924.133332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13924.133332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2778.448186 # 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Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30627 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 131.487315 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 12943.264838 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 249.609803 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 5801.290058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.394997 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007617 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.177041 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.579656 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1963548 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994008 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2064779 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2064779 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82223 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82223 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1094 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076226 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077320 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1094 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076226 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82184 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82184 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076192 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077271 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076192 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077271 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000293 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358999 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.029391 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.029391 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352782 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352782 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014246 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014246 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.322097 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34218.803419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34250.151240 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.158245 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.158245 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34093.111662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34093.111662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 14024 # number of writebacks -system.cpu.l2cache.writebacks::total 14024 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31537 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 313 # number of writebacks +system.cpu.l2cache.writebacks::total 313 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1653 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29518 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29518 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 59973 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 61055 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 59973 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 61055 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33615000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 944732500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 978347500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29578 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29578 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33172000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18151500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51323500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915134000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915134000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33615000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1859866500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1893481500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33615000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015807 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 898797500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 898797500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33172000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 916949000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 950121000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33172000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 916949000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 950121000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029391 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029391 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31059.925094 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31028.205128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31048.699335 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.500121 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.500121 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 96f41a3e2..4b59eaf01 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index d95343c19..894e40d36 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:22:27 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:17:22 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 370010840000 because target called exit() +Exiting @ tick 368062166000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index bcdb996d9..896f57262 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.370011 # Number of seconds simulated -sim_ticks 370010840000 # Number of ticks simulated -final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.368062 # Number of seconds simulated +sim_ticks 368062166000 # Number of ticks simulated +final_tick 368062166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 564351 # Simulator instruction rate (inst/s) -host_op_rate 993732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1321716509 # Simulator tick rate (ticks/s) -host_mem_usage 360832 # Number of bytes of host memory used -host_seconds 279.95 # Real time elapsed on the host +host_inst_rate 915530 # Simulator instruction rate (inst/s) +host_op_rate 1612102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2132888263 # Simulator tick rate (ticks/s) +host_mem_usage 362628 # Number of bytes of host memory used +host_seconds 172.57 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory -system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory +system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory -system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory +system.physmem.bytes_written::total 14528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory -system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory -system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5106963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5247461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5106963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5286933 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 740021680 # number of cpu cycles simulated +system.cpu.numCycles 736124332 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988583 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219139 # nu system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 740021680 # Number of busy cycles +system.cpu.num_busy_cycles 736124332 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.896557 # Cycle average of tags in use system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 665.896557 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.559519 # Cycle average of tags in use system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.559519 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995254 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995254 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27464486000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27464486000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2704691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2704691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30169177000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30169177000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30169177000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30169177000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14596.842313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks -system.cpu.dcache.writebacks::total 1437080 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks +system.cpu.dcache.writebacks::total 2061794 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386362500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386362500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968688500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23968688500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968688500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23968688500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.727544 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.727544 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49212 # number of replacements -system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1081 # number of replacements +system.cpu.l2cache.tagsinuse 19721.209952 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits -system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits +system.cpu.l2cache.occ_blocks::writebacks 19369.116114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 209.759091 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 142.334747 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.591099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006401 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.601844 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses -system.cpu.l2cache.overall_misses::total 76575 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses +system.cpu.l2cache.overall_misses::total 30178 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses @@ -294,27 +294,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 808 system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks -system.cpu.l2cache.writebacks::total 29460 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks +system.cpu.l2cache.writebacks::total 227 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 52f83ef58..5e05f1621 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..374965c0a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 90b73e8ee..5a5a625da 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:38:42 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:45:14 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233057542500 because target called exit() +Exiting @ tick 210036334500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index b64f135f3..43f7dedd0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233058 # Number of seconds simulated -sim_ticks 233057542500 # Number of ticks simulated -final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.210036 # Number of seconds simulated +sim_ticks 210036334500 # Number of ticks simulated +final_tick 210036334500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102553 # Simulator instruction rate (inst/s) -host_op_rate 115527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46960535 # Simulator tick rate (ticks/s) -host_mem_usage 237172 # Number of bytes of host memory used -host_seconds 4962.84 # Real time elapsed on the host -sim_insts 508954936 # Number of instructions simulated -sim_ops 573341497 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory -system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory -system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory -system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory -system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 177312 # Simulator instruction rate (inst/s) +host_op_rate 199743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73173320 # Simulator tick rate (ticks/s) +host_mem_usage 239056 # Number of bytes of host memory used +host_seconds 2870.40 # Real time elapsed on the host +sim_insts 508955243 # Number of instructions simulated +sim_ops 573341803 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10020416 # Number of bytes read from this memory +system.physmem.bytes_read::total 10239552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6682560 # Number of bytes written to this memory +system.physmem.bytes_written::total 6682560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159993 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104415 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104415 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1043324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47708012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48751336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31816209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31816209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31816209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47708012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80567546 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,321 +77,321 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466115086 # number of cpu cycles simulated +system.cpu.numCycles 420072670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits +system.cpu.BPredUnit.lookups 180017694 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142687184 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7729396 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 94339767 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87293897 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12415335 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116774 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 120382403 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 794428106 # Number of instructions fetch has processed +system.cpu.fetch.Branches 180017694 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99709232 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 176656328 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 41234330 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 91071148 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 358 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 113830042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2509224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 418577617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.181681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.031530 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 241934136 57.80% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14312407 3.42% 61.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20602450 4.92% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22857238 5.46% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20951996 5.01% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13135363 3.14% 79.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13267726 3.17% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12107850 2.89% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59408451 14.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 418577617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.428539 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.891168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 132749600 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85626153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165029361 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4780262 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 30392241 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26480489 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 870641905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 30392241 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 142822329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6003622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66002577 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159587024 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13769824 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 815822534 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 858 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2869085 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7326440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 963278183 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3562240909 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3562236360 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4549 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 291077860 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5318003 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5317721 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 67395600 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 171954811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74969765 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27370082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14835909 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 760687253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6768595 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 671184661 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1545827 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 191893024 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 487573539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3047459 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 418577617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.603489 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725201 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 157194444 37.55% 37.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77339610 18.48% 56.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 70514833 16.85% 72.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51630225 12.33% 85.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31661646 7.56% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16095104 3.85% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9461042 2.26% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3409350 0.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1271363 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 418577617 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 446687 4.54% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6731982 68.43% 72.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2658540 27.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450868550 67.18% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385779 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 220 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154882510 23.08% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65047599 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued -system.cpu.iq.rate 1.503321 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 671184661 # Type of FU issued +system.cpu.iq.rate 1.597782 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9837209 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1772329499 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 960150284 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650772394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 476 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 681021630 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8403522 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45181752 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43422 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 806126 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17365784 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19422 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 30392241 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2471437 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 146089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 773606723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1210159 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 171954811 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74969765 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5279868 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 67842 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6482 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 806126 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4698240 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6420025 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11118265 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 661214126 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151365480 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9970535 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8780498 # number of nop insts executed -system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed -system.cpu.iew.exec_branches 141958281 # Number of branches executed -system.cpu.iew.exec_stores 63961675 # Number of stores executed -system.cpu.iew.exec_rate 1.462860 # Inst execution rate -system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 381765084 # num instructions producing a value -system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value +system.cpu.iew.exec_nop 6150875 # number of nop insts executed +system.cpu.iew.exec_refs 214988835 # number of memory reference insts executed +system.cpu.iew.exec_branches 137027568 # Number of branches executed +system.cpu.iew.exec_stores 63623355 # Number of stores executed +system.cpu.iew.exec_rate 1.574047 # Inst execution rate +system.cpu.iew.wb_sent 655977937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650772410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374973371 # num instructions producing a value +system.cpu.iew.wb_consumers 645025945 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back +system.cpu.iew.wb_rate 1.549190 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.581331 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510299127 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685687 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 198937259 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9897053 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 388185377 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480441 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.160280 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 174260848 44.89% 44.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102323189 26.36% 71.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36274304 9.34% 80.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18231179 4.70% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17368323 4.47% 89.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8208578 2.11% 91.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6882791 1.77% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3781895 0.97% 94.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20854270 5.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298820 # Number of instructions committed -system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 388185377 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299127 # Number of instructions committed +system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376915 # Number of memory references committed -system.cpu.commit.loads 126772997 # Number of loads committed +system.cpu.commit.refs 184377040 # Number of memory references committed +system.cpu.commit.loads 126773059 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192182 # Number of branches committed +system.cpu.commit.branches 120192244 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701465 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20854270 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1226921226 # The number of ROB reads -system.cpu.rob.rob_writes 1682775882 # The number of ROB writes -system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954936 # Number of Instructions Simulated -system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated -system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads -system.cpu.int_regfile_writes 777373809 # number of integer regfile writes +system.cpu.rob.rob_reads 1140946915 # The number of ROB reads +system.cpu.rob.rob_writes 1577778936 # The number of ROB writes +system.cpu.timesIdled 55077 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1495053 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955243 # Number of Instructions Simulated +system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated +system.cpu.cpi 0.825363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825363 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211589 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211589 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3085576786 # number of integer regfile reads +system.cpu.int_regfile_writes 758984284 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes -system.cpu.icache.replacements 16105 # number of replacements -system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use -system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1021861854 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes +system.cpu.icache.replacements 15860 # number of replacements +system.cpu.icache.tagsinuse 1099.172767 # Cycle average of tags in use +system.cpu.icache.total_refs 113810641 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17722 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6421.997574 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits -system.cpu.icache.overall_hits::total 126840329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses -system.cpu.icache.overall_misses::total 19891 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1099.172767 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.536705 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.536705 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113810641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113810641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113810641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113810641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113810641 # number of overall hits +system.cpu.icache.overall_hits::total 113810641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19401 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19401 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19401 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19401 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19401 # number of overall misses +system.cpu.icache.overall_misses::total 19401 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 248637000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 248637000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 248637000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 248637000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 248637000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 248637000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113830042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113830042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113830042 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12815.679604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12815.679604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12815.679604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12815.679604 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,260 +400,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # 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number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1436571 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2698082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2698082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2698082 # number of overall misses +system.cpu.dcache.overall_misses::total 2698082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11193325500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11193325500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24423594500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24423594500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 430500 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232952 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2232952 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 192769177 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192769177 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192769177 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192769177 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026486 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013996 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013996 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8872.951167 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8872.951167 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17001.313893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17001.313893 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9784.090909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9784.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13200.829330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13200.829330 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,69 +656,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 171061 # number of writebacks -system.cpu.l2cache.writebacks::total 171061 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 104415 # number of writebacks +system.cpu.l2cache.writebacks::total 104415 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 27 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53134 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 56558 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103436 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 103436 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 156570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159994 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 156570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159994 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106506000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1650725500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1757231500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3207102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3207102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106506000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4857828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4964334000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106506000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4857828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4964334000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.116279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.116279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296367 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296367 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131387 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132293 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131387 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132293 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.724299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31067.216848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.548075 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31005.670173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31005.670173 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index f2f9dd654..b319ef658 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 5bc6f404c..5020b6420 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:42:59 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:45:54 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 290498972000 because target called exit() +Exiting @ tick 290498967000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index eec1b9eb1..d3328d763 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.290499 # Number of seconds simulated -sim_ticks 290498972000 # Number of ticks simulated -final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 290498967000 # Number of ticks simulated +final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2223848 # Simulator instruction rate (inst/s) -host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1275264214 # Simulator tick rate (ticks/s) -host_mem_usage 224628 # Number of bytes of host memory used -host_seconds 227.80 # Real time elapsed on the host -sim_insts 506581615 # Number of instructions simulated -sim_ops 570968176 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory +host_inst_rate 3026360 # Simulator instruction rate (inst/s) +host_op_rate 3411010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1735464120 # Simulator tick rate (ticks/s) +host_mem_usage 228428 # Number of bytes of host memory used +host_seconds 167.39 # Real time elapsed on the host +sim_insts 506581607 # Number of instructions simulated +sim_ops 570968167 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory -system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory +system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 580997945 # number of cpu cycles simulated +system.cpu.numCycles 580997935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506581615 # Number of instructions committed -system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.committedInsts 506581607 # Number of instructions committed +system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890035 # number of memory refs -system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_mem_refs 182890034 # number of memory refs +system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 580997945 # Number of busy cycles +system.cpu.num_busy_cycles 580997935 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 036427da7..6a9499ace 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index ec9ed9cd5..64f0d2855 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:46:58 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:48:24 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 722234364000 because target called exit() +Exiting @ tick 718982756000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 85dc67786..8439efddd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.722234 # Number of seconds simulated -sim_ticks 722234364000 # Number of ticks simulated -final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.718983 # Number of seconds simulated +sim_ticks 718982756000 # Number of ticks simulated +final_tick 718982756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114772 # Simulator instruction rate (inst/s) -host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1594352181 # Simulator tick rate (ticks/s) -host_mem_usage 233804 # Number of bytes of host memory used -host_seconds 453.00 # Real time elapsed on the host -sim_insts 504986861 # Number of instructions simulated -sim_ops 569034848 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory -system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory -system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory -system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1474104 # Simulator instruction rate (inst/s) +host_op_rate 1661066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2098778351 # Simulator tick rate (ticks/s) +host_mem_usage 237008 # Number of bytes of host memory used +host_seconds 342.57 # Real time elapsed on the host +sim_insts 504986853 # Number of instructions simulated +sim_ops 569034839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory +system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory +system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 248084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13441034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13689118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9144475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9144475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9144475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13441034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 22833594 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1444468728 # number of cpu cycles simulated +system.cpu.numCycles 1437965512 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504986861 # Number of instructions committed -system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.committedInsts 504986853 # Number of instructions committed +system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890035 # number of memory refs -system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_mem_refs 182890034 # number of memory refs +system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1444468728 # Number of busy cycles +system.cpu.num_busy_cycles 1437965512 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use -system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 983.088334 # Cycle average of tags in use +system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits -system.cpu.icache.overall_hits::total 516599864 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 983.088334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.480024 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.480024 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits +system.cpu.icache.overall_hits::total 516599855 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 278348000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 278348000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 278348000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 278348000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 278348000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 278348000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24160.055551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24160.055551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243785000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243785000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4065.352134 # Cycle average of tags in use +system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits +system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11889977000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.352134 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992518 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992518 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits -system.cpu.dcache.overall_hits::total 176840705 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits +system.cpu.dcache.overall_hits::total 176840704 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12960486000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12960486000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9326282000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9326282000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22286768000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22286768000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22286768000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22286768000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19568.369277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19568.369277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks -system.cpu.dcache.writebacks::total 1025440 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks +system.cpu.dcache.writebacks::total 1061444 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10612512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10612512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257502000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257502000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870014000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18870014000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870014000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18870014000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 212089 # number of replacements -system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits -system.cpu.l2cache.overall_hits::total 919235 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses -system.cpu.l2cache.overall_misses::total 231204 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3465.461521 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.708728 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007528 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.105757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.822014 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 252959 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8734 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 987920 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 996654 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8734 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 987920 # number of overall hits +system.cpu.l2cache.overall_hits::total 996654 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2787 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 47697 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 50484 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 103301 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 103301 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2787 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 150998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153785 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses +system.cpu.l2cache.overall_misses::total 153785 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2625168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371652000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371652000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144924000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7851896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7996820000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144924000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7851896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7996820000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1061444 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1061444 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 1150439 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.132580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.133675 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks -system.cpu.l2cache.writebacks::total 172302 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 102730 # number of writebacks +system.cpu.l2cache.writebacks::total 102730 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2787 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 47697 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 50484 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 103301 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 150998 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153785 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1907880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111480000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6039920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6151400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6039920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6151400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.289960 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.289960 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 5b8f0efef..1f04164bf 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 29af0d223..2f3625356 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:27:18 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:20:26 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +********************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +****** 58924 words stored in 3784810 bytes @@ -19,8 +32,6 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's @@ -64,19 +75,9 @@ Echoing of input sentence turned on. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 459937575500 because target called exit() +Exiting @ tick 455813328500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4a5cfadf8..46181ad4f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459938 # Number of seconds simulated -sim_ticks 459937575500 # Number of ticks simulated -final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455813 # Number of seconds simulated +sim_ticks 455813328500 # Number of ticks simulated +final_tick 455813328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70939 # Simulator instruction rate (inst/s) -host_op_rate 131174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39458742 # Simulator tick rate (ticks/s) -host_mem_usage 264492 # Number of bytes of host memory used -host_seconds 11656.16 # Real time elapsed on the host +host_inst_rate 110548 # Simulator instruction rate (inst/s) +host_op_rate 204416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60939389 # Simulator tick rate (ticks/s) +host_mem_usage 266636 # Number of bytes of host memory used +host_seconds 7479.78 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory -system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory -system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory -system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 220672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27604992 # Number of bytes read from this memory +system.physmem.bytes_read::total 27825664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20791296 # Number of bytes written to this memory +system.physmem.bytes_written::total 20791296 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431328 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324864 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324864 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 484128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60562055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61046183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 484128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 484128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45613620 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45613620 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45613620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 484128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60562055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106659803 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 919875152 # number of cpu cycles simulated +system.cpu.numCycles 911626658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits +system.cpu.BPredUnit.lookups 225614318 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225614318 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14285714 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160541063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155870604 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191565109 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263061891 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225614318 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155870604 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392054994 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98473885 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 230412581 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 273577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183478574 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3652581 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 898267437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.606318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.392133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 510675527 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25992328 2.89% 59.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29100733 3.24% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30303597 3.37% 66.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19641643 2.19% 68.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25615145 2.85% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32617140 3.63% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30849776 3.43% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193471548 21.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6492696430 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6491823905 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 898267437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247485 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.385503 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252696641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 182534450 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 330171612 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 48929478 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83935256 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290198570 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 83935256 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289311592 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40780199 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340344585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 143881166 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240282902 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2186 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22940117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103602655 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11705 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2887046684 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6493129070 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6492267923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 861147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 893969200 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1261 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1244 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 345524950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540216674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217364695 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 216116185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63552241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143188368 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61311 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846653007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1596963 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612532438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1230905034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60758 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 898267437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.806511 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 246353790 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 156616035 17.37% 44.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 150729220 16.72% 61.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 147768173 16.39% 77.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 244119309 27.18% 27.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 156083539 17.38% 44.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150204364 16.72% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147125554 16.38% 77.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103909500 11.57% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58948328 6.56% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27781277 3.09% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9047752 1.01% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1047814 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 898267437 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2653512 16.69% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10033753 63.11% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3212720 20.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2721869 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219400147 66.03% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued @@ -195,86 +195,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447092064 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177438927 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued -system.cpu.iq.rate 2.007566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846653007 # Type of FU issued +system.cpu.iq.rate 2.025668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15899985 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008610 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4609062574 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755747075 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806129295 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7825 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 296338 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859828366 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2757 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 167960734 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156114514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 428176 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 272950 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68204770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6724 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83935256 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705090 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1089193 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143249679 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2772043 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540216674 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217364955 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5665 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 876205 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14852 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 272950 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10085276 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5239623 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15324899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818663600 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438639718 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27989407 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed -system.cpu.iew.exec_branches 170830738 # Number of branches executed -system.cpu.iew.exec_stores 171857297 # Number of stores executed -system.cpu.iew.exec_rate 1.977147 # Inst execution rate -system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1379770015 # num instructions producing a value -system.cpu.iew.wb_consumers 2939115295 # num instructions consuming a value +system.cpu.iew.exec_refs 610490535 # number of memory reference insts executed +system.cpu.iew.exec_branches 170808194 # Number of branches executed +system.cpu.iew.exec_stores 171850817 # Number of stores executed +system.cpu.iew.exec_rate 1.994965 # Inst execution rate +system.cpu.iew.wb_sent 1813450071 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806129580 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379661197 # num instructions producing a value +system.cpu.iew.wb_consumers 2939711936 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back +system.cpu.iew.wb_rate 1.981216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.469319 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614283465 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14312346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 814332181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.877598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.330573 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 298731075 36.68% 36.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 203556250 25.00% 61.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73630894 9.04% 70.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 94876671 11.65% 82.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30957165 3.80% 86.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28752943 3.53% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16466236 2.02% 91.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11737662 1.44% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55623285 6.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 814332181 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,68 +285,69 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55623285 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2905110180 # The number of ROB reads -system.cpu.rob.rob_writes 4370460169 # The number of ROB writes -system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2901981117 # The number of ROB reads +system.cpu.rob.rob_writes 4370596606 # The number of ROB writes +system.cpu.timesIdled 304669 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13359221 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004380471 # number of integer regfile reads -system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes -system.cpu.fp_regfile_reads 262 # number of floating regfile reads -system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads -system.cpu.icache.replacements 10653 # number of replacements -system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use -system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks. +system.cpu.cpi 1.102493 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102493 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907035 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907035 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004133317 # number of integer regfile reads +system.cpu.int_regfile_writes 2286262019 # number of integer regfile writes +system.cpu.fp_regfile_reads 284 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001892809 # number of misc regfile reads +system.cpu.icache.replacements 5521 # number of replacements +system.cpu.icache.tagsinuse 1042.048866 # Cycle average of tags in use +system.cpu.icache.total_refs 183243707 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25660.790786 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits -system.cpu.icache.overall_hits::total 183258482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses -system.cpu.icache.overall_misses::total 224389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1042.048866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508813 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508813 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183260633 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183260633 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183260633 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183260633 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183260633 # number of overall hits +system.cpu.icache.overall_hits::total 183260633 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 217941 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 217941 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 217941 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 217941 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 217941 # number of overall misses +system.cpu.icache.overall_misses::total 217941 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1509664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1509664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1509664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1509664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1509664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1509664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183478574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183478574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183478574 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183478574 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183478574 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183478574 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6926.938942 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6926.938942 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6926.938942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6926.938942 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,94 +358,94 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 8 # number of writebacks system.cpu.icache.writebacks::total 8 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1622 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1622 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1622 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 823021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 823021000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 823021000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001179 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001179 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001179 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3804.663483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3804.663483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527239 # number of replacements -system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use -system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2527069 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 269038413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 269038413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418198614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418198614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418198614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418198614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009821 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009821 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006625 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12787.034255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12787.034255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19076.087638 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19076.087638 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14498.936331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14498.936331 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,144 +454,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks -system.cpu.dcache.writebacks::total 2229248 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9153 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 324864 # number of writebacks +system.cpu.l2cache.writebacks::total 324864 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3448 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222182 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225630 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 207844 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 207844 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209183 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209183 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434813 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3448 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431365 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 434813 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107086500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6894107000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7001193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6443438500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6443438500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6484873000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6484873000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107086500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13378980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13486066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107086500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13378980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13486066500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127690 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271263 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271263 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171310 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171310 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.569606 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31029.097767 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31029.532864 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.320702 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.320702 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.956101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.956101 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 7ea92ba3c..2db6fca67 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 1909314a2..0422a99cd 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:45:58 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:33:45 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1658729604000 because target called exit() +Exiting @ tick 1652422044000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index b3396b2cb..246184477 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.658730 # Number of seconds simulated -sim_ticks 1658729604000 # Number of ticks simulated -final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.652422 # Number of seconds simulated +sim_ticks 1652422044000 # Number of ticks simulated +final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 615589 # Simulator instruction rate (inst/s) -host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1234881669 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1343.23 # Real time elapsed on the host +host_inst_rate 1001096 # Simulator instruction rate (inst/s) +host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2000579398 # Simulator tick rate (ticks/s) +host_mem_usage 231692 # Number of bytes of host memory used +host_seconds 825.97 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory -system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory -system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory +system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory +system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory +system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory +system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numCycles 3304844088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877145 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262345 # nu system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.num_busy_cycles 3304844088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks -system.cpu.dcache.writebacks::total 2223170 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks +system.cpu.dcache.writebacks::total 2297113 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,68 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 568906 # number of replacements -system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 543011 # 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number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses -system.cpu.l2cache.overall_misses::total 579609 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17241952000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30139674000 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641958 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.244073 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.888463 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits +system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses +system.cpu.l2cache.overall_misses::total 429429 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses @@ -296,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,41 +326,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks -system.cpu.l2cache.writebacks::total 411709 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks +system.cpu.l2cache.writebacks::total 323570 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 217560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 429429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index 673c743ff..fd38a6ce1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 051061431..8d1e02107 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:58 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:46 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141175129500 because target called exit() +Exiting @ tick 141174877500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 06e2fa444..63af08cbf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.141175 # Number of seconds simulated -sim_ticks 141175129500 # Number of ticks simulated -final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 141174877500 # Number of ticks simulated +final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110841 # Simulator instruction rate (inst/s) -host_op_rate 110841 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39251086 # Simulator tick rate (ticks/s) -host_mem_usage 221340 # Number of bytes of host memory used -host_seconds 3596.72 # Real time elapsed on the host +host_inst_rate 165783 # Simulator instruction rate (inst/s) +host_op_rate 165783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58706881 # Simulator tick rate (ticks/s) +host_mem_usage 225068 # Number of bytes of host memory used +host_seconds 2404.74 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 468608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282350260 # number of cpu cycles simulated +system.cpu.numCycles 282349756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups @@ -93,9 +93,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. -system.cpu.activity 95.227214 # Percentage of cycles cpu is active +system.cpu.activity 95.227384 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,34 +107,34 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits @@ -213,12 +213,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits @@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -261,14 +261,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,63 +311,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use +system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 725 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7322 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7328 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7322 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) @@ -382,27 +382,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3901 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,49 +412,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4177 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7322 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 7162e6c66..11313b921 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 0c5d1935a..0f3bb3f65 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:46:44 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:52 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80257421500 because target called exit() +Exiting @ tick 80278875500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 55fb5b70f..c7cbab894 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080257 # Number of seconds simulated -sim_ticks 80257421500 # Number of ticks simulated -final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080279 # Number of seconds simulated +sim_ticks 80278875500 # Number of ticks simulated +final_tick 80278875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183656 # Simulator instruction rate (inst/s) -host_op_rate 183656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39245952 # Simulator tick rate (ticks/s) -host_mem_usage 222148 # Number of bytes of host memory used -host_seconds 2044.99 # Real time elapsed on the host +host_inst_rate 279986 # Simulator instruction rate (inst/s) +host_op_rate 279986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59846889 # Simulator tick rate (ticks/s) +host_mem_usage 226092 # Number of bytes of host memory used +host_seconds 1341.40 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory -system.physmem.bytes_read::total 478528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222720 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3480 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2775070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3187344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5962414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2775070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2775070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2775070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3187344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5962414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 477888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7467 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2772734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3180114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5952849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2772734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2772734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2772734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3180114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5952849 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103368572 # DTB read hits -system.cpu.dtb.read_misses 88956 # DTB read misses +system.cpu.dtb.read_hits 103395556 # DTB read hits +system.cpu.dtb.read_misses 88623 # DTB read misses system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103457528 # DTB read accesses -system.cpu.dtb.write_hits 78975243 # DTB write hits -system.cpu.dtb.write_misses 1664 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78976907 # DTB write accesses -system.cpu.dtb.data_hits 182343815 # DTB hits -system.cpu.dtb.data_misses 90620 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 182434435 # DTB accesses -system.cpu.itb.fetch_hits 52487109 # ITB hits -system.cpu.itb.fetch_misses 461 # ITB misses +system.cpu.dtb.read_accesses 103484179 # DTB read accesses +system.cpu.dtb.write_hits 78997481 # DTB write hits +system.cpu.dtb.write_misses 1612 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78999093 # DTB write accesses +system.cpu.dtb.data_hits 182393037 # DTB hits +system.cpu.dtb.data_misses 90235 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 182483272 # DTB accesses +system.cpu.itb.fetch_hits 52516361 # ITB hits +system.cpu.itb.fetch_misses 462 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52487570 # ITB accesses +system.cpu.itb.fetch_accesses 52516823 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,112 +60,112 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160514845 # number of cpu cycles simulated +system.cpu.numCycles 160557753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits +system.cpu.BPredUnit.lookups 52050833 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30287644 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1599078 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 29208422 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24276895 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9365187 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1064 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53558689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462299559 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52050833 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33642082 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81488062 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7763373 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19255908 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52516361 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 627395 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160436815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314292 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78948753 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4374209 2.73% 51.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7277181 4.54% 56.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5613096 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12419261 7.74% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8092340 5.04% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5700245 3.55% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1902354 1.19% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36109376 22.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 160436815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324188 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879335 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59087459 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14718957 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76680946 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3827925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6121528 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9736129 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4314 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 456834278 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12214 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6121528 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62371527 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4787903 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 394179 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77332259 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9429419 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451139499 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 22898 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7804449 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 294872724 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593300368 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314087845 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279212523 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35340395 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38267 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 351 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27285549 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106973750 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81779740 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8912420 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6388901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416336746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 335 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407746724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1079648 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40502587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19766308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 120 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160436815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.541479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32040952 19.97% 19.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26498917 16.52% 36.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25974021 16.19% 52.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24801870 15.46% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21558468 13.44% 81.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15451278 9.63% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8686999 5.41% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4112581 2.56% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1311729 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160436815 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35223 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74176 0.62% 0.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4373 0.04% 0.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3034 0.03% 0.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1856115 15.64% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1782113 15.01% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available @@ -187,19 +187,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5098643 42.95% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3017744 25.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158007223 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126531 0.52% 39.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33463416 8.21% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7846184 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2836368 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16562414 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1592681 0.39% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105279650 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79998676 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued -system.cpu.iq.rate 2.539806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407746724 # Type of FU issued +system.cpu.iq.rate 2.539564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11871421 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647615644 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269617595 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237690414 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341265688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187272317 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162935841 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245304560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174280004 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14820631 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12219263 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125114 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50286 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259011 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260829 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6121528 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2498871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 366274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441262786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203691 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106973750 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81779740 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 335 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50286 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1245920 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 565907 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1811827 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403241961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103532839 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4504763 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24943165 # number of nop insts executed -system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed -system.cpu.iew.exec_branches 47188511 # Number of branches executed -system.cpu.iew.exec_stores 78976945 # Number of stores executed -system.cpu.iew.exec_rate 2.511684 # Inst execution rate -system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195210305 # num instructions producing a value -system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value +system.cpu.iew.exec_nop 24925705 # number of nop insts executed +system.cpu.iew.exec_refs 182531964 # number of memory reference insts executed +system.cpu.iew.exec_branches 47208062 # Number of branches executed +system.cpu.iew.exec_stores 78999125 # Number of stores executed +system.cpu.iew.exec_rate 2.511507 # Inst execution rate +system.cpu.iew.wb_sent 401471936 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400626255 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195236823 # num instructions producing a value +system.cpu.iew.wb_consumers 273330928 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back +system.cpu.iew.wb_rate 2.495216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42637745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1594835 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154315287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.583442 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.967476 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58825621 38.12% 38.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23339762 15.12% 53.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13270606 8.60% 61.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11657566 7.55% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8455456 5.48% 74.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5496217 3.56% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5141868 3.33% 81.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3368734 2.18% 83.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24759457 16.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154315287 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24759457 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 570775521 # The number of ROB reads -system.cpu.rob.rob_writes 888672842 # The number of ROB writes -system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 570855181 # The number of ROB reads +system.cpu.rob.rob_writes 888739971 # The number of ROB writes +system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 120938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads -system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402674037 # number of integer regfile reads -system.cpu.int_regfile_writes 172514061 # number of integer regfile writes -system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads -system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes +system.cpu.cpi 0.427499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427499 # CPI: Total CPI of All Threads +system.cpu.ipc 2.339188 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.339188 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402766119 # number of integer regfile reads +system.cpu.int_regfile_writes 172550874 # number of integer regfile writes +system.cpu.fp_regfile_reads 158333530 # number of floating regfile reads +system.cpu.fp_regfile_writes 105213831 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2234 # number of replacements -system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use -system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks. +system.cpu.icache.replacements 2221 # number of replacements +system.cpu.icache.tagsinuse 1836.833971 # Cycle average of tags in use +system.cpu.icache.total_refs 52510942 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4151 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12650.190797 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits -system.cpu.icache.overall_hits::total 52481453 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses -system.cpu.icache.overall_misses::total 5656 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31012.199434 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31012.199434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31012.199434 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1836.833971 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.896892 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.896892 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52510942 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52510942 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52510942 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52510942 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52510942 # number of overall hits +system.cpu.icache.overall_hits::total 52510942 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5419 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5419 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5419 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5419 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5419 # number of overall misses +system.cpu.icache.overall_misses::total 5419 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170335500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170335500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170335500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170335500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170335500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170335500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52516361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52516361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52516361 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52516361 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52516361 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52516361 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31433.013471 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31433.013471 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31433.013471 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31433.013471 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,82 +383,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1268 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1268 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1268 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1268 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1268 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1268 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4151 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4151 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4151 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4151 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4151 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4151 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125070500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125070500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125070500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125070500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125070500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125070500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30055.955812 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30130.209588 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30130.209588 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30130.209588 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30130.209588 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30130.209588 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30130.209588 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 804 # number of replacements -system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use -system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks. +system.cpu.dcache.replacements 783 # number of replacements +system.cpu.dcache.tagsinuse 3297.903545 # Cycle average of tags in use +system.cpu.dcache.total_refs 161813696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4184 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38674.401530 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.800145 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.805127 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.805127 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88308332 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88308332 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501218 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 16 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161809550 # number of overall hits -system.cpu.dcache.overall_hits::total 161809550 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1689 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1689 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19511 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21200 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21200 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21200 # number of overall misses -system.cpu.dcache.overall_misses::total 21200 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56020500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56020500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 567228500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 567228500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 623249000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 623249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 623249000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 623249000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88310021 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.903545 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.805152 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.805152 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88312425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88312425 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88314078 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161834807 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161834807 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161834807 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161834807 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses @@ -467,148 +467,148 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33167.850799 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29072.241300 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29398.537736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29398.537736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33398.971567 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33398.971567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29267.816800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29267.816800 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29591.012353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29591.012353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682 # number of writebacks -system.cpu.dcache.writebacks::total 682 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16309 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16309 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1003 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1003 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4205 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4205 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4205 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4205 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31754500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31754500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144878500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 144878500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 661 # number of writebacks +system.cpu.dcache.writebacks::total 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 664 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16281 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16945 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16945 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16945 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16945 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4184 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4184 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4184 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4184 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113198500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113198500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144517500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144517500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144517500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144517500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31659.521436 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35329.169269 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31667.340748 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31667.340748 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35429.890454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35429.890454 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 11 # number of replacements -system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use -system.cpu.l2cache.total_refs 903 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4887 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.184776 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 4030.550390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 892 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4871 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183125 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 374.716771 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3001.811767 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 662.773402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011435 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091608 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020226 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 684 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 133 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34647.105852 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34516.918550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34516.918550 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 372.758053 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2998.208675 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 659.583662 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011376 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.091498 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020129 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123003 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 673 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 804 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 661 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 661 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 64 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 64 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 673 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 868 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 673 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits +system.cpu.l2cache.overall_hits::total 868 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3478 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4336 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3131 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3478 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7467 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3478 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses +system.cpu.l2cache.overall_misses::total 7467 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 119555000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 149223000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108422000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108422000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 119555000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 138090000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 257645000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 119555000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 138090000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 257645000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4151 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 989 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5140 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 661 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 661 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4151 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4184 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8335 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4151 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4184 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8335 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.837870 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.843580 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979969 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.979969 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.837870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.953394 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.895861 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.837870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.953394 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.895861 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34374.640598 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34578.088578 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34414.898524 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34628.553178 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34628.553178 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34374.640598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34617.698671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34504.486407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34374.640598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34617.698671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34504.486407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,50 +617,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 870 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3127 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3127 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7477 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3480 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108421000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135761000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98470000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98470000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108421000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125810000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.841881 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.976577 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.893416 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.893416 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31209.425287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31490.246242 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4336 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7467 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3478 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7467 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26958500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135278500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98537000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98537000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125495500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 233815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125495500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 233815500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.843580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.895861 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.895861 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31144.335825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.163170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31198.916052 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31471.414883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31471.414883 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index b05b7d5ce..b7b2de2d4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 39e268f04..535f9cae3 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:47:31 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:12:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.566667 -Exiting @ tick 567343170000 because target called exit() +Exiting @ tick 567342918000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f16fecb77..049129481 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567343 # Number of seconds simulated -sim_ticks 567343170000 # Number of ticks simulated -final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567342918000 # Number of ticks simulated +final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1377504 # Simulator instruction rate (inst/s) -host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1960338494 # Simulator tick rate (ticks/s) -host_mem_usage 220796 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host +host_inst_rate 2055836 # Simulator instruction rate (inst/s) +host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2925676505 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 193.92 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 459520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 459136 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134686340 # number of cpu cycles simulated +system.cpu.numCycles 1134685836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,16 +79,16 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134686340 # Number of busy cycles +system.cpu.num_busy_cycles 1134685836 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits @@ -161,12 +161,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,63 +251,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use -system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use +system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 645 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 651 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7180 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7174 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -322,16 +322,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3673 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -352,38 +352,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index b166901dc..27728d570 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index fd4ba336e..e6faeb5f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:54:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:48:53 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.070000 -Exiting @ tick 71774859500 because target called exit() +Exiting @ tick 71244143500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 154ddb0a7..e982040ed 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071775 # Number of seconds simulated -sim_ticks 71774859500 # Number of ticks simulated -final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071244 # Number of seconds simulated +sim_ticks 71244143500 # Number of ticks simulated +final_tick 71244143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120484 # Simulator instruction rate (inst/s) -host_op_rate 154032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31671128 # Simulator tick rate (ticks/s) -host_mem_usage 240520 # Number of bytes of host memory used -host_seconds 2266.26 # Real time elapsed on the host -sim_insts 273048474 # Number of instructions simulated -sim_ops 349076199 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory -system.physmem.bytes_read::total 472896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 187993 # Simulator instruction rate (inst/s) +host_op_rate 240337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49051248 # Simulator tick rate (ticks/s) +host_mem_usage 243200 # Number of bytes of host memory used +host_seconds 1452.44 # Real time elapsed on the host +sim_insts 273048446 # Number of instructions simulated +sim_ops 349076170 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 195520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273792 # Number of bytes read from this memory +system.physmem.bytes_read::total 469312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4278 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7333 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2744366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3843011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6587377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2744366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2744366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2744366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3843011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6587377 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 143549720 # number of cpu cycles simulated +system.cpu.numCycles 142488288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits +system.cpu.BPredUnit.lookups 36834655 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22011992 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2128141 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 21111775 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17921807 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7049660 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9673 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 41170537 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 330092344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36834655 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24971467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 74065448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8653461 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20659218 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3712 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39589827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 662584 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142371733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.982100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68999572 48.46% 48.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7443838 5.23% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5890912 4.14% 57.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6290109 4.42% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5018667 3.53% 65.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4222472 2.97% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3222890 2.26% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4319860 3.03% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36963413 25.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142371733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258510 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316628 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47920905 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15947714 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69670851 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2428941 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6403322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7589257 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69989 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 416841547 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 209997 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6403322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53735690 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1551358 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 361067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 66219864 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14100432 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 406248964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1649610 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10115480 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 773 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 445265070 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2397426033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1310073571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1087352462 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584954 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60680116 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19505 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19502 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35831958 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105842469 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93258241 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4666139 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5699487 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 393022623 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378573033 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1364119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42964941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 113697743 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5987 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142371733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.659046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.045030 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29238426 20.54% 20.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20559915 14.44% 34.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20888687 14.67% 49.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18235605 12.81% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24142271 16.96% 79.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16046767 11.27% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9027765 6.34% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3298956 2.32% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 933341 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142371733 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9050 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4700 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,203 +189,203 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48305 0.27% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7771 0.04% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 390 0.00% 0.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 194430 1.08% 1.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4896 0.03% 1.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241266 1.34% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9438470 52.59% 55.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7998776 44.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128705433 34.00% 34.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2178586 0.58% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 5 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6839771 1.81% 36.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8697995 2.30% 38.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3451888 0.91% 39.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605167 0.42% 40.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21254253 5.61% 45.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7183697 1.90% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136969 1.89% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102677998 27.12% 76.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88665985 23.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued -system.cpu.iq.rate 2.643039 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378573033 # Type of FU issued +system.cpu.iq.rate 2.656871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17948057 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 668230837 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 303627249 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252741444 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250599138 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132404625 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118730959 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267327381 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129193709 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10789214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11191376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112013 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13979 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10880305 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7857 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6403322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34047 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1473 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 393102382 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1223414 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105842469 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93258241 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19294 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13979 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1692038 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 558009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2250047 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373788733 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101161202 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4784300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 50388 # number of nop insts executed -system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed -system.cpu.iew.exec_branches 32491949 # Number of branches executed -system.cpu.iew.exec_stores 87417217 # Number of stores executed -system.cpu.iew.exec_rate 2.608698 # Inst execution rate -system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back -system.cpu.iew.wb_producers 185166823 # num instructions producing a value -system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value +system.cpu.iew.exec_nop 49294 # number of nop insts executed +system.cpu.iew.exec_refs 188542226 # number of memory reference insts executed +system.cpu.iew.exec_branches 32415827 # Number of branches executed +system.cpu.iew.exec_stores 87381024 # Number of stores executed +system.cpu.iew.exec_rate 2.623294 # Inst execution rate +system.cpu.iew.wb_sent 372275263 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371472403 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184833323 # num instructions producing a value +system.cpu.iew.wb_consumers 367854017 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back +system.cpu.iew.wb_rate 2.607038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502464 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273049058 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349076782 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 44025608 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24478 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2100754 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135968412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.567337 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.653672 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38641813 28.42% 28.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29058445 21.37% 49.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13534255 9.95% 59.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11222379 8.25% 68.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13789944 10.14% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7224545 5.31% 83.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4032637 2.97% 86.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3910785 2.88% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14553609 10.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049086 # Number of instructions committed -system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135968412 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049058 # Number of instructions committed +system.cpu.commit.committedOps 349076782 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029038 # Number of memory references committed -system.cpu.commit.loads 94651098 # Number of loads committed +system.cpu.commit.refs 177029029 # Number of memory references committed +system.cpu.commit.loads 94651093 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30523993 # Number of branches committed +system.cpu.commit.branches 30523988 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594011 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593987 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14553609 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 516653738 # The number of ROB reads -system.cpu.rob.rob_writes 795243409 # The number of ROB writes -system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048474 # Number of Instructions Simulated -system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated -system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads -system.cpu.int_regfile_writes 236964047 # number of integer regfile writes -system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads -system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes -system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14190 # number of replacements -system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use -system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 514514670 # The number of ROB reads +system.cpu.rob.rob_writes 792612920 # The number of ROB writes +system.cpu.timesIdled 2826 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 116555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048446 # Number of Instructions Simulated +system.cpu.committedOps 349076170 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048446 # Number of Instructions Simulated +system.cpu.cpi 0.521843 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521843 # CPI: Total CPI of All Threads +system.cpu.ipc 1.916287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.916287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1784947411 # number of integer regfile reads +system.cpu.int_regfile_writes 236351279 # number of integer regfile writes +system.cpu.fp_regfile_reads 189697788 # number of floating regfile reads +system.cpu.fp_regfile_writes 133433924 # number of floating regfile writes +system.cpu.misc_regfile_reads 991980863 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426471 # number of misc regfile writes +system.cpu.icache.replacements 14091 # number of replacements +system.cpu.icache.tagsinuse 1855.139503 # Cycle average of tags in use +system.cpu.icache.total_refs 39573076 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15985 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2475.638161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits -system.cpu.icache.overall_hits::total 39934285 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses -system.cpu.icache.overall_misses::total 17014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1855.139503 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.905830 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.905830 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39573076 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39573076 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39573076 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39573076 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39573076 # number of overall hits +system.cpu.icache.overall_hits::total 39573076 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16751 # number of overall misses +system.cpu.icache.overall_misses::total 16751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 205369500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 205369500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 205369500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 205369500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 205369500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 205369500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39589827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39589827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39589827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39589827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39589827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39589827 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000423 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000423 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000423 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000423 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000423 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12260.133723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12260.133723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12260.133723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12260.133723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,252 +394,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 765 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 765 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 765 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 765 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 765 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15986 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15986 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15986 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15986 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15986 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15986 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 137471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 137471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137471000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 137471000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8599.462029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8599.462029 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1427 # number of replacements -system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use -system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1422 # number of replacements +system.cpu.dcache.tagsinuse 3120.754345 # Cycle average of tags in use +system.cpu.dcache.total_refs 172231049 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4634 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37166.821105 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits -system.cpu.dcache.overall_hits::total 172474184 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3120.754345 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.761903 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.761903 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90171406 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90171406 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82032842 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82032842 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13547 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13253 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13253 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172204248 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172204248 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172204248 # number of overall hits +system.cpu.dcache.overall_hits::total 172204248 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3698 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3698 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19818 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19818 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses -system.cpu.dcache.overall_misses::total 23126 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 23516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23516 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23516 # number of overall misses +system.cpu.dcache.overall_misses::total 23516 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 118442000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 118442000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 655611500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 655611500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 774053500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 774053500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 774053500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 774053500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90175104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90175104 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13253 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13253 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172227764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172227764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172227764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172227764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000242 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000242 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32028.664143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32028.664143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33081.617721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33081.617721 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32916.035890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32916.035890 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks -system.cpu.dcache.writebacks::total 1038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks +system.cpu.dcache.writebacks::total 1041 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1882 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1882 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16999 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16999 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 18881 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 18881 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 18881 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 18881 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2819 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2819 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4635 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4635 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4635 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4635 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 55172500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 55172500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100155500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 100155500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 155328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 155328000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30381.332599 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30381.332599 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35528.733593 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35528.733593 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 69 # number of replacements -system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3993.397220 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13323 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5445 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.446832 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2851.587465 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 802.133324 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011614 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.087024 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024479 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123117 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13268 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13285 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits -system.cpu.l2cache.overall_hits::total 13285 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3122 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4629 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 22 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 22 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3122 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4326 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3122 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4326 # number of overall misses -system.cpu.l2cache.overall_misses::total 7448 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106982000 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133897000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 228844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94947500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133897000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 228844500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813671 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254565 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993617 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993617 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355643 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355643 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31079.378069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31287.601626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.208122 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31304.960742 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31304.960742 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 796e4e4fa..8af4db376 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 80d4c141d..0dc5c6cdd 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:01:26 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:54:17 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.210000 -Exiting @ tick 212344048000 because target called exit() +Exiting @ tick 212344043000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 1239fc01a..4a3f2e632 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.212344 # Number of seconds simulated -sim_ticks 212344048000 # Number of ticks simulated -final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 212344043000 # Number of ticks simulated +final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1586428 # Simulator instruction rate (inst/s) -host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1233780581 # Simulator tick rate (ticks/s) -host_mem_usage 229108 # Number of bytes of host memory used -host_seconds 172.11 # Real time elapsed on the host -sim_insts 273037671 # Number of instructions simulated -sim_ops 349065408 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory +host_inst_rate 2237295 # Simulator instruction rate (inst/s) +host_op_rate 2860273 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1739965936 # Simulator tick rate (ticks/s) +host_mem_usage 232696 # Number of bytes of host memory used +host_seconds 122.04 # Real time elapsed on the host +sim_insts 273037663 # Number of instructions simulated +sim_ops 349065399 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424688097 # number of cpu cycles simulated +system.cpu.numCycles 424688087 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037671 # Number of instructions committed -system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses +system.cpu.committedInsts 273037663 # Number of instructions committed +system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584926 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls +system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written +system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024357 # number of memory refs -system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024356 # number of memory refs +system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 424688097 # Number of busy cycles +system.cpu.num_busy_cycles 424688087 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index f88d3c19b..68ac46334 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 02e894db6..ddb90c634 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:04:29 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:56:30 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.520000 -Exiting @ tick 525854475000 because target called exit() +Exiting @ tick 525854423000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index ce6e736cb..bbdf06ba7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.525854 # Number of seconds simulated -sim_ticks 525854475000 # Number of ticks simulated -final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 525854423000 # Number of ticks simulated +final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 697015 # Simulator instruction rate (inst/s) -host_op_rate 891108 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1343878935 # Simulator tick rate (ticks/s) -host_mem_usage 238268 # Number of bytes of host memory used -host_seconds 391.30 # Real time elapsed on the host -sim_insts 272739291 # Number of instructions simulated -sim_ops 348687131 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory +host_inst_rate 1009014 # Simulator instruction rate (inst/s) +host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1945426950 # Simulator tick rate (ticks/s) +host_mem_usage 241152 # Number of bytes of host memory used +host_seconds 270.30 # Real time elapsed on the host +sim_insts 272739283 # Number of instructions simulated +sim_ops 348687122 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory -system.physmem.bytes_read::total 437312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 437248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,73 +70,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051708950 # number of cpu cycles simulated +system.cpu.numCycles 1051708846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739291 # Number of instructions committed -system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses +system.cpu.committedInsts 272739283 # Number of instructions committed +system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584925 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls +system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written +system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024357 # number of memory refs -system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024356 # number of memory refs +system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051708950 # Number of busy cycles +system.cpu.num_busy_cycles 1051708846 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use -system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use +system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits -system.cpu.icache.overall_hits::total 348644756 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits +system.cpu.icache.overall_hits::total 348644747 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,46 +151,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use +system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits -system.cpu.dcache.overall_hits::total 176619810 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits +system.cpu.dcache.overall_hits::total 176619809 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 240058000 system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -278,54 +278,54 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 48 # number of replacements -system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13248 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -339,17 +339,17 @@ system.cpu.l2cache.demand_accesses::total 20081 # n system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.231100 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.340272 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.340272 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -369,39 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.340272 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.340272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index c3e480ad3..1dc93d52f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 9147626b9..fbf7fa994 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:24:16 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:12:31 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 645508416000 because target called exit() +Exiting @ tick 639588907000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index b1e9e0d80..f93e57319 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.645508 # Number of seconds simulated -sim_ticks 645508416000 # Number of ticks simulated -final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.639589 # Number of seconds simulated +sim_ticks 639588907000 # Number of ticks simulated +final_tick 639588907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137005 # Simulator instruction rate (inst/s) -host_op_rate 137005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48511232 # Simulator tick rate (ticks/s) -host_mem_usage 222596 # Number of bytes of host memory used -host_seconds 13306.37 # Real time elapsed on the host +host_inst_rate 210347 # Simulator instruction rate (inst/s) +host_op_rate 210347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73797228 # Simulator tick rate (ticks/s) +host_mem_usage 229080 # Number of bytes of host memory used +host_seconds 8666.84 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 192384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94602752 # Number of bytes read from this memory -system.physmem.bytes_read::total 94795136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 192384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 191360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94464192 # Number of bytes read from this memory +system.physmem.bytes_read::total 94655552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 191360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 191360 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1478168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1481174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476003 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1478993 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 298035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146555412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146853447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6632713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 298035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146555412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153486160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 299192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 147695169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 147994362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 299192 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 299192 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6694100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6694100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6694100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 299192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 147695169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 154688461 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526109598 # DTB read hits -system.cpu.dtb.read_misses 625347 # DTB read misses +system.cpu.dtb.read_hits 525683715 # DTB read hits +system.cpu.dtb.read_misses 628896 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526734945 # DTB read accesses -system.cpu.dtb.write_hits 292167921 # DTB write hits -system.cpu.dtb.write_misses 53946 # DTB write misses +system.cpu.dtb.read_accesses 526312611 # DTB read accesses +system.cpu.dtb.write_hits 287304184 # DTB write hits +system.cpu.dtb.write_misses 53890 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292221867 # DTB write accesses -system.cpu.dtb.data_hits 818277519 # DTB hits -system.cpu.dtb.data_misses 679293 # DTB misses +system.cpu.dtb.write_accesses 287358074 # DTB write accesses +system.cpu.dtb.data_hits 812987899 # DTB hits +system.cpu.dtb.data_misses 682786 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 818956812 # DTB accesses -system.cpu.itb.fetch_hits 402604817 # ITB hits -system.cpu.itb.fetch_misses 847 # ITB misses +system.cpu.dtb.data_accesses 813670685 # DTB accesses +system.cpu.itb.fetch_hits 398461552 # ITB hits +system.cpu.itb.fetch_misses 1212 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402605664 # ITB accesses +system.cpu.itb.fetch_accesses 398462764 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1291016833 # number of cpu cycles simulated +system.cpu.numCycles 1279177815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 393573728 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 256530657 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27586844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 324820294 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 261991971 # Number of BTB hits +system.cpu.BPredUnit.lookups 391601012 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 255930815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27097905 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 318432805 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 256621752 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57786471 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 8197 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421176645 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3321335108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 393573728 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319778442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638257970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162812665 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 96711303 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 59044090 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7305 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 417206849 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3304631660 # Number of instructions fetch has processed +system.cpu.fetch.Branches 391601012 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315665842 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 634205086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158948618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 96266839 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8593 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402604817 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9565592 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1290891849 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.572900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.136734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 11708 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 398461552 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8907646 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1279053519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.145594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 652633879 50.56% 50.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59721794 4.63% 55.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43804545 3.39% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72624877 5.63% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127484332 9.88% 74.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46855386 3.63% 77.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41599950 3.22% 80.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7021053 0.54% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 239146033 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 644848433 50.42% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60073670 4.70% 55.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44904383 3.51% 58.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71013010 5.55% 64.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 124436565 9.73% 73.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45667903 3.57% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41114141 3.21% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7023739 0.55% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239971675 18.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1290891849 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.304856 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.572651 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 453921580 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79454568 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 612779431 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10011349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134724921 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33550717 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12520 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3227083732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46784 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134724921 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 483920973 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32457268 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 591448832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48313875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3136668879 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 8064 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42516144 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2086288186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3648925200 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3531562512 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117362688 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1279053519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.306135 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.583403 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 450209575 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79019815 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 608453320 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10020119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131350690 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33655569 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12307 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3205531959 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46810 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131350690 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 478839352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32033074 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25872 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 588505763 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48298768 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3118953725 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 371 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 8014 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42155636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2071308237 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3619384197 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3501684594 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117699603 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 701319116 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4353 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 267 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142890931 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 736649308 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 360329563 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68950696 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9282518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642275746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 205 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2193056773 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17946555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 819111732 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 708893207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1290891849 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.698869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804017 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 686339167 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4232 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 140575935 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 734762265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 354500186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67932920 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9138793 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2625466002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2176735177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17945547 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802302909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 703322223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1279053519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.701833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.797036 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470876253 36.48% 36.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 218068463 16.89% 53.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252707156 19.58% 72.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121463164 9.41% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106308054 8.24% 90.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77452334 6.00% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21076392 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17287996 1.34% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5652037 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 464081398 36.28% 36.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 216592353 16.93% 53.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 250622762 19.59% 72.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121884176 9.53% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104836053 8.20% 90.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77987896 6.10% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21570720 1.69% 98.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17288528 1.35% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4189633 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1290891849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1279053519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141130 3.16% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24070571 66.71% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10868345 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1140853 3.19% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24076891 67.30% 70.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10558644 29.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1255545244 57.25% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29218260 1.33% 58.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589185884 26.87% 86.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303628594 13.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1247700404 57.32% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16695 0.00% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 28729941 1.32% 58.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254693 0.38% 59.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586556392 26.95% 86.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 298269645 13.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2193056773 # Type of FU issued -system.cpu.iq.rate 1.698705 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36080046 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016452 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5576578817 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3377639693 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2021595592 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154453179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 83821528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75359015 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2150081181 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79052886 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67169273 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2176735177 # Type of FU issued +system.cpu.iq.rate 1.701667 # Inst issue rate +system.cpu.iq.fu_busy_cnt 35776388 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016436 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5534048167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3341408955 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2010160977 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 152197641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 86432816 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74384435 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2134737053 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77771760 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67976479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 225579282 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76359 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 149534667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 223692239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13198 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75649 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 143705290 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4417 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 29 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134724921 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3817892 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203271 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3000868514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2715875 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 736649308 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 360329563 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 205 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131040 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76359 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27588382 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31906 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27620288 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2101232365 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526735105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 91824408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131350690 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3811054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 200562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2981894857 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2707472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 734762265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 354500186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131033 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4888 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75649 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27118847 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27150805 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2088347607 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526312810 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 88387570 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358592563 # number of nop insts executed -system.cpu.iew.exec_refs 818957488 # number of memory reference insts executed -system.cpu.iew.exec_branches 281208298 # Number of branches executed -system.cpu.iew.exec_stores 292222383 # Number of stores executed -system.cpu.iew.exec_rate 1.627579 # Inst execution rate -system.cpu.iew.wb_sent 2099740429 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2096954607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185148628 # num instructions producing a value -system.cpu.iew.wb_consumers 1754528061 # num instructions consuming a value +system.cpu.iew.exec_nop 356428733 # number of nop insts executed +system.cpu.iew.exec_refs 813671363 # number of memory reference insts executed +system.cpu.iew.exec_branches 280895404 # Number of branches executed +system.cpu.iew.exec_stores 287358553 # Number of stores executed +system.cpu.iew.exec_rate 1.632570 # Inst execution rate +system.cpu.iew.wb_sent 2087345359 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2084545412 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181911333 # num instructions producing a value +system.cpu.iew.wb_consumers 1746825923 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.624266 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675480 # average fanout of values written-back +system.cpu.iew.wb_rate 1.629598 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.676605 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 975184756 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 956239558 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27574586 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1156166928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.737628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495396 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27085717 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147702829 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.750442 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 540094894 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227413285 19.67% 66.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119190896 10.31% 76.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56737431 4.91% 81.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50997203 4.41% 86.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24159454 2.09% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18394192 1.59% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15607584 1.35% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103571989 8.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 533397723 46.48% 46.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226612269 19.74% 66.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 118218768 10.30% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56744377 4.94% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50032490 4.36% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24020067 2.09% 87.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19167450 1.67% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15607807 1.36% 90.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103901878 9.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1156166928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1147702829 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103571989 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103901878 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4031130889 # The number of ROB reads -system.cpu.rob.rob_writes 6103072592 # The number of ROB writes -system.cpu.timesIdled 3457 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 124984 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4003391703 # The number of ROB reads +system.cpu.rob.rob_writes 6061807983 # The number of ROB writes +system.cpu.timesIdled 3462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 124296 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.708166 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.708166 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412099 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.412099 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2678294251 # number of integer regfile reads -system.cpu.int_regfile_writes 1517633044 # number of integer regfile writes -system.cpu.fp_regfile_reads 81926245 # number of floating regfile reads -system.cpu.fp_regfile_writes 54028832 # number of floating regfile writes +system.cpu.cpi 0.701672 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.701672 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.425168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2657999656 # number of integer regfile reads +system.cpu.int_regfile_writes 1510398630 # number of integer regfile writes +system.cpu.fp_regfile_reads 80463471 # number of floating regfile reads +system.cpu.fp_regfile_writes 53540440 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8444 # number of replacements -system.cpu.icache.tagsinuse 1673.037469 # Cycle average of tags in use -system.cpu.icache.total_refs 402593289 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10171 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39582.468685 # Average number of references to valid blocks. +system.cpu.icache.replacements 8417 # number of replacements +system.cpu.icache.tagsinuse 1667.677082 # Cycle average of tags in use +system.cpu.icache.total_refs 398450176 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39306.518299 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1673.037469 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.816913 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.816913 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402593289 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402593289 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402593289 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402593289 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402593289 # number of overall hits -system.cpu.icache.overall_hits::total 402593289 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11528 # number of overall misses -system.cpu.icache.overall_misses::total 11528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 191663000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 191663000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 191663000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 191663000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 191663000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 191663000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402604817 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402604817 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402604817 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402604817 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1667.677082 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.814295 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.814295 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 398450176 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398450176 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398450176 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398450176 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398450176 # number of overall hits +system.cpu.icache.overall_hits::total 398450176 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11376 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11376 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11376 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11376 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11376 # number of overall misses +system.cpu.icache.overall_misses::total 11376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188382000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188382000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188382000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188382000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188382000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188382000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398461552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398461552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398461552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398461552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398461552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398461552 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16625.867453 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16625.867453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16625.867453 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16559.599156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16559.599156 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16559.599156 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16559.599156 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,304 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1356 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1356 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1356 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1356 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1356 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10172 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10172 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10172 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10172 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10172 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123488000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 123488000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123488000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 123488000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1238 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1238 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1238 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1238 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1238 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1238 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10138 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10138 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10138 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10138 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10138 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10138 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122862500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122862500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12139.992135 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12119.007694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12119.007694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528059 # number of replacements -system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use -system.cpu.dcache.total_refs 667250429 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532155 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.497994 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267049000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.059846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999770 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999770 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457007415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457007415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210242966 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210242966 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667250381 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667250381 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667250381 # number of overall hits -system.cpu.dcache.overall_hits::total 667250381 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928420 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 551930 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 551930 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.replacements 1527982 # number of replacements +system.cpu.dcache.tagsinuse 4095.064488 # Cycle average of tags in use +system.cpu.dcache.total_refs 666017344 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532078 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 434.715037 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 264095000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.064488 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999772 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999772 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 455774339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 455774339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210242956 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210242956 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666017295 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666017295 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666017295 # number of overall hits +system.cpu.dcache.overall_hits::total 666017295 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928410 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928410 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 551940 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 551940 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 2480350 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2480350 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2480350 # number of overall misses system.cpu.dcache.overall_misses::total 2480350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71491683500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71491683500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20877271991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20877271991 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 58500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 58500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92368955491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92368955491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92368955491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92368955491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 458935835 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 458935835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71225328000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71225328000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20805642991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20805642991 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92030970991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92030970991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92030970991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92030970991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 457702749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 457702749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 50 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 50 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669730731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669730731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 668497645 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 668497645 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 668497645 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 668497645 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004213 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003704 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003704 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37072.672706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.941679 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37240.290883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37240.290883 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.020000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.020000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003710 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003710 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003710 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003710 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36934.743130 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36934.743130 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37695.479565 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37695.479565 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37104.026041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37104.026041 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6187.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6156.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107245 # number of writebacks -system.cpu.dcache.writebacks::total 107245 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467870 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467870 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 480326 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 109405 # number of writebacks +system.cpu.dcache.writebacks::total 109405 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467937 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467937 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480335 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 480335 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 948196 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 948196 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 948196 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 948196 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460550 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460550 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71604 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71604 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532154 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532154 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49990545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49990545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492898500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492898500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52483443500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 948272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 948272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 948272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 948272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460473 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460473 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532078 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532078 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532078 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532078 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49721165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49721165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2483602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52204767500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52204767500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52204767500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52204767500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003191 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34227.205505 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34815.073180 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002292 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002292 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.563302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.563302 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34684.756651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34684.756651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480784 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2990 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409150 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1412140 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2990 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476003 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1478993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2990 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476003 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1478993 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92982500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43684578500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43777561000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2138150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2138150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45822729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45915711500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92982500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45822729000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45915711500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.294930 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933636 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933636 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294930 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.959005 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.959005 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.826087 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.658908 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.864645 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31982.865391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31982.865391 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.826087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31045.146250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31045.252750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.826087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31045.146250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31045.252750 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index f9460f41a..acb7a4c77 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 508096573..85893d278 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:40:02 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:15:06 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2813467842000 because target called exit() +Exiting @ tick 2813377164000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c273e38a0..9b3a7daff 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813468 # Number of seconds simulated -sim_ticks 2813467842000 # Number of ticks simulated -final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.813377 # Number of seconds simulated +sim_ticks 2813377164000 # Number of ticks simulated +final_tick 2813377164000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1483350 # Simulator instruction rate (inst/s) -host_op_rate 1483350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2077343480 # Simulator tick rate (ticks/s) -host_mem_usage 220820 # Number of bytes of host memory used -host_seconds 1354.36 # Real time elapsed on the host +host_inst_rate 2127881 # Simulator instruction rate (inst/s) +host_op_rate 2127880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2979874149 # Simulator tick rate (ticks/s) +host_mem_usage 227924 # Number of bytes of host memory used +host_seconds 944.13 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94556032 # Number of bytes read from this memory -system.physmem.bytes_read::total 94708160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94417856 # Number of bytes read from this memory +system.physmem.bytes_read::total 94569984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1477438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475279 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33608357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33662428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33608357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35184206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33560326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33614400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1521827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1521827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1521827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33560326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35136226 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5626935684 # number of cpu cycles simulated +system.cpu.numCycles 5626754328 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,16 +86,16 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5626935684 # Number of busy cycles +system.cpu.num_busy_cycles 5626754328 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.423352 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.423269 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1478.423352 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits @@ -168,12 +168,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.204600 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.204626 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4095.204600 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79658418000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79658418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79567740000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3815994000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3815994000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83474412000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83474412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83474412000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83474412000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83383734000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83383734000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83383734000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83383734000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54628.209454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.024227 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54553.304787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54553.304787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54494.043698 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107612 # number of writebacks -system.cpu.dcache.writebacks::total 107612 # number of writebacks +system.cpu.dcache.writebacks::writebacks 109771 # number of writebacks +system.cpu.dcache.writebacks::total 109771 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75283842000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75283842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78883980000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78883980000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78883980000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78883980000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51628.209454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1479797 # number of replacements -system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1479705 # number of replacements +system.cpu.l2cache.tagsinuse 32704.227313 # Cycle average of tags in use +system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3081.828747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.409968 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28814.603011 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.094050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001020 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.879352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974421 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3254.893374 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.487953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29415.845986 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998054 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 47627 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 55846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107612 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107612 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109771 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109771 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 8219 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 52706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 60925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 54865 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 63084 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 8219 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 52706 # number of overall hits -system.cpu.l2cache.overall_hits::total 60925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 54865 # number of overall hits +system.cpu.l2cache.overall_hits::total 63084 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1410565 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1412942 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1408406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1410783 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1477438 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479815 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1477656 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2377 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1477438 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479815 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475279 # number of overall misses +system.cpu.l2cache.overall_misses::total 1477656 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73349380000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73472984000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73237112000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73360716000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 123604000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76826776000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76950380000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 76714508000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76838112000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76826776000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76950380000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76714508000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76838112000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107612 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109771 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses @@ -329,16 +329,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 10596 system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.961978 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965858 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.960508 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.960457 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964144 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.959056 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.960457 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964144 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.959056 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -361,38 +361,38 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks system.cpu.l2cache.writebacks::total 66898 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1408406 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1410783 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1477656 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1477656 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56336240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56431320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59011160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59106240000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59011160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59106240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961978 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965858 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960508 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.960457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.959056 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.960457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.959056 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index d9870188c..420e789e0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 0c5c10637..95a99c94b 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:06:13 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:01:11 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 735495062500 because target called exit() +Exiting @ tick 734755023500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 81f1da57a..abd280906 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.735495 # Number of seconds simulated -sim_ticks 735495062500 # Number of ticks simulated -final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.734755 # Number of seconds simulated +sim_ticks 734755023500 # Number of ticks simulated +final_tick 734755023500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76677 # Simulator instruction rate (inst/s) -host_op_rate 104424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40737062 # Simulator tick rate (ticks/s) -host_mem_usage 237976 # Number of bytes of host memory used -host_seconds 18054.69 # Real time elapsed on the host -sim_insts 1384379503 # Number of instructions simulated -sim_ops 1885334256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory -system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory +host_inst_rate 119232 # Simulator instruction rate (inst/s) +host_op_rate 162378 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63282228 # Simulator tick rate (ticks/s) +host_mem_usage 243808 # Number of bytes of host memory used +host_seconds 11610.76 # Real time elapsed on the host +sim_insts 1384372850 # Number of instructions simulated +sim_ops 1885327602 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94510912 # Number of bytes read from this memory +system.physmem.bytes_read::total 94716672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476733 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479948 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 280039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128629147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128909186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5757478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5757478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5757478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128629147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134666664 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1470990126 # number of cpu cycles simulated +system.cpu.numCycles 1469510048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits +system.cpu.BPredUnit.lookups 526868038 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 401113446 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 36046358 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 383398262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 286508671 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed -system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 60655682 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2811201 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 448614021 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2626557864 # Number of instructions fetch has processed +system.cpu.fetch.Branches 526868038 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 347164353 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716084096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 226374824 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 100079168 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20420 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 419610687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12785505 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1449541071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.542405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 733526710 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55834579 3.85% 54.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113825896 7.85% 62.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72745123 5.02% 67.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 84690661 5.84% 73.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54721422 3.78% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 33849353 2.34% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 34645380 2.39% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 265701947 18.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1449541071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.358533 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.787370 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 497288026 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79567524 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 676485575 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11475102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 184724844 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 81162192 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 16785 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3548614330 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 38542 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 184724844 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 535414239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 30600962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 541148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 648147088 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50112790 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3434293747 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4398993 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40741019 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1775 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3359442434 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16257634697 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15596931258 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 660703439 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993143706 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1366298728 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50062 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45371 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 137456980 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1058714008 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 577829073 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 31866160 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36849262 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3203795171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52627 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2727879490 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26513766 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1318072615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3048733772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 30791 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1449541071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.881892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914534 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 528205619 36.44% 36.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200385301 13.82% 50.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 218048243 15.04% 65.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179845166 12.41% 77.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155269867 10.71% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101678601 7.01% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47766137 3.30% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10944186 0.76% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7397951 0.51% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1449541071 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1786371 1.87% 1.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23899 0.03% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56927453 59.70% 61.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36612005 38.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1265692730 46.40% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11246210 0.41% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876504 0.25% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503517 0.20% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 65 0.00% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23431459 0.86% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 901624360 33.05% 81.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512129355 18.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued -system.cpu.iq.rate 1.847748 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2727879490 # Type of FU issued +system.cpu.iq.rate 1.856319 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95349728 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034954 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6892702222 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4416661768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2501406306 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 134461323 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 105324073 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59997583 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2754068673 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 69160545 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71273395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 427326375 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 261567 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1134338 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 300833324 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 184724844 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16014821 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1979639 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3203920541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4008843 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1058714008 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 577829073 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42582 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1976809 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 591 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1134338 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 37198169 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9007131 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46205300 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2628771663 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 847609803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99107827 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 77258 # number of nop insts executed -system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed -system.cpu.iew.exec_branches 359930496 # Number of branches executed -system.cpu.iew.exec_stores 479754342 # Number of stores executed -system.cpu.iew.exec_rate 1.779747 # Inst execution rate -system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1472840060 # num instructions producing a value -system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value +system.cpu.iew.exec_nop 72743 # number of nop insts executed +system.cpu.iew.exec_refs 1330077082 # number of memory reference insts executed +system.cpu.iew.exec_branches 361648549 # Number of branches executed +system.cpu.iew.exec_stores 482467279 # Number of stores executed +system.cpu.iew.exec_rate 1.788876 # Inst execution rate +system.cpu.iew.wb_sent 2589616129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2561403889 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1477403496 # num instructions producing a value +system.cpu.iew.wb_consumers 2764851406 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back +system.cpu.iew.wb_rate 1.743033 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534352 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384383866 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885338618 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1318582287 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 21836 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41567877 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1264816229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.490603 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207767 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 584481462 46.21% 46.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 317753060 25.12% 71.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 101743247 8.04% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79200545 6.26% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52876697 4.18% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23864362 1.89% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17162643 1.36% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9180731 0.73% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78553482 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390519 # Number of instructions committed -system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1264816229 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384383866 # Number of instructions committed +system.cpu.commit.committedOps 1885338618 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908386041 # Number of memory references committed -system.cpu.commit.loads 631388963 # Number of loads committed +system.cpu.commit.refs 908383382 # Number of memory references committed +system.cpu.commit.loads 631387633 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350326 # Number of branches committed +system.cpu.commit.branches 291348996 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653700675 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78553482 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4369697780 # The number of ROB reads -system.cpu.rob.rob_writes 6568059146 # The number of ROB writes -system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379503 # Number of Instructions Simulated -system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated -system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads -system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes -system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads -system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes -system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes -system.cpu.icache.replacements 29072 # number of replacements -system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use -system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4390165307 # The number of ROB reads +system.cpu.rob.rob_writes 6592584661 # The number of ROB writes +system.cpu.timesIdled 1305443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19968977 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384372850 # Number of Instructions Simulated +system.cpu.committedOps 1885327602 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384372850 # Number of Instructions Simulated +system.cpu.cpi 1.061499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.061499 # CPI: Total CPI of All Threads +system.cpu.ipc 0.942064 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.942064 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12961850201 # number of integer regfile reads +system.cpu.int_regfile_writes 2434855102 # number of integer regfile writes +system.cpu.fp_regfile_reads 71417921 # number of floating regfile reads +system.cpu.fp_regfile_writes 51448336 # number of floating regfile writes +system.cpu.misc_regfile_reads 4106986212 # number of misc regfile reads +system.cpu.misc_regfile_writes 13773806 # number of misc regfile writes +system.cpu.icache.replacements 25589 # number of replacements +system.cpu.icache.tagsinuse 1654.450414 # Cycle average of tags in use +system.cpu.icache.total_refs 419572856 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 27281 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15379.672886 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # 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miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1654.450414 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.807837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.807837 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 419577538 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 419577538 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 419577538 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 419577538 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 419577538 # number of overall hits +system.cpu.icache.overall_hits::total 419577538 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33149 # number of overall misses +system.cpu.icache.overall_misses::total 33149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 298308500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 298308500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 298308500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 298308500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 298308500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 298308500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 419610687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 419610687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 419610687 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 419610687 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 419610687 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 419610687 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000079 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000079 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000079 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000079 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000079 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000079 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8999.019578 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8999.019578 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8999.019578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8999.019578 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # 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mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 781 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 781 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 781 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 180567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 180567000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5578.565250 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5578.565250 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532415 # number of replacements -system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use -system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1032932504 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.970368 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999749 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999749 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 758296274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 758296274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276114755 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276114755 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10674 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10674 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10437 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10437 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1034411029 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3653704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3653704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3653704 # number of overall misses +system.cpu.dcache.overall_misses::total 3653704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 91513466000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 91513466000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28577501500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28577501500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 115500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 120090967500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 120090967500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 120090967500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 120090967500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 761129055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 761129055 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10677 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10677 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10437 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10437 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1038064733 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1038064733 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1038064733 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1038064733 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003722 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003722 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000281 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000281 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003520 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003520 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003520 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003520 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32305.167960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32305.167960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34811.427503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34811.427503 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32868.280381 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32868.280381 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks -system.cpu.dcache.writebacks::total 106560 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 108625 # number of writebacks +system.cpu.dcache.writebacks::total 108625 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1368436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1368436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743264 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1648210 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463799 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1463799 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2111700 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2111700 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2111700 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2111700 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464345 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464345 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1542004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1542004 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1542004 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1542004 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49970798500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49970798500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2507122500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2507122500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52477921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52477921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52477921000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52477921000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001485 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001485 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001485 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001485 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34125.017329 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34125.017329 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32283.734017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32283.734017 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34032.285908 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34032.285908 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34032.285908 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34032.285908 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480284 # number of replacements -system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use -system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480163 # number of replacements +system.cpu.l2cache.tagsinuse 32703.911790 # Cycle average of tags in use +system.cpu.l2cache.total_refs 86402 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512907 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.057110 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 61.172380 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28946.522403 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.090509 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001867 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.883378 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.975754 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27428 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51328 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 78756 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 106560 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 106560 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3110.119974 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 59.486457 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29534.305360 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.094913 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001815 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.901315 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998044 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24063 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 77734 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108625 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48571122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252292000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2252292000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 114766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50708648500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50823414500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 114766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50708648500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50823414500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 30776 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1463799 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476733 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99910500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45876091500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45976002000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99910500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45876091500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45976002000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963334 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999410 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999410 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.946138 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.946138 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31076.360809 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.985782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.002552 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.809625 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.809625 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 73b2ffcd2..c9a1801d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 1893c8b1d..d3221b5d3 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:11:11 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:03:08 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 945613131000 because target called exit() +Exiting @ tick 945613126000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 56b9fe676..088f25fd3 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613131000 # Number of ticks simulated -final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 945613126000 # Number of ticks simulated +final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1814541 # Simulator instruction rate (inst/s) -host_op_rate 2471154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239437075 # Simulator tick rate (ticks/s) -host_mem_usage 226248 # Number of bytes of host memory used -host_seconds 762.94 # Real time elapsed on the host -sim_insts 1384381614 # Number of instructions simulated -sim_ops 1885336367 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 5561086040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2464405275 # Number of bytes read from this memory -system.physmem.bytes_read::total 8025491315 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5561086040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5561086040 # Number of instructions bytes read from this memory +host_inst_rate 2568124 # Simulator instruction rate (inst/s) +host_op_rate 3497430 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1754178123 # Simulator tick rate (ticks/s) +host_mem_usage 233172 # Number of bytes of host memory used +host_seconds 539.06 # Real time elapsed on the host +sim_insts 1384381606 # Number of instructions simulated +sim_ops 1885336358 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory +system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1390271510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 620345399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2010616909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5880931491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606145361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8487076852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5880931491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3794748141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9675679632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226263 # number of cpu cycles simulated +system.cpu.numCycles 1891226253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1384381614 # Number of instructions committed -system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.committedInsts 1384381606 # Number of instructions committed +system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_func_calls 80372855 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382479 # number of memory refs +system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226263 # Number of busy cycles +system.cpu.num_busy_cycles 1891226253 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 1dd9a3ff2..a14c026cf 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 579afd945..e82eb191d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:24:05 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:12:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369901960000 because target called exit() +Exiting @ tick 2369826854000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 4610b3f7b..a105f9616 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369902 # Number of seconds simulated -sim_ticks 2369901960000 # Number of ticks simulated -final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.369827 # Number of seconds simulated +sim_ticks 2369826854000 # Number of ticks simulated +final_tick 2369826854000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 768078 # Simulator instruction rate (inst/s) -host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1317503901 # Simulator tick rate (ticks/s) -host_mem_usage 235416 # Number of bytes of host memory used -host_seconds 1798.78 # Real time elapsed on the host -sim_insts 1381604347 # Number of instructions simulated -sim_ops 1874244950 # Number of ops (including micro ops) simulated +host_inst_rate 1185646 # Simulator instruction rate (inst/s) +host_op_rate 1608413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2033704433 # Simulator tick rate (ticks/s) +host_mem_usage 241756 # Number of bytes of host memory used +host_seconds 1165.28 # Real time elapsed on the host +sim_insts 1381604339 # Number of instructions simulated +sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory -system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory +system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39849932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39910885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39849932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41695968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739803920 # number of cpu cycles simulated +system.cpu.numCycles 4739653708 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604347 # Number of instructions committed -system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.committedInsts 1381604339 # Number of instructions committed +system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_func_calls 80372855 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382479 # number of memory refs +system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.num_busy_cycles 4739653708 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1392.324421 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1392.324421 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits -system.cpu.icache.overall_hits::total 1390251708 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits +system.cpu.icache.overall_hits::total 1390251699 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses @@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 372036000 system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses @@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.960317 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997872000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.960317 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits -system.cpu.dcache.overall_hits::total 895737439 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits +system.cpu.dcache.overall_hits::total 895737438 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650886000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79650886000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83445712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83445712000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.799723 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54409.773267 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks -system.cpu.dcache.writebacks::total 107259 # number of writebacks +system.cpu.dcache.writebacks::writebacks 109047 # number of writebacks +system.cpu.dcache.writebacks::total 109047 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478755 # number of replacements -system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1478696 # number of replacements +system.cpu.l2cache.tagsinuse 32689.777876 # Cycle average of tags in use +system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000995 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3194.588699 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.929350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29462.259827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899117 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997613 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49593 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 67139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107259 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107259 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109047 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109047 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 73826 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 58068 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 75614 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17546 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56280 # number of overall hits -system.cpu.l2cache.overall_hits::total 73826 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 58068 # number of overall hits +system.cpu.l2cache.overall_hits::total 75614 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2257 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411280 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1409492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1411749 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1477373 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479630 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1477842 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1477373 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479630 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses +system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73386560000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73503924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76823396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76823396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76940760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109047 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109047 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses @@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 19803 system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964829 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.953449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.962137 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.951325 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -379,38 +379,38 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2257 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411280 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1411749 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1477373 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1479630 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1477842 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1477373 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1479630 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56451200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469960000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59094920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59113680000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59113680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 738c09057..ef879d8e7 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 91ee744be..23e06e448 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:25:13 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:15:35 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47232621500 because target called exit() +Exiting @ tick 47017029500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 0593fb6f2..0041bdcc8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047233 # Number of seconds simulated -sim_ticks 47232621500 # Number of ticks simulated -final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047017 # Number of seconds simulated +sim_ticks 47017029500 # Number of ticks simulated +final_tick 47017029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102058 # Simulator instruction rate (inst/s) -host_op_rate 102058 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54566702 # Simulator tick rate (ticks/s) -host_mem_usage 223484 # Number of bytes of host memory used -host_seconds 865.59 # Real time elapsed on the host +host_inst_rate 156470 # Simulator instruction rate (inst/s) +host_op_rate 156470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83276889 # Simulator tick rate (ticks/s) +host_mem_usage 227180 # Number of bytes of host memory used +host_seconds 564.59 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 602240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10564992 # Number of bytes read from this memory -system.physmem.bytes_read::total 11167232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7713024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7713024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165078 # Number of read requests responded to by this memory -system.physmem.num_reads::total 174488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 12750510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 223679984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 236430493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163298664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 12750510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 223679984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 399729158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 515072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272768 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160512 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10955009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 218490366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229445376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10955009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10955009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 157866205 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 157866205 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 157866205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10955009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 218490366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 387311580 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -42,18 +42,18 @@ system.cpu.dtb.read_hits 20277221 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367369 # DTB read accesses -system.cpu.dtb.write_hits 14736811 # DTB write hits +system.cpu.dtb.write_hits 14736814 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014032 # DTB hits +system.cpu.dtb.write_accesses 14744066 # DTB write accesses +system.cpu.dtb.data_hits 35014035 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111432 # DTB accesses -system.cpu.itb.fetch_hits 12477897 # ITB hits -system.cpu.itb.fetch_misses 13095 # ITB misses +system.cpu.dtb.data_accesses 35111435 # DTB accesses +system.cpu.itb.fetch_hits 12478267 # ITB hits +system.cpu.itb.fetch_misses 13087 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12490992 # ITB accesses +system.cpu.itb.fetch_accesses 12491354 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 94465244 # number of cpu cycles simulated +system.cpu.numCycles 94034060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18830633 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442208 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5026177 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16228748 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5052031 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660951 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.130134 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8480322 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10350311 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74324480 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126643730 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65335 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064147 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292965 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14127744 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064158 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4682153 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4915677 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8856497 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.692818 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775466 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78068863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. -system.cpu.activity 74.400368 # Percentage of cycles cpu is active +system.cpu.timesIdled 305152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23747130 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70286930 # Number of cycles cpu stages are processed. +system.cpu.activity 74.746246 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.064448 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.064448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.939454 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85310 # number of replacements -system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use -system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks. +system.cpu.ipc_total 0.939454 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 40602486 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53431574 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.821511 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51377982 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42656078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.362370 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50907944 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126116 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.862229 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71905105 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22128955 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.532915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47936936 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009478 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009478 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009478 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17668.535383 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17668.535383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17668.535383 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.307132 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921537 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921537 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12360070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12360070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12360070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12360070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12360070 # number of overall hits +system.cpu.icache.overall_hits::total 12360070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118149 # number of overall misses +system.cpu.icache.overall_misses::total 118149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2012242500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2012242500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2012242500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2012242500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2012242500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2012242500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12478219 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12478219 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12478219 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12478219 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12478219 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12478219 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17031.396796 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17031.396796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17031.396796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17031.396796 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1223500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 109 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 11224.770642 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15638.633866 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30805 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30805 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30805 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30805 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30805 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30805 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1308493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1308493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1308493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1308493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1308493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1308493500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14980.920269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14980.920269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use -system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.021699 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126085 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 167.000666 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits -system.cpu.dcache.overall_hits::total 34125996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses -system.cpu.dcache.overall_misses::total 764019 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 4073.021699 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994390 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994390 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180546 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180546 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945539 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945539 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126085 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126085 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126085 # number of overall hits +system.cpu.dcache.overall_hits::total 34126085 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96092 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96092 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 763930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 763930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 763930 # number of overall misses +system.cpu.dcache.overall_misses::total 763930 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3967104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3967104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35310638000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35310638000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39277742000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39277742000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39277742000 # 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miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43236.445110 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52900.510754 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51683.893332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51683.893332 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.021895 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021895 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021895 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021895 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41284.435749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41284.435749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52873.059035 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52873.059035 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51415.367900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51415.367900 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6330819000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124116 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51007.275452 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks -system.cpu.dcache.writebacks::total 161215 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165812 # number of writebacks +system.cpu.dcache.writebacks::total 165812 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524258 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524258 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559583 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559583 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559583 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559583 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254482000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1914810500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1914810500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7237342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7237342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9152152500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9152152500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9152152500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9152152500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34375.170734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50525.713888 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31510.696595 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31510.696595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50406.337930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50406.337930 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148111 # number of replacements -system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use -system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 136133 # number of replacements +system.cpu.l2cache.tagsinuse 28807.621629 # Cycle average of tags in use +system.cpu.l2cache.total_refs 146477 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166996 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.877129 # 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number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77946 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39269 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 117215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77946 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39269 # number of overall hits -system.cpu.l2cache.overall_hits::total 117215 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 42988 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 79296 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 43835 # number of overall hits +system.cpu.l2cache.overall_hits::total 123131 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 8048 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 29464 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37512 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131048 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131048 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8048 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 160512 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168560 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8048 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 160512 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87344 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291691 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.290591 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598170 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52222.387643 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52124.547529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52148.652056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52148.652056 # average overall miss latency +system.cpu.l2cache.overall_accesses::total 291691 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092141 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486389 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.253595 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911511 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911511 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092141 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785487 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.577872 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092141 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785487 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.577872 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52282.057654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52192.268531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52211.532310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52110.169556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52110.169556 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52132.727219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52132.727219 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,52 +418,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks -system.cpu.l2cache.writebacks::total 120516 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9410 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42988 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9410 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.290591 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.598170 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.598170 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.948823 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40020.931559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks +system.cpu.l2cache.writebacks::total 115975 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8048 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131048 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131048 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160512 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168560 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160512 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168560 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 322504500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178813500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1501318000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5243991500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5243991500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 322504500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6422805000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6745309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 322504500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6422805000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6745309500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253595 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577872 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577872 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40072.626740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40008.603720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40022.339518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.807185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.807185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 51735fdde..6543d2325 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 331fe5e75..109541527 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:55 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:20:14 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21302882000 because target called exit() +Exiting @ tick 21029927000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f6437b65f..3719775b2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021303 # Number of seconds simulated -sim_ticks 21302882000 # Number of ticks simulated -final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021030 # Number of seconds simulated +sim_ticks 21029927000 # Number of ticks simulated +final_tick 21029927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166406 # Simulator instruction rate (inst/s) -host_op_rate 166406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44538843 # Simulator tick rate (ticks/s) -host_mem_usage 224724 # Number of bytes of host memory used -host_seconds 478.30 # Real time elapsed on the host +host_inst_rate 262496 # Simulator instruction rate (inst/s) +host_op_rate 262496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69357396 # Simulator tick rate (ticks/s) +host_mem_usage 228212 # Number of bytes of host memory used +host_seconds 303.21 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 658624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10591744 # Number of bytes read from this memory -system.physmem.bytes_read::total 11250368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 658624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 658624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7713792 # Number of bytes written to this memory -system.physmem.bytes_written::total 7713792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175787 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120528 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 30917131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497197703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 528114834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 30917131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 30917131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 362100865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 362100865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 362100865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 30917131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497197703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890215699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 558848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10293248 # Number of bytes read from this memory +system.physmem.bytes_read::total 10852096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 558848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 558848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426112 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169564 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116033 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116033 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 26573939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 489457144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 516031083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 26573939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26573939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 353121150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 353121150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 353121150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 26573939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 489457144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 869152232 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22551743 # DTB read hits -system.cpu.dtb.read_misses 221888 # DTB read misses -system.cpu.dtb.read_acv 31 # DTB read access violations -system.cpu.dtb.read_accesses 22773631 # DTB read accesses -system.cpu.dtb.write_hits 15815895 # DTB write hits -system.cpu.dtb.write_misses 41880 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 15857775 # DTB write accesses -system.cpu.dtb.data_hits 38367638 # DTB hits -system.cpu.dtb.data_misses 263768 # DTB misses -system.cpu.dtb.data_acv 34 # DTB access violations -system.cpu.dtb.data_accesses 38631406 # DTB accesses -system.cpu.itb.fetch_hits 14242802 # ITB hits -system.cpu.itb.fetch_misses 40881 # ITB misses +system.cpu.dtb.read_hits 22489459 # DTB read hits +system.cpu.dtb.read_misses 217588 # DTB read misses +system.cpu.dtb.read_acv 44 # DTB read access violations +system.cpu.dtb.read_accesses 22707047 # DTB read accesses +system.cpu.dtb.write_hits 15786869 # DTB write hits +system.cpu.dtb.write_misses 41269 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 15828138 # DTB write accesses +system.cpu.dtb.data_hits 38276328 # DTB hits +system.cpu.dtb.data_misses 258857 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38535185 # DTB accesses +system.cpu.itb.fetch_hits 14133999 # ITB hits +system.cpu.itb.fetch_misses 38583 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14283683 # ITB accesses +system.cpu.itb.fetch_accesses 14172582 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42605767 # number of cpu cycles simulated +system.cpu.numCycles 42059856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits +system.cpu.BPredUnit.lookups 16727417 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10795081 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 475795 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12310974 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7475407 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1997632 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44950 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15195386 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106731428 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16727417 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9473039 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19807941 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2142694 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4831440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318425 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14133999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 219929 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 41712717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.558726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.170110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21904776 52.51% 52.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1546832 3.71% 56.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1409518 3.38% 59.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1517307 3.64% 63.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4200862 10.07% 73.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1863663 4.47% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 687442 1.65% 79.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091312 2.62% 82.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7491005 17.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 41712717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.397705 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.537608 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16282600 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4400388 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18871589 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 713555 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1444585 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3801857 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109351 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104838793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305565 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1444585 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16762775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2290284 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 81927 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19061483 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2071663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103408033 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1890 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1956072 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62335498 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124694291 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124234000 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 460291 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9788617 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5545 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5542 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4401091 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23371275 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16383320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1113297 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 382577 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91444399 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5409 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89052036 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123621 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11266129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4895344 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 826 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 41712717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.134889 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.120974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13445094 32.23% 32.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6815105 16.34% 48.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5522712 13.24% 61.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4804260 11.52% 73.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4760133 11.41% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2656664 6.37% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1952953 4.68% 95.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1309211 3.14% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 446585 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 41712717 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129648 6.83% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 800646 42.16% 48.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 968600 51.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49748943 55.87% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43836 0.05% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121395 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122222 0.14% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38945 0.04% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22978145 25.80% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15998405 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued -system.cpu.iq.rate 2.095998 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89052036 # Type of FU issued +system.cpu.iq.rate 2.117269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1898894 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221228638 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102311745 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87003241 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 610666 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420329 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 297405 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90645490 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305440 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1454782 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3094637 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5405 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17198 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1769943 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2465 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1444585 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1378750 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 59667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100988081 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 245674 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23371275 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16383320 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5409 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41936 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17198 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 251719 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 174529 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426248 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88078074 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22710515 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9561759 # number of nop insts executed -system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172966 # Number of branches executed -system.cpu.iew.exec_stores 15858326 # Number of stores executed -system.cpu.iew.exec_rate 2.071748 # Inst execution rate -system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33493281 # num instructions producing a value -system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value +system.cpu.iew.exec_nop 9538273 # number of nop insts executed +system.cpu.iew.exec_refs 38539046 # number of memory reference insts executed +system.cpu.iew.exec_branches 15143390 # Number of branches executed +system.cpu.iew.exec_stores 15828531 # Number of stores executed +system.cpu.iew.exec_rate 2.094113 # Inst execution rate +system.cpu.iew.wb_sent 87713914 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33458604 # num instructions producing a value +system.cpu.iew.wb_consumers 43597958 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back +system.cpu.iew.wb_rate 2.075629 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767435 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9531604 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 368829 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40268132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.193811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.828127 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17348502 43.08% 43.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7047839 17.50% 60.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3405424 8.46% 69.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2108778 5.24% 74.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2046687 5.08% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1183274 2.94% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1130602 2.81% 85.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 707287 1.76% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5289739 13.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40268132 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5289739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132302765 # The number of ROB reads -system.cpu.rob.rob_writes 197976180 # The number of ROB writes -system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131533327 # The number of ROB reads +system.cpu.rob.rob_writes 197192647 # The number of ROB writes +system.cpu.timesIdled 15699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 347139 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads -system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116852046 # number of integer regfile reads -system.cpu.int_regfile_writes 57987678 # number of integer regfile writes -system.cpu.fp_regfile_reads 254259 # number of floating regfile reads -system.cpu.fp_regfile_writes 241396 # number of floating regfile writes -system.cpu.misc_regfile_reads 38319 # number of misc regfile reads +system.cpu.cpi 0.528445 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528445 # CPI: Total CPI of All Threads +system.cpu.ipc 1.892345 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.892345 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116616744 # number of integer regfile reads +system.cpu.int_regfile_writes 57879304 # number of integer regfile writes +system.cpu.fp_regfile_reads 252339 # number of floating regfile reads +system.cpu.fp_regfile_writes 241658 # number of floating regfile writes +system.cpu.misc_regfile_reads 38301 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 94879 # number of replacements -system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use -system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits -system.cpu.icache.overall_hits::total 14141018 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 101784 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 101784 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 101784 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 101784 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 101784 # number of overall misses -system.cpu.icache.overall_misses::total 101784 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 964559500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 964559500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 964559500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 964559500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 964559500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 964559500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14242802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14242802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14242802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14242802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9476.533640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9476.533640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9476.533640 # average overall miss latency +system.cpu.icache.replacements 93371 # number of replacements +system.cpu.icache.tagsinuse 1930.973067 # Cycle average of tags in use +system.cpu.icache.total_refs 14034495 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 95419 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.082814 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17612659000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.973067 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942858 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942858 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14034495 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14034495 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14034495 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14034495 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14034495 # number of overall hits +system.cpu.icache.overall_hits::total 14034495 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14133999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14133999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14133999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14133999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14133999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14133999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007040 # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 96928 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 96928 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 566036000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 566036000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 566036000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 566036000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006805 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006805 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006805 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5839.757346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4084 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 511334500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 511334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 511334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 511334500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 511334500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006751 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006751 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5358.776986 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5358.776986 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201683 # number of replacements -system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use -system.cpu.dcache.total_refs 34409774 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205779 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.217131 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 158059000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.258401 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995180 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995180 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20831540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20831540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13578164 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13578164 # number of WriteReq hits +system.cpu.dcache.replacements 201494 # number of replacements +system.cpu.dcache.tagsinuse 4076.242085 # Cycle average of tags in use +system.cpu.dcache.total_refs 34356241 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205590 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.110467 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 156434000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.242085 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995176 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995176 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20778024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20778024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13578147 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13578147 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits -system.cpu.dcache.overall_hits::total 34409704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1292995 # number of overall misses -system.cpu.dcache.overall_misses::total 1292995 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8279025500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8279025500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34022399498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34022399498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42301424998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42301424998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42301424998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42301424998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21089322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21089322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 34356171 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34356171 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34356171 # number of overall hits +system.cpu.dcache.overall_hits::total 34356171 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 254081 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 254081 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035230 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1289311 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1289311 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1289311 # number of overall misses +system.cpu.dcache.overall_misses::total 1289311 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7948579000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7948579000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34030906498 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35702699 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35702699 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012223 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070840 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35645482 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35645482 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35645482 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012081 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012081 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070841 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036170 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036170 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036170 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036170 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31283.641831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31283.641831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32872.797830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32872.797830 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32559.627195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32559.627195 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5911.764706 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks -system.cpu.dcache.writebacks::total 161705 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195431 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 195431 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891785 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891785 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1087216 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1281958000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4735775500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4735775500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6017733500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 166286 # number of writebacks +system.cpu.dcache.writebacks::total 166286 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191915 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 191915 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891806 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1083721 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1083721 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1083721 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1083721 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62166 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62166 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143424 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143424 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205590 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205590 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205590 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205590 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1142650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1142650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4721135000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4721135000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5863785000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5863785000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5863785000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5863785000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002956 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005764 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005764 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20560.343860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33018.486627 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005768 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005768 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 299903500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1029755500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1329659000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4515967000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4515967000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 299903500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5545722500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 5845626000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 299903500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5545722500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5845626000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 95420 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62164 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 157584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 166286 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 166286 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143426 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143426 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 95420 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205590 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 301010 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 95420 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.782295 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.563317 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34345.338983 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34473.419035 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34444.447323 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34483.296554 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34483.296554 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34345.338983 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34481.462022 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34474.452124 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34345.338983 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34481.462022 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34474.452124 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2545.454545 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks -system.cpu.l2cache.writebacks::total 120528 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10291 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34099 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 44390 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131397 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131397 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10291 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165496 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 175787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10291 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165496 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 175787 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 319907000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1058267500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1378174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118158500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118158500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 319907000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176426000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5496333000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 319907000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.916086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.580717 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.580717 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31046.958774 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.343410 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 116033 # number of writebacks +system.cpu.l2cache.writebacks::total 116033 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8732 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29871 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169564 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8732 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169564 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 271655000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 927105000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1198760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4112324500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4112324500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 271655000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5039429500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5311084500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 271655000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5039429500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5311084500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480519 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244968 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913091 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913091 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.563317 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.563317 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31110.284013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.958923 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31053.545061 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31401.138507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31401.138507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 92307a506..db5db2a63 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index 8571fc6fb..1808f3b15 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:21:00 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:25:28 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 134276988000 because target called exit() +Exiting @ tick 134036748000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 026fc581b..9facba206 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134277 # Number of seconds simulated -sim_ticks 134276988000 # Number of ticks simulated -final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134037 # Number of seconds simulated +sim_ticks 134036748000 # Number of ticks simulated +final_tick 134036748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1431789 # Simulator instruction rate (inst/s) -host_op_rate 1431788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2176303972 # Simulator tick rate (ticks/s) -host_mem_usage 222880 # Number of bytes of host memory used -host_seconds 61.70 # Real time elapsed on the host +host_inst_rate 2004374 # Simulator instruction rate (inst/s) +host_op_rate 2004373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3041175629 # Simulator tick rate (ticks/s) +host_mem_usage 226164 # Number of bytes of host memory used +host_seconds 44.07 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 558272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10563648 # Number of bytes read from this memory -system.physmem.bytes_read::total 11121920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7712384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7712384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8723 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 173780 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120506 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120506 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4157615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 78670576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 82828191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 57436379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4157615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 78670576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140264570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory +system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory +system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3620738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76624718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 80245456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55366309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3620738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76624718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135611765 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 268553976 # number of cpu cycles simulated +system.cpu.numCycles 268073496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 268553976 # Number of busy cycles +system.cpu.num_busy_cycles 268073496 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.539157 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.539157 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913837 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1388590000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1388590000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1388590000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1388590000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18793.107960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18793.107960 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18166.701554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18166.701554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18166.701554 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159282000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1159282000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.827650 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4078.827650 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995808 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995808 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9600850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9600850000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37208.307277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52460.753040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47925.116470 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34354.441629 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34354.441629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52328.824750 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52328.824750 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46983.762675 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks -system.cpu.dcache.writebacks::total 161222 # number of writebacks +system.cpu.dcache.writebacks::writebacks 165828 # number of writebacks +system.cpu.dcache.writebacks::total 165828 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987818000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8987818000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 147405 # number of replacements -system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use -system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 135625 # number of replacements +system.cpu.l2cache.tagsinuse 29002.202656 # Cycle average of tags in use +system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits -system.cpu.l2cache.overall_hits::total 107000 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses -system.cpu.l2cache.overall_misses::total 173780 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 25777.846112 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1647.476120 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1576.880424 # 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number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 112720 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 68853 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 43867 # number of overall hits +system.cpu.l2cache.overall_hits::total 112720 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7583 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 29449 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37032 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131028 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131028 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 160477 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168060 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7583 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 160477 # number of overall misses +system.cpu.l2cache.overall_misses::total 168060 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531348000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1925664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813456000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6813456000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394316000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8344804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8739120000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394316000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8344804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8739120000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 165828 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 165828 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses @@ -328,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 280780 # n system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.308312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.618919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.618919 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.484630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099207 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598547 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -358,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks -system.cpu.l2cache.writebacks::total 120506 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.618919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.618919 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 115955 # number of writebacks +system.cpu.l2cache.writebacks::total 115955 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7583 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29449 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37032 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131028 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131028 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160477 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168060 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1177960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6722400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6722400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912591 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912591 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 566c57286..33fd8bc7c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index cb33c4c0f..462a53b1f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:32:39 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:13:16 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24560764000 because target called exit() +Exiting @ tick 23981004500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 826f949e8..8d4101747 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024561 # Number of seconds simulated -sim_ticks 24560764000 # Number of ticks simulated -final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023981 # Number of seconds simulated +sim_ticks 23981004500 # Number of ticks simulated +final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104807 # Simulator instruction rate (inst/s) -host_op_rate 148726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36296181 # Simulator tick rate (ticks/s) -host_mem_usage 240672 # Number of bytes of host memory used -host_seconds 676.68 # Real time elapsed on the host -sim_insts 70920072 # Number of instructions simulated -sim_ops 100639320 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory -system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 169152 # Simulator instruction rate (inst/s) +host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57193739 # Simulator tick rate (ticks/s) +host_mem_usage 242580 # Number of bytes of host memory used +host_seconds 419.29 # Real time elapsed on the host +sim_insts 70924419 # Number of instructions simulated +sim_ops 100643666 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory +system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 49121529 # number of cpu cycles simulated +system.cpu.numCycles 47962010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued -system.cpu.iq.rate 2.216654 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued +system.cpu.iq.rate 2.261272 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80316 # number of nop insts executed -system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed -system.cpu.iew.exec_branches 14752818 # Number of branches executed -system.cpu.iew.exec_stores 21480847 # Number of stores executed -system.cpu.iew.exec_rate 2.190148 # Inst execution rate -system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628736 # num instructions producing a value -system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value +system.cpu.iew.exec_nop 80134 # number of nop insts executed +system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed +system.cpu.iew.exec_branches 14662886 # Number of branches executed +system.cpu.iew.exec_stores 21472021 # Number of stores executed +system.cpu.iew.exec_rate 2.235982 # Inst execution rate +system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53610539 # num instructions producing a value +system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70925624 # Number of instructions committed -system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929971 # Number of instructions committed +system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47867821 # Number of memory references committed -system.cpu.commit.loads 27309596 # Number of loads committed +system.cpu.commit.refs 47869562 # Number of memory references committed +system.cpu.commit.loads 27310466 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671115 # Number of branches committed +system.cpu.commit.branches 13671985 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91482735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153979107 # The number of ROB reads -system.cpu.rob.rob_writes 230788170 # The number of ROB writes -system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70920072 # Number of Instructions Simulated -system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated -system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 517371049 # number of integer regfile reads -system.cpu.int_regfile_writes 104514948 # number of integer regfile writes -system.cpu.fp_regfile_reads 1051 # number of floating regfile reads -system.cpu.fp_regfile_writes 886 # number of floating regfile writes -system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads -system.cpu.misc_regfile_writes 36814 # number of misc regfile writes -system.cpu.icache.replacements 31518 # number of replacements -system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use -system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152158977 # The number of ROB reads +system.cpu.rob.rob_writes 228826081 # The number of ROB writes +system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924419 # Number of Instructions Simulated +system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated +system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads +system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516206868 # number of integer regfile reads +system.cpu.int_regfile_writes 104370444 # number of integer regfile writes +system.cpu.fp_regfile_reads 520 # number of floating regfile reads +system.cpu.fp_regfile_writes 444 # number of floating regfile writes +system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads +system.cpu.misc_regfile_writes 38556 # number of misc regfile writes +system.cpu.icache.replacements 29824 # number of replacements +system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use +system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits -system.cpu.icache.overall_hits::total 12397114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses -system.cpu.icache.overall_misses::total 35108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits +system.cpu.icache.overall_hits::total 12028408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses +system.cpu.icache.overall_misses::total 33018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,258 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158907 # number of replacements -system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use -system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44703101 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26503495 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20534 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20534 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19277 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19277 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44571602 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44571602 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44571602 # number of overall hits +system.cpu.dcache.overall_hits::total 44571602 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 105369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 105369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1548293 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1548293 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1653662 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1653662 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1653662 # number of overall misses +system.cpu.dcache.overall_misses::total 1653662 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks -system.cpu.dcache.writebacks::total 123795 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128124 # number of writebacks +system.cpu.dcache.writebacks::total 128124 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49671 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49671 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1441258 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4569551498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 84654 # number of writebacks +system.cpu.l2cache.writebacks::total 84654 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 68 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 68 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5109 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23142 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28251 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130565 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130565 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 719908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 878707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3911148000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4069946500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158798500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3911148000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4069946500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.671096 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.671096 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.110002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31108.309567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31103.571555 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 311edc8c7..5344e06dd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index f1623eafd..64d9d48cf 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:34:04 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:19:28 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 53932162000 because target called exit() +Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index b5b6453b4..875e92986 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.053932 # Number of seconds simulated -sim_ticks 53932162000 # Number of ticks simulated -final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53932157000 # Number of ticks simulated +final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1760373 # Simulator instruction rate (inst/s) -host_op_rate 2498132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1338828629 # Simulator tick rate (ticks/s) -host_mem_usage 228700 # Number of bytes of host memory used -host_seconds 40.28 # Real time elapsed on the host -sim_insts 70913189 # Number of instructions simulated -sim_ops 100632437 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 312580308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573346 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153654 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580308 # Number of instructions bytes read from this memory +host_inst_rate 2430593 # Simulator instruction rate (inst/s) +host_op_rate 3449236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1848555696 # Simulator tick rate (ticks/s) +host_mem_usage 232076 # Number of bytes of host memory used +host_seconds 29.18 # Real time elapsed on the host +sim_insts 70913181 # Number of instructions simulated +sim_ops 100632428 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory +system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27156253 # Number of read requests responded to by this memory -system.physmem.num_reads::total 105301330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27156252 # Number of read requests responded to by this memory +system.physmem.num_reads::total 105301320 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5795805256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1976062929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7771868185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5795805256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5795805256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1458502832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1458502832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5795805256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3434565761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9230371017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5795805126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1976063093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7771868220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5795805126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5795805126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1458502967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1458502967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 107864325 # number of cpu cycles simulated +system.cpu.numCycles 107864315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913189 # Number of instructions committed -system.cpu.committedOps 100632437 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses +system.cpu.committedInsts 70913181 # Number of instructions committed +system.cpu.committedOps 100632428 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472788 # number of integer instructions +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written +system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862848 # number of memory refs -system.cpu.num_load_insts 27307109 # Number of load instructions +system.cpu.num_mem_refs 47862847 # number of memory refs +system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107864325 # Number of busy cycles +system.cpu.num_busy_cycles 107864315 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 678b8b9b7..c08fcfcdd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index d480c9ad1..b1460f18e 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:34:55 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:20:08 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 133117442000 because target called exit() +Exiting @ tick 132924820000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f1e03b8eb..b1eb24a6a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133117 # Number of seconds simulated -sim_ticks 133117442000 # Number of ticks simulated -final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132925 # Number of seconds simulated +sim_ticks 132924820000 # Number of ticks simulated +final_tick 132924820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 828989 # Simulator instruction rate (inst/s) -host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568098699 # Simulator tick rate (ticks/s) -host_mem_usage 237868 # Number of bytes of host memory used -host_seconds 84.89 # Real time elapsed on the host -sim_insts 70373636 # Number of instructions simulated -sim_ops 99791663 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory -system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1112405 # Simulator instruction rate (inst/s) +host_op_rate 1577419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101158995 # Simulator tick rate (ticks/s) +host_mem_usage 240528 # Number of bytes of host memory used +host_seconds 63.26 # Real time elapsed on the host +sim_insts 70373628 # Number of instructions simulated +sim_ops 99791654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory +system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory +system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2059269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60210396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62269665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40649985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2059269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60210396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102919650 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 266234884 # number of cpu cycles simulated +system.cpu.numCycles 265849640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373636 # Number of instructions committed -system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses +system.cpu.committedInsts 70373628 # Number of instructions committed +system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472788 # number of integer instructions +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written +system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862848 # number of memory refs -system.cpu.num_load_insts 27307109 # Number of load instructions +system.cpu.num_mem_refs 47862847 # number of memory refs +system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 266234884 # Number of busy cycles +system.cpu.num_busy_cycles 265849640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use -system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1736.286948 # Cycle average of tags in use +system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits -system.cpu.icache.overall_hits::total 78126170 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 1736.286948 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847796 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847796 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits +system.cpu.icache.overall_hits::total 78126161 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 444346000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 444346000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 444346000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444346000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23500.423101 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387622000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 387622000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.906689 # Cycle average of tags in use +system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits +system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1079631000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.906689 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits -system.cpu.dcache.overall_hits::total 46830237 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits +system.cpu.dcache.overall_hits::total 46830236 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7492240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7492240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46827.085339 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks -system.cpu.dcache.writebacks::total 122808 # number of writebacks +system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks +system.cpu.dcache.writebacks::total 127057 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012246000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7012246000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113660 # number of replacements -system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use -system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 96735 # number of replacements +system.cpu.l2cache.tagsinuse 28872.647154 # Cycle average of tags in use +system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits -system.cpu.l2cache.overall_hits::total 44989 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102627 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.881123 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 127057 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 127057 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4691 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4691 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 34944 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 49575 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14631 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 34944 # number of overall hits +system.cpu.l2cache.overall_hits::total 49575 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26990 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102341 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102341 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4277 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 125054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses +system.cpu.l2cache.overall_misses::total 129331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 127057 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 127057 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks -system.cpu.l2cache.writebacks::total 88449 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 84428 # number of writebacks +system.cpu.l2cache.writebacks::total 84428 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22713 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26990 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 129331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 3ca0a8939..480848980 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index f3517e2c4..2acf8263c 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:59:31 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:58:54 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 202941992000 because target called exit() +Exiting @ tick 202680458000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3b1cc6fcd..b1d40b1a6 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202942 # Number of seconds simulated -sim_ticks 202941992000 # Number of ticks simulated -final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202680 # Number of seconds simulated +sim_ticks 202680458000 # Number of ticks simulated +final_tick 202680458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325068 # Simulator instruction rate (inst/s) -host_op_rate 1342225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2000847198 # Simulator tick rate (ticks/s) -host_mem_usage 231252 # Number of bytes of host memory used -host_seconds 101.43 # Real time elapsed on the host +host_inst_rate 1918134 # Simulator instruction rate (inst/s) +host_op_rate 1942970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2892641209 # Simulator tick rate (ticks/s) +host_mem_usage 229316 # Number of bytes of host memory used +host_seconds 70.07 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 835264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8135040 # Number of bytes read from this memory -system.physmem.bytes_read::total 8970304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5584960 # Number of bytes written to this memory -system.physmem.bytes_written::total 5584960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 127110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 140161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 87265 # Number of write requests responded to by this memory -system.physmem.num_writes::total 87265 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4115777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 40085543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 44201320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27519982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4115777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 40085543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 71721303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory +system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory +system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3284303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39007767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 42292069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3284303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3284303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26156325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26156325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26156325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3284303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39007767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68448395 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 405883984 # number of cpu cycles simulated +system.cpu.numCycles 405360916 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398975 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160249 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405883984 # Number of busy cycles +system.cpu.num_busy_cycles 405360916 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.741762 # Cycle average of tags in use system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 144318639000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.741762 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978878 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3055178000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3055178000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3055178000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3055178000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3055178000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3055178000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16930.864488 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16335.753700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16335.753700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16335.753700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16335.753700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2494106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2494106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494106000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2494106000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.753700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.753700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.606333 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4087.606333 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997951 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997951 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1569302000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1569302000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728156000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5728156000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 420000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 420000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7297458000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7297458000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7297458000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7297458000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 30800 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49432.508313 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34490.911888 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34490.911888 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54468.791602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54468.791602 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 28000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48435.634496 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48435.634496 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks -system.cpu.dcache.writebacks::total 118818 # number of writebacks +system.cpu.dcache.writebacks::writebacks 122378 # number of writebacks +system.cpu.dcache.writebacks::total 122378 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432805000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432805000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845469000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6845469000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845469000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6845469000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 27800 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.911888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31490.911888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 120138 # number of replacements -system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use -system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 101560 # number of replacements +system.cpu.l2cache.tagsinuse 29288.840921 # Cycle average of tags in use +system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 118818 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3599 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3599 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 173973 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 23568 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 197541 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 173973 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 23568 # number of overall hits -system.cpu.l2cache.overall_hits::total 197541 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13051 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 25530 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 38581 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101580 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101580 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13051 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127110 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 140161 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13051 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127110 # number of overall misses -system.cpu.l2cache.overall_misses::total 140161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 678652000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1327560000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2006212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5282160000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5282160000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 678652000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6609720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7288372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 678652000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6609720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7288372000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 24773.097821 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3265.951230 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1249.791870 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.756015 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.099669 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.038141 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893824 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 122378 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 122378 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3844 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3844 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 176623 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 27145 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 203768 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 176623 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 27145 # number of overall hits +system.cpu.l2cache.overall_hits::total 203768 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 10401 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 22198 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32599 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101335 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101335 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10401 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123533 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 133934 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses +system.cpu.l2cache.overall_misses::total 133934 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154296000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1695148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5269420000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5269420000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 540852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6423716000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6964568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 540852000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6423716000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6964568000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 118818 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 118818 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 122378 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 122378 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses @@ -316,17 +316,17 @@ system.cpu.l2cache.demand_accesses::total 337702 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165923 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965782 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.415043 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.415043 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.055613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.487879 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.140197 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963453 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.963453 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.055613 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.819848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.396604 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -346,41 +346,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks -system.cpu.l2cache.writebacks::total 87265 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13051 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 25530 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 38581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101580 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101580 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13051 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 127110 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 140161 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13051 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 127110 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 140161 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 522040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1021200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1543240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4063200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4063200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 522040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5084400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5606440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 522040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165923 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965782 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.415043 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.415043 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 82834 # number of writebacks +system.cpu.l2cache.writebacks::total 82834 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10401 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22198 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101335 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101335 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 133934 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1303960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5357360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5357360000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963453 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963453 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 1fcd4f24c..4a4e79f41 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 0482efbeb..74ab835bf 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:44:37 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:25:40 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1009998808500 because target called exit() +Exiting @ tick 991340143500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 0ddfc2b1c..35d38838f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009999 # Number of seconds simulated -sim_ticks 1009998808500 # Number of ticks simulated -final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.991340 # Number of seconds simulated +sim_ticks 991340143500 # Number of ticks simulated +final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98665 # Simulator instruction rate (inst/s) -host_op_rate 98665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54760444 # Simulator tick rate (ticks/s) -host_mem_usage 215204 # Number of bytes of host memory used -host_seconds 18443.95 # Real time elapsed on the host +host_inst_rate 147354 # Simulator instruction rate (inst/s) +host_op_rate 147354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 80272080 # Simulator tick rate (ticks/s) +host_mem_usage 218972 # Number of bytes of host memory used +host_seconds 12349.75 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory -system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory -system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614444 # DTB read hits +system.cpu.dtb.read_hits 444614343 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511522 # DTB read accesses -system.cpu.dtb.write_hits 160920906 # DTB write hits +system.cpu.dtb.read_accesses 449511421 # DTB read accesses +system.cpu.dtb.write_hits 160920087 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622210 # DTB write accesses -system.cpu.dtb.data_hits 605535350 # DTB hits +system.cpu.dtb.write_accesses 162621391 # DTB write accesses +system.cpu.dtb.data_hits 605534430 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133732 # DTB accesses -system.cpu.itb.fetch_hits 231980230 # ITB hits +system.cpu.dtb.data_accesses 612132812 # DTB accesses +system.cpu.itb.fetch_hits 232194533 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231980252 # ITB accesses +system.cpu.itb.fetch_accesses 232194555 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019997618 # number of cpu cycles simulated +system.cpu.numCycles 1982680288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits +system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989652 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989806 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. -system.cpu.activity 78.063714 # Percentage of cycles cpu is active +system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed. +system.cpu.activity 79.544400 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads +system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use -system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use +system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits -system.cpu.icache.overall_hits::total 231979155 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses -system.cpu.icache.overall_misses::total 1072 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.725255 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325549 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325549 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232193463 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232193463 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232193463 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232193463 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232193463 # number of overall hits +system.cpu.icache.overall_hits::total 232193463 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1067 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1067 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1067 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1067 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1067 # number of overall misses +system.cpu.icache.overall_misses::total 1067 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58495000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58495000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58495000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58495000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58495000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58495000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232194530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232194530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232194530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232194530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232194530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232194530 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54821.930647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54821.930647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54821.930647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54821.930647 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 208 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 208 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 208 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45935000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45935000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45935000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45935000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45935000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45935000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53474.970896 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53474.970896 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use -system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits -system.cpu.dcache.overall_hits::total 595069970 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses -system.cpu.dcache.overall_misses::total 10254195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles +system.cpu.dcache.replacements 9107366 # number of replacements +system.cpu.dcache.tagsinuse 4082.290547 # Cycle average of tags in use +system.cpu.dcache.total_refs 595076211 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310727 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12667784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.290547 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996653 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996653 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271439 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271439 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157804772 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157804772 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595076211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595076211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595076211 # number of overall hits +system.cpu.dcache.overall_hits::total 595076211 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2923730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2923730 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10247954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10247954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10247954 # number of overall misses +system.cpu.dcache.overall_misses::total 10247954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 162150578000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 162150578000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105068682500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105068682500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 267219260500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 267219260500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 267219260500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 267219260500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018190 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018190 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016930 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016930 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016930 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016930 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22138.943047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22138.943047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35936.520301 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35936.520301 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26075.376656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26075.376656 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10790500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7928721000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2625 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208163 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4110.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38089.002368 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks -system.cpu.dcache.writebacks::total 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3389687 # number of writebacks +system.cpu.dcache.writebacks::total 3389687 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101944 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1034548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1034548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136492 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136492 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136492 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136492 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137265020500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137265020500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54890953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54890953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192155973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 192155973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192155973500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 192155973500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,95 +318,95 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21612.503361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31332.051551 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.773869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.773869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29055.407579 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29055.407579 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686301 # number of replacements -system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3058572 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1000333 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1000333 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6415150 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits -system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits +system.cpu.l2cache.replacements 2133759 # number of replacements +system.cpu.l2cache.tagsinuse 30545.371941 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448402 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2163450 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.905060 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 183782202000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14422.538140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.487886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16088.345915 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440141 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001052 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.490977 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.932171 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5860988 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52337.019790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52256.438623 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52256.489456 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52275.931661 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52275.931661 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52337.019790 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.591655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52263.620985 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52337.019790 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.591655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52263.620985 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -415,52 +415,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks -system.cpu.l2cache.writebacks::total 1170911 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks +system.cpu.l2cache.writebacks::total 1048517 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31621283000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86088171500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86122652500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86088171500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86122652500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188435 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417455 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417455 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index b6ae8cce3..b3f63cedd 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3e17983a4..41442f622 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:48:46 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:26:23 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 614317285000 because target called exit() +Exiting @ tick 607216877500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index ad65e54b6..66e8bd283 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.614317 # Number of seconds simulated -sim_ticks 614317285000 # Number of ticks simulated -final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607217 # Number of seconds simulated +sim_ticks 607216877500 # Number of ticks simulated +final_tick 607216877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134863 # Simulator instruction rate (inst/s) -host_op_rate 134863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47722573 # Simulator tick rate (ticks/s) -host_mem_usage 216172 # Number of bytes of host memory used -host_seconds 12872.68 # Real time elapsed on the host +host_inst_rate 209626 # Simulator instruction rate (inst/s) +host_op_rate 209626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73321119 # Simulator tick rate (ticks/s) +host_mem_usage 219996 # Number of bytes of host memory used +host_seconds 8281.61 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory -system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory -system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138164352 # Number of bytes read from this memory +system.physmem.bytes_read::total 138226304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67205952 # Number of bytes written to this memory +system.physmem.bytes_written::total 67205952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158818 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159786 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050093 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050093 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 227537075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 227639101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 110678663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 110678663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 110678663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 227537075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 338317764 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613430411 # DTB read hits -system.cpu.dtb.read_misses 10984160 # DTB read misses +system.cpu.dtb.read_hits 612238035 # DTB read hits +system.cpu.dtb.read_misses 10898868 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 624414571 # DTB read accesses -system.cpu.dtb.write_hits 208466528 # DTB write hits -system.cpu.dtb.write_misses 6835381 # DTB write misses +system.cpu.dtb.read_accesses 623136903 # DTB read accesses +system.cpu.dtb.write_hits 208056215 # DTB write hits +system.cpu.dtb.write_misses 6766994 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215301909 # DTB write accesses -system.cpu.dtb.data_hits 821896939 # DTB hits -system.cpu.dtb.data_misses 17819541 # DTB misses +system.cpu.dtb.write_accesses 214823209 # DTB write accesses +system.cpu.dtb.data_hits 820294250 # DTB hits +system.cpu.dtb.data_misses 17665862 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 839716480 # DTB accesses -system.cpu.itb.fetch_hits 401793450 # ITB hits -system.cpu.itb.fetch_misses 51 # ITB misses +system.cpu.dtb.data_accesses 837960112 # DTB accesses +system.cpu.itb.fetch_hits 401011528 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401793501 # ITB accesses +system.cpu.itb.fetch_accesses 401011585 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1228634571 # number of cpu cycles simulated +system.cpu.numCycles 1214433756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits +system.cpu.BPredUnit.lookups 380951023 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 293099658 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18933784 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 266477220 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262392566 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 25151704 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 412376649 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3157323952 # Number of instructions fetch has processed +system.cpu.fetch.Branches 380951023 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 287544270 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 576306152 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 134891835 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 111419989 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1063 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401011528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10506825 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1209281794 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.610908 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.168401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 632975642 52.34% 52.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43351030 3.58% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22268396 1.84% 57.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40872577 3.38% 61.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127179039 10.52% 71.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63789232 5.27% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40665333 3.36% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30280275 2.50% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 207900270 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1209281794 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.313686 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.599832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 441212287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97730865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 545630156 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15531465 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 109177021 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60290905 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1025 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3078047382 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 109177021 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 462067522 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51929068 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5163 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539154184 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46948836 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2995870549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 446955 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1708785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42808765 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2241183009 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3870137990 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3868740839 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1397151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 246 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 864980046 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 207 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 100505126 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 676579077 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251278116 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61563067 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34698773 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2690247704 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2489728191 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3267337 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 942739143 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 400071480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1209281794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.058849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971213 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 378679312 31.31% 31.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 195809975 16.19% 47.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 182681515 15.11% 62.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152412696 12.60% 75.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 135959135 11.24% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80206603 6.63% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63601344 5.26% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14610233 1.21% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5320981 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1209281794 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1977743 10.56% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12229984 65.27% 75.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4528924 24.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1627060855 65.35% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 100 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 286 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 14 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued @@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 640749326 25.74% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221917384 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued -system.cpu.iq.rate 2.030637 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2489728191 # Type of FU issued +system.cpu.iq.rate 2.050114 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18736651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007526 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6208757898 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3631737993 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2386612184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1984266 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870224 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2507489711 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 975131 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57077193 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 231983414 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 247523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 104727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 90549614 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 172 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 177103 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 109177021 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19521566 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 973961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2832586299 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17875212 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 676579077 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 251278116 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178484 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13307 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 104727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13292243 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8865054 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22157297 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2437364251 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 623138442 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52363940 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142658665 # number of nop insts executed -system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed -system.cpu.iew.exec_branches 299305457 # Number of branches executed -system.cpu.iew.exec_stores 215301954 # Number of stores executed -system.cpu.iew.exec_rate 1.988190 # Inst execution rate -system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1370537618 # num instructions producing a value -system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value +system.cpu.iew.exec_nop 142338412 # number of nop insts executed +system.cpu.iew.exec_refs 837961692 # number of memory reference insts executed +system.cpu.iew.exec_branches 298501873 # Number of branches executed +system.cpu.iew.exec_stores 214823250 # Number of stores executed +system.cpu.iew.exec_rate 2.006996 # Inst execution rate +system.cpu.iew.wb_sent 2416135407 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2387482408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1367770503 # num instructions producing a value +system.cpu.iew.wb_consumers 1732591741 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back +system.cpu.iew.wb_rate 1.965922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789436 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 773736355 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1112602008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.635607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507788 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18932893 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1100104773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.654188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513944 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 589258835 52.96% 52.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53793341 4.83% 82.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36407733 3.27% 85.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27937238 2.51% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22627047 2.03% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23085278 2.07% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 575678608 52.33% 52.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 180745216 16.43% 68.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90628498 8.24% 77.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53598095 4.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36474012 3.32% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28175112 2.56% 87.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22568883 2.05% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23092069 2.10% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89144280 8.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1112602008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1100104773 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89144280 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3539839075 # The number of ROB reads -system.cpu.rob.rob_writes 5315403238 # The number of ROB writes -system.cpu.timesIdled 405378 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3518697774 # The number of ROB reads +system.cpu.rob.rob_writes 5296336807 # The number of ROB writes +system.cpu.timesIdled 353272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5151962 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3284485483 # number of integer regfile reads -system.cpu.int_regfile_writes 1919152187 # number of integer regfile writes -system.cpu.fp_regfile_reads 52475 # number of floating regfile reads -system.cpu.fp_regfile_writes 577 # number of floating regfile writes +system.cpu.cpi 0.699541 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.699541 # CPI: Total CPI of All Threads +system.cpu.ipc 1.429509 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.429509 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3277031179 # number of integer regfile reads +system.cpu.int_regfile_writes 1915203405 # number of integer regfile writes +system.cpu.fp_regfile_reads 51821 # number of floating regfile reads +system.cpu.fp_regfile_writes 555 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 800.240430 # Cycle average of tags in use -system.cpu.icache.total_refs 401791975 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 409573.878695 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 769.354058 # Cycle average of tags in use +system.cpu.icache.total_refs 401010025 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414266.554752 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 800.240430 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390742 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390742 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401791975 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401791975 # 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number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 401011528 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34225.423729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34225.423729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34225.423729 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33660.678643 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33660.678643 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33660.678643 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33660.678643 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33660.678643 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16686.513125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16686.513125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27968.066921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27968.066921 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20285.420171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20285.420171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.020924 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020924 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020924 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020924 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14699.271374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14699.271374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27211.415028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27211.415028 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18801.481153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18801.481153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18801.481153 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 94480762 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33098 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3157.127470 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32992.651688 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2854.576168 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32992.429012 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3083289 # number of writebacks -system.cpu.dcache.writebacks::total 3083289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3193376 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3193376 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3030443 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3030443 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3416687 # number of writebacks +system.cpu.dcache.writebacks::total 3416687 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2770476 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2770476 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3026700 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3026700 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6223819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6223819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6223819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6223819 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296993 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296993 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883731 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 5797176 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5797176 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5797176 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5797176 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296557 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296557 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883812 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883812 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180724 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180724 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 81348046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 81348046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38571686956 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38571686956 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180369 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180369 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66994974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 66994974500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 35740755693 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 35740755693 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119919732956 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 119919732956 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119919732956 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 119919732956 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013124 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013124 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102735730193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 102735730193 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102735730193 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 102735730193 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013145 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.142857 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012809 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012809 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11148.160071 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11148.160071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20476.218184 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012825 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012825 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012825 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012825 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9181.724271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9181.724271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 18972.570348 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 18972.570348 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11190.806186 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11190.806186 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2696556 # number of replacements -system.cpu.l2cache.tagsinuse 26644.209628 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7654288 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2721176 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.812860 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 130971058500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10796.913806 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.565729 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15822.730093 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.329496 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.813117 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5472701 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5472701 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3083289 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3083289 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1001978 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1001978 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6474679 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6474679 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6474679 # number of overall hits -system.cpu.l2cache.overall_hits::total 6474679 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1824281 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 30390866500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 30390866500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 33718000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 93033972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 93067690500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 33718000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 93033972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 93067690500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 981 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296982 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3083289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3083289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 981 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180725 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 981 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180725 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2143360 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 26934706500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 33271000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 74202276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 74235547000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 33271000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 74202276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 74235547000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296544 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3416687 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3416687 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883826 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883826 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180370 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181338 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180370 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181338 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250005 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.250106 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468092 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.468092 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188625 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188732 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415383 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.294753 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.294828 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235156 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235237 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294828 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.535509 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34465.947843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34380.037768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34380.037768 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17522000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235156 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235237 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34370.867769 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34343.743915 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34343.762979 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34420.910276 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34420.910276 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34370.867769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34371.714522 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34371.714142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34370.867769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34371.714522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34371.714142 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 10439000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1011 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10404.988124 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10325.420376 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks -system.cpu.l2cache.writebacks::total 1172197 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1824281 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1825262 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 881765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 881765 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2706046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2707027 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2706046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2707027 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30568000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56848109000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56878677000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27575743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27575743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84423852000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 84454420000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050093 # number of writebacks +system.cpu.l2cache.writebacks::total 1050093 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782510 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782510 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2159786 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2159786 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30173000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42897858500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42928031500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 24429166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 24429166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30173000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67327024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 67357197500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30173000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67327024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 67357197500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188625 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188732 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415383 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235237 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235156 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31170.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.792523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31168.793691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.982505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31218.982505 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31170.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31186.984961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31186.977552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index f89f54e31..51c5aee6c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 267941dc1..80ad9dac8 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:46 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:33:25 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2663443716000 because target called exit() +Exiting @ tick 2640486390000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 3da64d83e..02104b02f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.663444 # Number of seconds simulated -sim_ticks 2663443716000 # Number of ticks simulated -final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.640486 # Number of seconds simulated +sim_ticks 2640486390000 # Number of ticks simulated +final_tick 2640486390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1479188 # Simulator instruction rate (inst/s) -host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2164950496 # Simulator tick rate (ticks/s) -host_mem_usage 214896 # Number of bytes of host memory used -host_seconds 1230.26 # Real time elapsed on the host +host_inst_rate 2162683 # Simulator instruction rate (inst/s) +host_op_rate 2162683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3138035754 # Simulator tick rate (ticks/s) +host_mem_usage 218976 # Number of bytes of host memory used +host_seconds 841.45 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory -system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory +system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory -system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2697097 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1170923 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64789385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64789385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 92944814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52104146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52123585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25414106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25414106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25414106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52104146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77537690 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5326887432 # number of cpu cycles simulated +system.cpu.numCycles 5280972780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5326887432 # Number of busy cycles +system.cpu.num_busy_cycles 5280972780 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.518964 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299002 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299002 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.518964 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -168,14 +168,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.363452 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.504248 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995973 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40985601000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.363452 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995938 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995938 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240808666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240808666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158270882000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158270882000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59580458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59580458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 217851340000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 217851340000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 217851340000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 217851340000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24508.481513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33767.845574 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26428.412638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21913.847918 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21913.847918 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31535.397921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31535.397921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23908.878376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23908.878376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23908.878376 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3058802 # number of writebacks -system.cpu.dcache.writebacks::total 3058802 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks +system.cpu.dcache.writebacks::total 3389919 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136603640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136603640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912498000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912498000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190516138000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190516138000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190516138000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190516138000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18913.847918 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18913.847918 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.397921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.397921 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20908.878376 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20908.878376 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686269 # number of replacements -system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10727.578894 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.806952 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15282.701350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.327380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466391 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.794680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5415352 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5415352 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3058802 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3058802 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1000087 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1000087 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6415439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6415439 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6415439 # number of overall hits -system.cpu.l2cache.overall_hits::total 6415439 # number of overall hits +system.cpu.l2cache.replacements 2133721 # number of replacements +system.cpu.l2cache.tagsinuse 30166.064442 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 498208075000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14372.212156 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 37.660543 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15756.191744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438605 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.480841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.920595 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389919 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100511 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100511 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6962042 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6962042 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6962042 # number of overall hits +system.cpu.l2cache.overall_hits::total 6962042 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1807062 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1807864 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 889233 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 889233 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1360883 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1361685 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 788809 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 788809 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2696295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2697097 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2149692 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2150494 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2696295 # number of overall misses -system.cpu.l2cache.overall_misses::total 2697097 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses +system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 93967224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94008928000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46240116000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46240116000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70765916000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70807620000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018068000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018068000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 41704000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140207340000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140249044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 111825688000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 41704000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140207340000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140249044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 111825688000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3058802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3058802 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389919 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses @@ -326,16 +326,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 802 system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.250285 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188425 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188515 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417509 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.295977 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235993 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.295977 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -355,41 +355,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1170923 # number of writebacks -system.cpu.l2cache.writebacks::total 1170923 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1048525 # number of writebacks +system.cpu.l2cache.writebacks::total 1048525 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807062 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1807864 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889233 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 889233 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2696295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2697097 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2149692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2150494 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2696295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2697097 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72282480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72314560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35569320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35569320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54435320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54467400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552360000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85987680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86019760000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85987680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86019760000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250285 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417509 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.295977 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.295977 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 48015577c..c94040a4a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 2f52f2c05..1148e0586 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:36:31 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:20:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 463993693500 because target called exit() +Exiting @ tick 458035985000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7863d76cc..f8f6b4a6a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.463994 # Number of seconds simulated -sim_ticks 463993693500 # Number of ticks simulated -final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458036 # Number of seconds simulated +sim_ticks 458035985000 # Number of ticks simulated +final_tick 458035985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128371 # Simulator instruction rate (inst/s) -host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38563333 # Simulator tick rate (ticks/s) -host_mem_usage 232076 # Number of bytes of host memory used -host_seconds 12031.99 # Real time elapsed on the host -sim_insts 1544563066 # Number of instructions simulated -sim_ops 1723073879 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory -system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory -system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 197390 # Simulator instruction rate (inst/s) +host_op_rate 220203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58535443 # Simulator tick rate (ticks/s) +host_mem_usage 234800 # Number of bytes of host memory used +host_seconds 7824.93 # Real time elapsed on the host +sim_insts 1544563073 # Number of instructions simulated +sim_ops 1723073885 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156358784 # Number of bytes read from this memory +system.physmem.bytes_read::total 156407104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71946432 # Number of bytes written to this memory +system.physmem.bytes_written::total 71946432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2443106 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 105494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341367904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341473398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 105494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 157075938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 157075938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 157075938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 105494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341367904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 498549336 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 927987388 # number of cpu cycles simulated +system.cpu.numCycles 916071971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits +system.cpu.BPredUnit.lookups 300386365 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246254548 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16072669 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 170403157 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156239351 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed -system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18292614 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292465712 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2157283635 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300386365 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174531965 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 428963032 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83531263 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119911343 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 109 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283465873 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5375761 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 908345220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.641582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245010 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 479382246 52.78% 52.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23075019 2.54% 55.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38696357 4.26% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47758356 5.26% 64.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40740735 4.49% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46836926 5.16% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39064245 4.30% 78.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18137906 2.00% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174653430 19.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 908345220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.327907 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.354928 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 321276302 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100437637 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403614016 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16012907 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67004358 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46143588 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 709 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2345766913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2404 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67004358 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 342772787 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44470406 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13938 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 396994343 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57089388 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2288809868 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4587251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 43867874 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2263371035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10565210641 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10565207285 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3356 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320010 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 557051025 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5363 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5361 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 133306732 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624412648 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218802984 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85974356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66146404 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2189209490 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1708 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2014638202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4851094 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 461527844 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075835396 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1528 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 908345220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.217921 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.925838 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 244431658 26.91% 26.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 136114338 14.98% 41.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157116427 17.30% 59.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116129005 12.78% 71.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125782921 13.85% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75959694 8.36% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39392857 4.34% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10729861 1.18% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2688459 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 908345220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 792596 3.16% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4903 0.02% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19003801 75.87% 79.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5245876 20.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1233307061 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 930228 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 49 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 28 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 10 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586604414 29.12% 90.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193796407 9.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued -system.cpu.iq.rate 2.172504 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2014638202 # Type of FU issued +system.cpu.iq.rate 2.199214 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25047176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4967519524 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2650923657 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956580647 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2039685190 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63569960 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138485869 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 280074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 188083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43955929 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 515490 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67004358 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19766452 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1127497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2189219165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5544678 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624412648 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218802984 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1639 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 172089 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43011 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 188083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8607625 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10203792 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18811417 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1985083877 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 571977023 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29554325 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8125 # number of nop insts executed -system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed -system.cpu.iew.exec_branches 238194699 # Number of branches executed -system.cpu.iew.exec_stores 190834919 # Number of stores executed -system.cpu.iew.exec_rate 2.140744 # Inst execution rate -system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296093484 # num instructions producing a value -system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value +system.cpu.iew.exec_nop 7967 # number of nop insts executed +system.cpu.iew.exec_refs 762799722 # number of memory reference insts executed +system.cpu.iew.exec_branches 238022734 # Number of branches executed +system.cpu.iew.exec_stores 190822699 # Number of stores executed +system.cpu.iew.exec_rate 2.166952 # Inst execution rate +system.cpu.iew.wb_sent 1965575614 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956580779 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296425776 # num instructions producing a value +system.cpu.iew.wb_consumers 2069436870 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back +system.cpu.iew.wb_rate 2.135837 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626463 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563091 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073903 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 466205393 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 180 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16072230 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841340863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.048009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.762269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352627350 41.91% 41.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193034897 22.94% 64.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73667996 8.76% 73.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35236864 4.19% 77.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18719576 2.22% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30675778 3.65% 83.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19663987 2.34% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10964014 1.30% 87.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106750401 12.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563084 # Number of instructions committed -system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 841340863 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563091 # Number of instructions committed +system.cpu.commit.committedOps 1723073903 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773829 # Number of memory references committed -system.cpu.commit.loads 485926777 # Number of loads committed +system.cpu.commit.refs 660773834 # Number of memory references committed +system.cpu.commit.loads 485926779 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462371 # Number of branches committed +system.cpu.commit.branches 213462373 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106750401 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2934966123 # The number of ROB reads -system.cpu.rob.rob_writes 4448699546 # The number of ROB writes -system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563066 # Number of Instructions Simulated -system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated -system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads -system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads -system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes -system.cpu.fp_regfile_reads 186 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads -system.cpu.misc_regfile_writes 138 # number of misc regfile writes -system.cpu.icache.replacements 28 # number of replacements -system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use -system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2923869159 # The number of ROB reads +system.cpu.rob.rob_writes 4445740607 # The number of ROB writes +system.cpu.timesIdled 753914 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7726751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563073 # Number of Instructions Simulated +system.cpu.committedOps 1723073885 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563073 # Number of Instructions Simulated +system.cpu.cpi 0.593095 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593095 # CPI: Total CPI of All Threads +system.cpu.ipc 1.686072 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.686072 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9944305109 # number of integer regfile reads +system.cpu.int_regfile_writes 1936656463 # number of integer regfile writes +system.cpu.fp_regfile_reads 139 # number of floating regfile reads +system.cpu.fp_regfile_writes 147 # number of floating regfile writes +system.cpu.misc_regfile_reads 2896410924 # number of misc regfile reads +system.cpu.misc_regfile_writes 144 # number of misc regfile writes +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 627.053723 # Cycle average of tags in use +system.cpu.icache.total_refs 283464725 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361101.560510 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits -system.cpu.icache.overall_hits::total 283729068 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses -system.cpu.icache.overall_misses::total 1197 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.053723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306179 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306179 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283464725 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283464725 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283464725 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283464725 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283464725 # number of overall hits +system.cpu.icache.overall_hits::total 283464725 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1148 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1148 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1148 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1148 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1148 # number of overall misses +system.cpu.icache.overall_misses::total 1148 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38598000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283465873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283465873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283465873 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283465873 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283465873 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283465873 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33621.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33621.951220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,309 +401,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27001000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27001000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27001000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27001000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27001000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27001000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34396.178344 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34396.178344 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34396.178344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34396.178344 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619302 # number of replacements -system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use -system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits -system.cpu.dcache.overall_hits::total 660726507 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses +system.cpu.dcache.replacements 9618836 # number of replacements +system.cpu.dcache.tagsinuse 4087.631943 # Cycle average of tags in use +system.cpu.dcache.total_refs 660703184 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9622932 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.659239 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3346369000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.631943 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997957 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493290864 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493290864 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167412157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167412157 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 92 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 92 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 71 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 71 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660703021 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660703021 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660703021 # number of overall hits +system.cpu.dcache.overall_hits::total 660703021 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10330521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10330521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5173890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5173890 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses -system.cpu.dcache.overall_misses::total 15901577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 15504411 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15504411 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15504411 # number of overall misses +system.cpu.dcache.overall_misses::total 15504411 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 163224239500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 163224239500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124852568337 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124852568337 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 288076807837 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 288076807837 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 288076807837 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 288076807837 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 503621385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 503621385 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 95 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 95 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 71 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 71 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676207432 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676207432 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676207432 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676207432 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029979 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029979 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031579 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031579 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022928 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022928 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022928 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022928 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15800.194346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15800.194346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24131.276146 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24131.276146 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18580.312908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18580.312908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18580.312908 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 200292336 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 119500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73738 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2716.270254 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14937.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks -system.cpu.dcache.writebacks::total 3133684 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473805 # number of writebacks +system.cpu.dcache.writebacks::total 3473805 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2601467 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2601467 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3280012 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3280012 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 5881479 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5881479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5881479 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5881479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729054 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121751862249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 121751862249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121751862249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 121751862249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015347 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015347 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612172 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612927 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830934 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830934 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2443106 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443861 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2443106 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443861 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50285384000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 50308930000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26141067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26141067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76426451500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 76449997500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76426451500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 76449997500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208586 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208662 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438747 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438747 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253941 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253884 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253941 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index b103ca45f..e60a29e1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 4559b3892..5ff891bb9 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:41:45 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:21:22 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 861538205000 because target called exit() +Exiting @ tick 861538200000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 6c3e8b909..9f9278806 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.861538 # Number of seconds simulated -sim_ticks 861538205000 # Number of ticks simulated -final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 861538200000 # Number of ticks simulated +final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2187855 # Simulator instruction rate (inst/s) -host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220358665 # Simulator tick rate (ticks/s) -host_mem_usage 221416 # Number of bytes of host memory used -host_seconds 705.97 # Real time elapsed on the host -sim_insts 1544563049 # Number of instructions simulated -sim_ops 1723073862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory -system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory +host_inst_rate 3167213 # Simulator instruction rate (inst/s) +host_op_rate 3533259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1766632085 # Simulator tick rate (ticks/s) +host_mem_usage 225200 # Number of bytes of host memory used +host_seconds 487.67 # Real time elapsed on the host +sim_insts 1544563041 # Number of instructions simulated +sim_ops 1723073853 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory +system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1723076411 # number of cpu cycles simulated +system.cpu.numCycles 1723076401 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563049 # Number of instructions committed -system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses +system.cpu.committedInsts 1544563041 # Number of instructions committed +system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written +system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions +system.cpu.num_mem_refs 660773815 # number of memory refs +system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1723076411 # Number of busy cycles +system.cpu.num_busy_cycles 1723076401 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 88ea9515a..e66f558e0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index d07a6ceff..4ec39cba0 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:44:07 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:25:17 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2431419954000 because target called exit() +Exiting @ tick 2408512388000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index db0ae235a..c9d66243a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.431420 # Number of seconds simulated -sim_ticks 2431419954000 # Number of ticks simulated -final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.408512 # Number of seconds simulated +sim_ticks 2408512388000 # Number of ticks simulated +final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1031283 # Simulator instruction rate (inst/s) -host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1629547552 # Simulator tick rate (ticks/s) -host_mem_usage 230584 # Number of bytes of host memory used -host_seconds 1492.08 # Real time elapsed on the host -sim_insts 1538759609 # Number of instructions simulated -sim_ops 1717270343 # Number of ops (including micro ops) simulated +host_inst_rate 1431405 # Simulator instruction rate (inst/s) +host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2240478292 # Simulator tick rate (ticks/s) +host_mem_usage 233776 # Number of bytes of host memory used +host_seconds 1075.00 # Real time elapsed on the host +sim_insts 1538759601 # Number of instructions simulated +sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory -system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory +system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory -system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory +system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4862839908 # number of cpu cycles simulated +system.cpu.numCycles 4817024776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759609 # Number of instructions committed -system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses +system.cpu.committedInsts 1538759601 # Number of instructions committed +system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written +system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions +system.cpu.num_mem_refs 660773815 # number of memory refs +system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4862839908 # Number of busy cycles +system.cpu.num_busy_cycles 4817024776 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 515.022606 # Cycle average of tags in use +system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits -system.cpu.icache.overall_hits::total 1544564961 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 515.022606 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251476 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251476 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits +system.cpu.icache.overall_hits::total 1544564952 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses @@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34804000 system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses @@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use +system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits +system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.603265 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996973 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits -system.cpu.dcache.overall_hits::total 645854938 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits +system.cpu.dcache.overall_hits::total 645854937 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 158470312000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59587262000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59587262000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218057574000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218057574000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218057574000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218057574000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks -system.cpu.dcache.writebacks::total 3061985 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks +system.cpu.dcache.writebacks::total 3385547 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136792051000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53919815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53919815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190711866000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190711866000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190711866000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190711866000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.307786 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.307786 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28541.854031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28541.854031 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.317974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.317974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2687066 # number of replacements -system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2138446 # number of replacements +system.cpu.l2cache.tagsinuse 30628.680390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 437045285000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14782.399882 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.716042 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.564466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.451123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.483110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.934713 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6961801 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961823 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits -system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 6961801 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961823 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1364407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1365023 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 789028 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 789028 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2153435 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2154051 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses -system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses +system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3385547 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses @@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188817 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188885 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417663 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.236246 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.236297 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks -system.cpu.l2cache.writebacks::total 1171980 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks +system.cpu.l2cache.writebacks::total 1050331 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1364407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1365023 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 5c77a44a2..643e6799d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 11192711e..5dc44ec4f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 16:08:32 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:47:42 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5923548078000 because target called exit() +Exiting @ tick 5900695290000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e2cb03bbf..faa206e56 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.923548 # Number of seconds simulated -sim_ticks 5923548078000 # Number of ticks simulated -final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.900695 # Number of seconds simulated +sim_ticks 5900695290000 # Number of ticks simulated +final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 633731 # Simulator instruction rate (inst/s) -host_op_rate 987410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1247949692 # Simulator tick rate (ticks/s) -host_mem_usage 225520 # Number of bytes of host memory used -host_seconds 4746.62 # Real time elapsed on the host +host_inst_rate 1070782 # Simulator instruction rate (inst/s) +host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2100461088 # Simulator tick rate (ticks/s) +host_mem_usage 228516 # Number of bytes of host memory used +host_seconds 2809.24 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory -system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory +system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory -system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory +system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11847096156 # number of cpu cycles simulated +system.cpu.numCycles 11801390580 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081057 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713086 # nu system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11847096156 # Number of busy cycles +system.cpu.num_busy_cycles 11801390580 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks -system.cpu.dcache.writebacks::total 3053391 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks +system.cpu.dcache.writebacks::total 3375759 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2706631 # number of replacements -system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits -system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits +system.cpu.l2cache.replacements 2158210 # number of replacements +system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16168.397523 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.447434 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.493420 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941513 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3375759 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1099986 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1099986 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6940121 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6940121 # 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number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2717345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2172556 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2173231 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2716670 # number of overall misses -system.cpu.l2cache.overall_misses::total 2717345 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses +system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94947840000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94982940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46319000000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71936280000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071732000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41071732000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 141301940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112972912000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113008012000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 141301940000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112972912000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113008012000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3053391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3053391 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3375759 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3375759 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses @@ -294,16 +294,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 675 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.252868 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.191436 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191512 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417944 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417944 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.298172 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.238410 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.238467 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.298172 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks -system.cpu.l2cache.writebacks::total 1174631 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks +system.cpu.l2cache.writebacks::total 1053029 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1382715 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1383390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789841 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 789841 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2172556 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593640000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86929240000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86929240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.252868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.298172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.298172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 0cab3c39f..4aef8f4de 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index c65e040d8..926d51412 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:52:53 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:37:18 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index a7912f8e0..60e11bdef 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106867 # Simulator instruction rate (inst/s) -host_op_rate 106867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48844875 # Simulator tick rate (ticks/s) -host_mem_usage 218932 # Number of bytes of host memory used -host_seconds 859.98 # Real time elapsed on the host +host_inst_rate 160903 # Simulator instruction rate (inst/s) +host_op_rate 160903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73542430 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 571.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -322,9 +322,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 7269 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.214808 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index f02146b21..d1830cc83 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 11770df5a..157ee9690 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:06:35 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:41:57 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23638033500 because target called exit() +122 123 124 Exiting @ tick 23635060000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 5f8b8cbb4..42e01362d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023638 # Number of seconds simulated -sim_ticks 23638033500 # Number of ticks simulated -final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023635 # Number of seconds simulated +sim_ticks 23635060000 # Number of ticks simulated +final_tick 23635060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160213 # Simulator instruction rate (inst/s) -host_op_rate 160213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44988546 # Simulator tick rate (ticks/s) -host_mem_usage 220112 # Number of bytes of host memory used -host_seconds 525.42 # Real time elapsed on the host +host_inst_rate 242450 # Simulator instruction rate (inst/s) +host_op_rate 242450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68072464 # Simulator tick rate (ticks/s) +host_mem_usage 223772 # Number of bytes of host memory used +host_seconds 347.20 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138112 # Number of bytes read from this memory -system.physmem.bytes_read::total 336064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197952 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8374301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5842787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14217088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8374301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5842787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14217088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 335744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8345568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5859769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14205337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8345568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8345568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8345568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5859769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14205337 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23223377 # DTB read hits -system.cpu.dtb.read_misses 198479 # DTB read misses +system.cpu.dtb.read_hits 23228346 # DTB read hits +system.cpu.dtb.read_misses 200425 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 23421856 # DTB read accesses -system.cpu.dtb.write_hits 7079825 # DTB write hits -system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.read_accesses 23428771 # DTB read accesses +system.cpu.dtb.write_hits 7078031 # DTB write hits +system.cpu.dtb.write_misses 1393 # DTB write misses system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 7081228 # DTB write accesses -system.cpu.dtb.data_hits 30303202 # DTB hits -system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.write_accesses 7079424 # DTB write accesses +system.cpu.dtb.data_hits 30306377 # DTB hits +system.cpu.dtb.data_misses 201818 # DTB misses system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30503084 # DTB accesses -system.cpu.itb.fetch_hits 14943347 # ITB hits -system.cpu.itb.fetch_misses 91 # ITB misses +system.cpu.dtb.data_accesses 30508195 # DTB accesses +system.cpu.itb.fetch_hits 14951144 # ITB hits +system.cpu.itb.fetch_misses 107 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14943438 # ITB accesses +system.cpu.itb.fetch_accesses 14951251 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47276068 # number of cpu cycles simulated +system.cpu.numCycles 47270121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits +system.cpu.BPredUnit.lookups 15030146 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10897396 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964237 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8689796 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7074632 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1488592 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3325 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15628273 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128247685 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15030146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8563224 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22387448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4637135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5522059 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1901 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14951144 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336879 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47178795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.718333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24791347 52.55% 52.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2391230 5.07% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207932 2.56% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776893 3.77% 63.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2805490 5.95% 69.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1170846 2.48% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228782 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789170 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11017105 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47178795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317963 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.713081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17466562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4227162 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20770000 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1087804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3627267 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2544055 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12184 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125158453 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31894 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3627267 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18628524 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8367 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20673426 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3280961 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122187472 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401237 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2407508 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89717314 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158683253 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148939266 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743987 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21289953 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1139 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1148 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8701053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25559054 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8299979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2600508 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 916071 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106169681 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2314 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96996119 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 187372 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21529768 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16156839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47178795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055926 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12439775 26.37% 26.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9421207 19.97% 46.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8463269 17.94% 64.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6318044 13.39% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948438 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2848262 6.04% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1729160 3.67% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 800900 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209740 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47178795 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186062 11.86% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 228 0.01% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7118 0.45% 12.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5890 0.38% 12.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842932 53.71% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 447788 28.53% 94.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79372 5.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58995521 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480822 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802067 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115555 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385721 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311403 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759596 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23975443 24.72% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7169665 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued -system.cpu.iq.rate 2.051269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96996119 # Type of FU issued +system.cpu.iq.rate 2.051954 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1569390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016180 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227797779 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118919368 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87372371 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130016 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8817376 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7067715 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90571077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994425 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518936 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5562856 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19876 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1798876 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10509 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3627267 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134249 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17377 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116472912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393481 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25559054 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8299979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2314 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2868 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569232 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508759 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1077991 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95699624 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23429474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1296495 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10296358 # number of nop insts executed -system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076445 # Number of branches executed -system.cpu.iew.exec_stores 7081427 # Number of stores executed -system.cpu.iew.exec_rate 2.023822 # Inst execution rate -system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64608180 # num instructions producing a value -system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value +system.cpu.iew.exec_nop 10300917 # number of nop insts executed +system.cpu.iew.exec_refs 30509089 # number of memory reference insts executed +system.cpu.iew.exec_branches 12078604 # Number of branches executed +system.cpu.iew.exec_stores 7079615 # Number of stores executed +system.cpu.iew.exec_rate 2.024527 # Inst execution rate +system.cpu.iew.wb_sent 94984897 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94440086 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64627368 # num instructions producing a value +system.cpu.iew.wb_consumers 90016132 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997881 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717953 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24570867 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43551528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.110214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736227 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17031202 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9950887 22.85% 61.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4509538 10.35% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2291714 5.26% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1611645 3.70% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125442 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722499 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 819642 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5488959 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43551528 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5488959 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154514159 # The number of ROB reads -system.cpu.rob.rob_writes 236533126 # The number of ROB writes -system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154535451 # The number of ROB reads +system.cpu.rob.rob_writes 236599608 # The number of ROB writes +system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 91326 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129442497 # number of integer regfile reads -system.cpu.int_regfile_writes 70765525 # number of integer regfile writes -system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads -system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes -system.cpu.misc_regfile_reads 714278 # number of misc regfile reads +system.cpu.cpi 0.561538 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561538 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129477590 # number of integer regfile reads +system.cpu.int_regfile_writes 70782663 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191536 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049328 # number of floating regfile writes +system.cpu.misc_regfile_reads 714291 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10359 # number of replacements -system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use -system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. +system.cpu.icache.replacements 10215 # number of replacements +system.cpu.icache.tagsinuse 1600.385722 # Cycle average of tags in use +system.cpu.icache.total_refs 14937616 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12152 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1229.231073 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits -system.cpu.icache.overall_hits::total 14929668 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses -system.cpu.icache.overall_misses::total 13679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14911.104613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14911.104613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14911.104613 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1600.385722 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.781438 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.781438 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14937616 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14937616 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14937616 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14937616 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14937616 # number of overall hits +system.cpu.icache.overall_hits::total 14937616 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13528 # number of overall misses +system.cpu.icache.overall_misses::total 13528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201479500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201479500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201479500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201479500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201479500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201479500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14951144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14951144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14951144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14951144 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14951144 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14951144 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000823 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000823 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10645.319997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10645.319997 # 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Cycle average of tags in use -system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.321585 # Cycle average of tags in use +system.cpu.dcache.total_refs 28191010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12562.838681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001240 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001240 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001901 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001901 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30077.695560 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35913.531968 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29879.014989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29879.014989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35997.704430 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35997.704430 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35300.188868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35300.188868 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35362.226176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35362.226176 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34332.723177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34718.823529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34457.722339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34457.722339 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1730 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984971 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.364407 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.364407 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34325.275795 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34418.478261 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34337.380011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34740.903756 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34740.903756 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34468.452154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34468.452154 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277227 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.361266 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.361266 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.451704 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31549.411765 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3542 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1704 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1704 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5246 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5246 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95761000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14382500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110143500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53772000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53772000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95761000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68154500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 163915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95761000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68154500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 163915500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279646 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984971 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984971 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364407 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364407 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31071.057755 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31266.304348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.414455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31556.338028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31556.338028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 39023eb08..7fbc3a2c7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 3fe1e7489..0bb9be5b6 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:18:52 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:47:30 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 5d71f2054..b947ca514 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1590844 # Simulator instruction rate (inst/s) -host_op_rate 1590843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2055391195 # Simulator tick rate (ticks/s) -host_mem_usage 218628 # Number of bytes of host memory used -host_seconds 57.77 # Real time elapsed on the host +host_inst_rate 2205371 # Simulator instruction rate (inst/s) +host_op_rate 2205370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2849367775 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 41.67 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 292cbefed..bf679d420 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index f8119727b..6b424cab1 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:52:11 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:29:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76322764500 because target called exit() +122 123 124 Exiting @ tick 76049800000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 15323b4b4..a9dc709bb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076323 # Number of seconds simulated -sim_ticks 76322764500 # Number of ticks simulated -final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076050 # Number of seconds simulated +sim_ticks 76049800000 # Number of ticks simulated +final_tick 76049800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95790 # Simulator instruction rate (inst/s) -host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42423254 # Simulator tick rate (ticks/s) -host_mem_usage 235620 # Number of bytes of host memory used -host_seconds 1799.08 # Real time elapsed on the host -sim_insts 172333279 # Number of instructions simulated -sim_ops 188686762 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory -system.physmem.bytes_read::total 246592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 156056 # Simulator instruction rate (inst/s) +host_op_rate 170865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68866655 # Simulator tick rate (ticks/s) +host_mem_usage 238096 # Number of bytes of host memory used +host_seconds 1104.31 # Real time elapsed on the host +sim_insts 172333196 # Number of instructions simulated +sim_ops 188686678 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112128 # Number of bytes read from this memory +system.physmem.bytes_read::total 244544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1752 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3821 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1741175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1474402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3215577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1741175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1474402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3215577 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +70,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152645530 # number of cpu cycles simulated +system.cpu.numCycles 152099601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits +system.cpu.BPredUnit.lookups 96837963 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76071776 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6557528 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46441082 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44202196 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4477911 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40623947 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388565051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96837963 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48680107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82289244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28490098 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220589 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8612 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37659031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1889609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69920012 45.99% 45.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5487559 3.61% 49.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10685692 7.03% 56.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10438123 6.87% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8795207 5.78% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6832085 4.49% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6301825 4.14% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8365502 5.50% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25213584 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.636675 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46670430 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5932664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76574160 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1118361 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21743974 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14821262 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162795 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401681988 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736800 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21743974 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52193760 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 715909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 791714 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72108942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4485290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 379159906 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 316677 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3600241 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642535255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1615137204 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1597539210 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17597994 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092419 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344442836 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 52677 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12879836 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44010443 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16892323 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5849879 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3738879 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334925831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74527 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252866200 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 897062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145077714 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 374156671 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152039589 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.663160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.758894 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58521655 38.49% 38.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23034636 15.15% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25191735 16.57% 70.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20480082 13.47% 83.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12877411 8.47% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6577788 4.33% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4065173 2.67% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110646 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180463 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152039589 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 967418 37.56% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5599 0.22% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 146 0.01% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 21 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198100 46.52% 84.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 404230 15.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197377765 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 996285 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,169 +224,169 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33143 0.01% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164246 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255557 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76455 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467877 0.19% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206463 0.08% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39025783 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14190441 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued -system.cpu.iq.rate 1.659274 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252866200 # Type of FU issued +system.cpu.iq.rate 1.662504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2575514 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657470724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477849498 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240611060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3773841 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2247636 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852910 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253547208 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894506 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2021626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14154924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19840 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4241654 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21743974 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 622 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 335058586 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 832362 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44010443 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16892323 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51985 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 162 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19840 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4108839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3946041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8054880 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245860683 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37402341 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7005517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 58893 # number of nop insts executed -system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed -system.cpu.iew.exec_branches 54101167 # Number of branches executed -system.cpu.iew.exec_stores 13816344 # Number of stores executed -system.cpu.iew.exec_rate 1.612486 # Inst execution rate -system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150184249 # num instructions producing a value -system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value +system.cpu.iew.exec_nop 58228 # number of nop insts executed +system.cpu.iew.exec_refs 51211338 # number of memory reference insts executed +system.cpu.iew.exec_branches 54022808 # Number of branches executed +system.cpu.iew.exec_stores 13808997 # Number of stores executed +system.cpu.iew.exec_rate 1.616445 # Inst execution rate +system.cpu.iew.wb_sent 243598204 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242463970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150083518 # num instructions producing a value +system.cpu.iew.wb_consumers 269173561 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.594113 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172347584 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188701066 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146357504 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51251 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6423604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130295616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.448253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.160604 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 60033353 46.07% 46.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32093498 24.63% 70.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14006031 10.75% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7653781 5.87% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4421161 3.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1332201 1.02% 91.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737103 1.33% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1282008 0.98% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7736480 5.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347667 # Number of instructions committed -system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130295616 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347584 # Number of instructions committed +system.cpu.commit.committedOps 188701066 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506219 # Number of memory references committed -system.cpu.commit.loads 29855535 # Number of loads committed +system.cpu.commit.refs 42506188 # Number of memory references committed +system.cpu.commit.loads 29855519 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40287733 # Number of branches committed +system.cpu.commit.branches 40287717 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130425 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130357 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7736480 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458778355 # The number of ROB reads -system.cpu.rob.rob_writes 693498788 # The number of ROB writes -system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333279 # Number of Instructions Simulated -system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated -system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads -system.cpu.int_regfile_writes 388952433 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes -system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads -system.cpu.misc_regfile_writes 832136 # number of misc regfile writes -system.cpu.icache.replacements 2645 # number of replacements -system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use -system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457612505 # The number of ROB reads +system.cpu.rob.rob_writes 691979598 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60012 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333196 # Number of Instructions Simulated +system.cpu.committedOps 188686678 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333196 # Number of Instructions Simulated +system.cpu.cpi 0.882590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133029 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133029 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092071141 # number of integer regfile reads +system.cpu.int_regfile_writes 388656879 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914235 # number of floating regfile reads +system.cpu.fp_regfile_writes 2512527 # number of floating regfile writes +system.cpu.misc_regfile_reads 474801777 # number of misc regfile reads +system.cpu.misc_regfile_writes 832106 # number of misc regfile writes +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.tagsinuse 1365.085421 # Cycle average of tags in use +system.cpu.icache.total_refs 37653918 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8680.017981 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits -system.cpu.icache.overall_hits::total 37836261 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses -system.cpu.icache.overall_misses::total 5199 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1365.085421 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.666546 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.666546 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37653921 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37653921 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37653921 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37653921 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37653921 # number of overall hits +system.cpu.icache.overall_hits::total 37653921 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5110 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5110 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5110 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5110 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5110 # number of overall misses +system.cpu.icache.overall_misses::total 5110 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 111334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 111334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 111334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 111334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37659031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37659031 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21787.475538 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,246 +395,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 804 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 768 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4342 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4342 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4342 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4342 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78323000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78323000 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use -system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1413.439257 # Cycle average of tags in use +system.cpu.dcache.total_refs 47316793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25370.934584 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits -system.cpu.dcache.overall_hits::total 47275886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1413.439257 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345078 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345078 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47267977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47267977 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47267977 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47267977 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31501.642297 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34317.044566 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,59 +647,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 677 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1752 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3821 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1752 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3821 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64256500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21124000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33377000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33377000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118757500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64256500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118757500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866837 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.536223 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.615794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.615794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index b72ac514a..337b40f6d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 18d32cd6b..887de4fb8 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:53:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:29:40 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 103106771000 because target called exit() +122 123 124 Exiting @ tick 103106766000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index bbd6c00f1..0e78b9612 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.103107 # Number of seconds simulated -sim_ticks 103106771000 # Number of ticks simulated -final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 103106766000 # Number of ticks simulated +final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2060024 # Simulator instruction rate (inst/s) -host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1232622542 # Simulator tick rate (ticks/s) -host_mem_usage 224496 # Number of bytes of host memory used -host_seconds 83.65 # Real time elapsed on the host -sim_insts 172317417 # Number of instructions simulated -sim_ops 188670900 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory +host_inst_rate 3148564 # Simulator instruction rate (inst/s) +host_op_rate 3447371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1883953687 # Simulator tick rate (ticks/s) +host_mem_usage 227464 # Number of bytes of host memory used +host_seconds 54.73 # Real time elapsed on the host +sim_insts 172317409 # Number of instructions simulated +sim_ops 188670891 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 206213543 # number of cpu cycles simulated +system.cpu.numCycles 206213533 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317417 # Number of instructions committed -system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.committedInsts 172317409 # Number of instructions committed +system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written +system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494120 # number of memory refs -system.cpu.num_load_insts 29849485 # Number of load instructions +system.cpu.num_mem_refs 42494119 # number of memory refs +system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 206213543 # Number of busy cycles +system.cpu.num_busy_cycles 206213533 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 3e3d3dcbe..7a871da2f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 08e4c719e..0e8fdda90 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:54:15 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:30:46 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 232077154000 because target called exit() +122 123 124 Exiting @ tick 232077144000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 1e695b431..4c3bb52b8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.232077 # Number of seconds simulated -sim_ticks 232077154000 # Number of ticks simulated -final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 232077144000 # Number of ticks simulated +final_tick 232077144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665536 # Simulator instruction rate (inst/s) -host_op_rate 728833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898821179 # Simulator tick rate (ticks/s) -host_mem_usage 233632 # Number of bytes of host memory used -host_seconds 258.20 # Real time elapsed on the host -sim_insts 171842491 # Number of instructions simulated -sim_ops 188185929 # Number of ops (including micro ops) simulated +host_inst_rate 1482014 # Simulator instruction rate (inst/s) +host_op_rate 1622964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2001492603 # Simulator tick rate (ticks/s) +host_mem_usage 236052 # Number of bytes of host memory used +host_seconds 115.95 # Real time elapsed on the host +sim_insts 171842483 # Number of instructions simulated +sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464154308 # number of cpu cycles simulated +system.cpu.numCycles 464154288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842491 # Number of instructions committed -system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.committedInsts 171842483 # Number of instructions committed +system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3504894 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written +system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494120 # number of memory refs -system.cpu.num_load_insts 29849485 # Number of load instructions +system.cpu.num_mem_refs 42494119 # number of memory refs +system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464154308 # Number of busy cycles +system.cpu.num_busy_cycles 464154288 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.981155 # Cycle average of tags in use -system.cpu.icache.total_refs 189857010 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1147.981203 # Cycle average of tags in use +system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1147.981203 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits -system.cpu.icache.overall_hits::total 189857010 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits +system.cpu.icache.overall_hits::total 189857001 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses @@ -119,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 115332000 system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007359 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1363.604373 # Cycle average of tags in use +system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.916154 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.604315 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1363.604373 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.332911 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.332911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 29599358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 29599358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41962545 # number of overall hits -system.cpu.dcache.overall_hits::total 41962545 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits +system.cpu.dcache.overall_hits::total 41962544 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 97454000 system.cpu.dcache.demand_miss_latency::total 97454000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 97454000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 97454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 29600047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 29600047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41964334 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41964334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1675.648101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582102 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 3.038048 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.027734 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.582248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.027783 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.582269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 1b6b8f01a..24899e6d1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index e9982c78d..34329ed9e 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 16:25:20 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:01:11 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87751730000 because target called exit() +122 123 124 Exiting @ tick 87734048000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 9505812e4..963d9307c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,272 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087752 # Number of seconds simulated -sim_ticks 87751730000 # Number of ticks simulated -final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087734 # Number of seconds simulated +sim_ticks 87734048000 # Number of ticks simulated +final_tick 87734048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66952 # Simulator instruction rate (inst/s) -host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44484510 # Simulator tick rate (ticks/s) -host_mem_usage 236376 # Number of bytes of host memory used -host_seconds 1972.64 # Real time elapsed on the host +host_inst_rate 104988 # Simulator instruction rate (inst/s) +host_op_rate 175969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69742772 # Simulator tick rate (ticks/s) +host_mem_usage 239080 # Number of bytes of host memory used +host_seconds 1257.97 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory system.physmem.bytes_read::total 345024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 219520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2502107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1430505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3932612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2502107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2502107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2502107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1430505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3932612 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175503461 # number of cpu cycles simulated +system.cpu.numCycles 175468097 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20929970 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20929970 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2208761 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15515509 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13857635 # Number of BTB hits +system.cpu.BPredUnit.lookups 20936810 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20936810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209025 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15519452 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13863485 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27320294 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 226942709 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20929970 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13857635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59854483 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19459786 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71271521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5211 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25822554 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 471165 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175426420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.136612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.300359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27317448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 226954156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20936810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13863485 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59860939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19465594 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71226359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7164 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25821692 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175391237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.300907 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117249103 66.84% 66.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3234615 1.84% 68.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2477718 1.41% 70.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3147881 1.79% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3542128 2.02% 73.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3766355 2.15% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4530628 2.58% 78.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2823565 1.61% 80.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34654427 19.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117206877 66.83% 66.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3231358 1.84% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2482815 1.42% 70.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3136542 1.79% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3542923 2.02% 73.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3767949 2.15% 76.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4531829 2.58% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2825666 1.61% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34665278 19.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175426420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119257 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.293095 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40654970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 61059749 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46547974 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10189463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16974264 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365977737 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16974264 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48548849 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16319097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23046 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48140036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45421128 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356799059 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20636040 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22537767 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2198 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 506554560 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130537584 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120266837 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10270747 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175391237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119320 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.293421 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40660130 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 61009372 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46541390 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10201855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16978490 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366073396 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16978490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48547252 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16251189 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23056 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48155491 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45435759 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356858942 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20674050 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22523448 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2249 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 506627728 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1130775437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1120479419 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10296018 # Number of floating rename lookups system.cpu.rename.CommittedMaps 320143989 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186410571 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1911 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1906 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95097015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89808446 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33130186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59201466 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19519303 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344515408 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 270869041 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 254270 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122674827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 297005948 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6596 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175426420 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.544061 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.467197 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 186483739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1903 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1897 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95061023 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89836107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126554 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59108509 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19466725 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344545895 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7937 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 270906839 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 256776 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122697293 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 297019638 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6691 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175391237 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.544586 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467556 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49131919 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52597597 29.98% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34344440 19.58% 77.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18981960 10.82% 88.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12711399 7.25% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4926918 2.81% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2079867 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 541264 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111056 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49119269 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52565616 29.97% 57.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34331484 19.57% 77.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18982131 10.82% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12721464 7.25% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4942775 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2076613 1.18% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542627 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 109258 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175426420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175391237 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91065 3.49% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2241508 85.86% 89.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277930 10.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90563 3.50% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2225289 85.92% 89.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 273998 10.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212815 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176257528 65.07% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1592327 0.59% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68300084 25.22% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23506287 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212985 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176266302 65.07% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1595268 0.59% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68329319 25.22% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23502965 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 270869041 # Type of FU issued -system.cpu.iq.rate 1.543383 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2610503 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009638 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714724682 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 462639790 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263265519 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5304593 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4857798 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2549095 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269608691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2658038 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18925158 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 270906839 # Type of FU issued +system.cpu.iq.rate 1.543909 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2589850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009560 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714739567 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462675137 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263287653 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5311974 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4876750 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553148 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269622080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2661624 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18915593 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33158856 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30567 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 304625 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12614470 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33186517 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 305892 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47486 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47515 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16974264 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 523635 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 253200 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344523250 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297274 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89808446 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33130186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 168556 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 304625 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298513 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1028751 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2327264 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 267763849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67223329 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3105192 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16978490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 517280 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 233874 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344553832 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297077 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89836107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126554 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1857 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147591 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33364 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 305892 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1298592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028927 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2327519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267790575 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67240366 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3116264 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90337843 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773998 # Number of branches executed -system.cpu.iew.exec_stores 23114514 # Number of stores executed -system.cpu.iew.exec_rate 1.525690 # Inst execution rate -system.cpu.iew.wb_sent 266689649 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 265814614 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214459238 # num instructions producing a value -system.cpu.iew.wb_consumers 504388652 # num instructions consuming a value +system.cpu.iew.exec_refs 90351837 # number of memory reference insts executed +system.cpu.iew.exec_branches 14775060 # Number of branches executed +system.cpu.iew.exec_stores 23111471 # Number of stores executed +system.cpu.iew.exec_rate 1.526150 # Inst execution rate +system.cpu.iew.wb_sent 266714598 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265840801 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214478617 # num instructions producing a value +system.cpu.iew.wb_consumers 504376698 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.514583 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425186 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.425235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123271968 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123301880 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2209353 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158452156 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.794480 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2209791 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158412747 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.795092 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54225216 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60443910 38.15% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15544008 9.81% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12710691 8.02% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4546278 2.87% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2974927 1.88% 94.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2086566 1.32% 96.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1244605 0.79% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4675955 2.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54206628 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60400758 38.13% 72.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15586261 9.84% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12707072 8.02% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4534557 2.86% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2957745 1.87% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2082808 1.31% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1250624 0.79% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4686294 2.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158452156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158412747 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,70 +277,70 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4675955 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4686294 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498411186 # The number of ROB reads -system.cpu.rob.rob_writes 706281673 # The number of ROB writes -system.cpu.timesIdled 1684 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 77041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498391350 # The number of ROB reads +system.cpu.rob.rob_writes 706346628 # The number of ROB writes +system.cpu.timesIdled 1678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76860 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.328855 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328855 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752528 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752528 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657510098 # number of integer regfile reads -system.cpu.int_regfile_writes 365370199 # number of integer regfile writes -system.cpu.fp_regfile_reads 3509073 # number of floating regfile reads -system.cpu.fp_regfile_writes 2221147 # number of floating regfile writes -system.cpu.misc_regfile_reads 139423581 # number of misc regfile reads +system.cpu.cpi 1.328587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752679 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752679 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 657568441 # number of integer regfile reads +system.cpu.int_regfile_writes 365395599 # number of integer regfile writes +system.cpu.fp_regfile_reads 3514318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2225520 # number of floating regfile writes +system.cpu.misc_regfile_reads 139440665 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5601 # number of replacements -system.cpu.icache.tagsinuse 1627.936468 # Cycle average of tags in use -system.cpu.icache.total_refs 25813461 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7571 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3409.518029 # Average number of references to valid blocks. +system.cpu.icache.replacements 5526 # number of replacements +system.cpu.icache.tagsinuse 1631.257386 # Cycle average of tags in use +system.cpu.icache.total_refs 25812694 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7496 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3443.529082 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1627.936468 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.794891 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.794891 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25813461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25813461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25813461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25813461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25813461 # number of overall hits -system.cpu.icache.overall_hits::total 25813461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9093 # number of overall misses -system.cpu.icache.overall_misses::total 9093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 187306000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 187306000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 187306000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 187306000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 187306000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 187306000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25822554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25822554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25822554 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25822554 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.257386 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796512 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796512 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25812694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25812694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25812694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25812694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25812694 # number of overall hits +system.cpu.icache.overall_hits::total 25812694 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25821692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25821692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25821692 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25821692 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25821692 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25821692 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000348 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000348 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000348 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000348 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000348 # 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Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34372.607912 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1425.887115 # Cycle average of tags in use +system.cpu.dcache.total_refs 68669194 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34368.965966 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1426.584624 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.348287 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.348287 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48127880 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2488 # number of overall misses -system.cpu.dcache.overall_misses::total 2488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24823500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24823500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65115000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65115000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89938500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89938500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89938500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89938500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48128652 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48128652 # 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number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3431 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5391 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106440500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12676500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119117000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4805000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4805000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106414500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12709500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119124000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4433000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4433000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48110500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106440500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167227500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106440500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106414500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167234500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106414500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167234500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929705 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.483810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.567713 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.457577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.567713 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 3d56f1a99..168d19d0f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 3bc28071d..c17116a39 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 17:00:16 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 29 2012 00:23:42 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 8ebc5f697..8e544f41c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 653434 # Simulator instruction rate (inst/s) -host_op_rate 1095213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241649233 # Simulator tick rate (ticks/s) -host_mem_usage 232776 # Number of bytes of host memory used -host_seconds 202.12 # Real time elapsed on the host +host_inst_rate 1047161 # Simulator instruction rate (inst/s) +host_op_rate 1755134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1989805633 # Simulator tick rate (ticks/s) +host_mem_usage 234988 # Number of bytes of host memory used +host_seconds 126.12 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -230,9 +230,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 06d87b670..86d337feb 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:49 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:04 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b45122ce6..046013e55 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,167 +4,167 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2870976 # Simulator instruction rate (inst/s) -host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85025108641 # Simulator tick rate (ticks/s) -host_mem_usage 298608 # Number of bytes of host memory used -host_seconds 22.00 # Real time elapsed on the host +host_inst_rate 4061827 # Simulator instruction rate (inst/s) +host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120292600618 # Simulator tick rate (ticks/s) +host_mem_usage 301032 # Number of bytes of host memory used +host_seconds 15.55 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory -system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory -system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1051788 # number of replacements -system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use -system.l2c.total_refs 2341203 # Total number of references to valid blocks. -system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. -system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits -system.l2c.Writeback_hits::total 811846 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000626 # number of replacements +system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use +system.l2c.total_refs 2464692 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. +system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000305 # 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number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses -system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses -system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses -system.l2c.overall_misses::cpu1.data 12152 # number of overall misses -system.l2c.overall_misses::total 1088735 # number of overall misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses +system.l2c.overall_misses::cpu1.data 10570 # number of overall misses +system.l2c.overall_misses::total 1066665 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses +system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 121798 # number of writebacks -system.l2c.writebacks::total 121798 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41695 # number of replacements system.iocache.tagsinuse 0.435437 # Cycle average of tags in use @@ -451,39 +451,39 @@ system.cpu0.icache.cache_copies 0 # nu system.cpu0.icache.writebacks::writebacks 95 # number of writebacks system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978962 # number of replacements -system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978686 # number of replacements +system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # 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Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) @@ -496,18 +496,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14729930 system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +516,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks -system.cpu0.dcache.writebacks::total 771740 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks +system.cpu0.dcache.writebacks::total 775641 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -687,42 +687,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15 # number of writebacks -system.cpu1.icache.writebacks::total 15 # number of writebacks +system.cpu1.icache.writebacks::writebacks 18 # number of writebacks +system.cpu1.icache.writebacks::total 18 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62338 # number of replacements -system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses -system.cpu1.dcache.overall_misses::total 67511 # number of overall misses +system.cpu1.dcache.replacements 62044 # number of replacements +system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses +system.cpu1.dcache.overall_misses::total 67292 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -735,18 +735,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,8 +755,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks -system.cpu1.dcache.writebacks::total 39996 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks +system.cpu1.dcache.writebacks::total 41012 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 92dc7ad3d..d842316f6 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:23 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:03 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 4492aa0b0..e2a65cb45 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,109 +4,109 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2878195 # Simulator instruction rate (inst/s) -host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87696777763 # Simulator tick rate (ticks/s) -host_mem_usage 296144 # Number of bytes of host memory used -host_seconds 20.86 # Real time elapsed on the host +host_inst_rate 4017982 # Simulator instruction rate (inst/s) +host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122425314574 # Simulator tick rate (ticks/s) +host_mem_usage 297960 # Number of bytes of host memory used +host_seconds 14.94 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory -system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory -system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1045877 # number of replacements -system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use -system.l2c.total_refs 2291835 # Total number of references to valid blocks. -system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits -system.l2c.Writeback_hits::total 825291 # number of Writeback hits +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 992301 # number of replacements +system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use +system.l2c.total_refs 2433195 # Total number of references to valid blocks. +system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.300972 # Average number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits +system.l2c.Writeback_hits::total 833599 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits -system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 905267 # number of overall hits -system.l2c.overall_hits::cpu.data 979511 # number of overall hits -system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses -system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits +system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 906797 # number of overall hits +system.l2c.overall_hits::cpu.data 998308 # number of overall hits +system.l2c.overall_hits::total 1905105 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses -system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 14936 # number of overall misses -system.l2c.overall_misses::cpu.data 1063552 # number of overall misses -system.l2c.overall_misses::total 1078488 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13406 # number of overall misses +system.l2c.overall_misses::cpu.data 1044757 # number of overall misses +system.l2c.overall_misses::total 1058163 # number of overall misses system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -115,8 +115,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117189 # number of writebacks -system.l2c.writebacks::total 117189 # number of writebacks +system.l2c.writebacks::writebacks 74291 # number of writebacks +system.l2c.writebacks::total 74291 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use @@ -388,37 +388,37 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 108 # number of writebacks system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.replacements 2042702 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits -system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits +system.cpu.dcache.overall_hits::total 13655992 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses -system.cpu.dcache.overall_misses::total 2026067 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses +system.cpu.dcache.overall_misses::total 2026069 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) @@ -431,16 +431,16 @@ system.cpu.dcache.demand_accesses::cpu.data 15682061 # system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,8 +449,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks -system.cpu.dcache.writebacks::total 825183 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index b3456c80f..4abaeca9d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 -Exiting @ tick 1958647095000 because m5_exit instruction encountered +Exiting @ tick 1957577582000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e92359043..9611b47c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.958647 # Number of seconds simulated -sim_ticks 1958647095000 # Number of ticks simulated -final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.957578 # Number of seconds simulated +sim_ticks 1957577582000 # Number of ticks simulated +final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1245422 # Simulator instruction rate (inst/s) -host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41097010927 # Simulator tick rate (ticks/s) -host_mem_usage 295412 # Number of bytes of host memory used -host_seconds 47.66 # Real time elapsed on the host -sim_insts 59355643 # Number of instructions simulated -sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +host_inst_rate 1866861 # Simulator instruction rate (inst/s) +host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61595044213 # Simulator tick rate (ticks/s) +host_mem_usage 296940 # Number of bytes of host memory used +host_seconds 31.78 # Real time elapsed on the host +sim_insts 59331415 # Number of instructions simulated +sim_ops 59331415 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory -system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory -system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory -system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13254145 # 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mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_uncacheable_latency::total 802312500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122098500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269224500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1391323000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914196500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279439000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2193635500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260412 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005660 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137222 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.936617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.900000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930358 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.533333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.782609 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.721311 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401253 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.322403 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.396429 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170530 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170530 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.345955 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40208.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.753491 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.905830 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40012.345679 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40024.498129 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.363984 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.992228 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.295729 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.563721 # Cycle average of tags in use +system.iocache.tagsinuse 0.563379 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035233 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035233 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721783806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721783806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741836804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741836804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741836804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741836804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8633623 # DTB read hits +system.cpu0.dtb.read_hits 8630502 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6044743 # DTB write hits +system.cpu0.dtb.write_hits 6043026 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14678366 # DTB hits +system.cpu0.dtb.data_hits 14673528 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3853057 # ITB hits +system.cpu0.itb.fetch_hits 3852973 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856928 # ITB accesses +system.cpu0.itb.fetch_accesses 3856844 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numCycles 3914070794 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54072652 # Number of instructions committed -system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.committedInsts 54051547 # Number of instructions committed +system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426863 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_func_calls 1426247 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50023130 # number of integer instructions system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14724357 # number of memory refs -system.cpu0.num_load_insts 8664914 # Number of load instructions -system.cpu0.num_store_insts 6059443 # Number of store instructions -system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles -system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles +system.cpu0.num_mem_refs 14719518 # number of memory refs +system.cpu0.num_load_insts 8661793 # Number of load instructions +system.cpu0.num_store_insts 6057725 # Number of store instructions +system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles +system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -567,28 +567,28 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # nu system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed -system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188203 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches +system.cpu0.kern.callpal::total 188201 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3895 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -622,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915147 # number of replacements -system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use -system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits -system.cpu0.icache.overall_hits::total 53165471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses -system.cpu0.icache.overall_misses::total 915781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency +system.cpu0.icache.replacements 914734 # number of replacements +system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use +system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits +system.cpu0.icache.overall_hits::total 53144779 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses +system.cpu0.icache.overall_misses::total 915368 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,112 +677,112 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 55 # number of writebacks system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1338438 # number of replacements -system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337419 # number of replacements +system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits -system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses -system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits +system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +791,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks -system.cpu0.dcache.writebacks::total 786441 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks +system.cpu0.dcache.writebacks::total 790358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +858,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1050117 # DTB read hits +system.cpu1.dtb.read_hits 1049963 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651208 # DTB write hits +system.cpu1.dtb.write_hits 651106 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701325 # DTB hits +system.cpu1.dtb.data_hits 1701069 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493438 # ITB hits +system.cpu1.itb.fetch_hits 1493400 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494654 # ITB accesses +system.cpu1.itb.fetch_accesses 1494616 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,51 +886,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numCycles 3915155164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5282991 # Number of instructions committed -system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.committedInsts 5279868 # Number of instructions committed +system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 158031 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_func_calls 157997 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4945263 # number of integer instructions system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710778 # number of memory refs -system.cpu1.num_load_insts 1056124 # Number of load instructions -system.cpu1.num_store_insts 654654 # Number of store instructions -system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles +system.cpu1.num_mem_refs 1710522 # number of memory refs +system.cpu1.num_load_insts 1055970 # Number of load instructions +system.cpu1.num_store_insts 654552 # Number of store instructions +system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -952,7 +952,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed @@ -961,66 +961,66 @@ system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # nu system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29554 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 477 -system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.callpal::total 29550 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 476 +system.cpu1.kern.mode_good::user 463 system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86457 # number of replacements -system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use -system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits -system.cpu1.icache.overall_hits::total 5199349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses -system.cpu1.icache.overall_misses::total 87005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # 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number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 11818 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11519 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11519 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1619933 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1619933 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1619933 # number of overall hits +system.cpu1.dcache.overall_hits::total 1619933 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 36999 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 36999 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 20414 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 20414 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 944 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 944 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 507 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 57413 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57413 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57413 # number of overall misses +system.cpu1.dcache.overall_misses::total 57413 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 492506000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 492506000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 549958000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 549958000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 11305000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 11305000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6352000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6352000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1042464000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1042464000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1042464000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1042464000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040124 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1040124 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 637222 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 637222 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1145,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks -system.cpu1.dcache.writebacks::total 29784 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 505 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 505 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57534 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57534 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57534 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57534 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 421922000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 421922000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 495533000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 495533000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 10133000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 10133000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4901000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4901000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 917455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 917455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 917455000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks +system.cpu1.dcache.writebacks::total 30624 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 33fb3404f..c4cb3c061 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:23:20 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1915548867000 because m5_exit instruction encountered +Exiting @ tick 1915492819000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 42fcfede1..abedba373 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.915549 # Number of seconds simulated -sim_ticks 1915548867000 # Number of ticks simulated -final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.915493 # Number of seconds simulated +sim_ticks 1915492819000 # Number of ticks simulated +final_tick 1915492819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1238015 # Simulator instruction rate (inst/s) -host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42244373047 # Simulator tick rate (ticks/s) -host_mem_usage 292960 # Number of bytes of host memory used -host_seconds 45.34 # Real time elapsed on the host -sim_insts 56137087 # Number of instructions simulated -sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory -system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory -system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory -system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 389289 # number of replacements -system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use -system.l2c.total_refs 2311163 # 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number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 531597000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15549758000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16081355000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 531597000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15549758000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16081355000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083816500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1083816500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856489500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1856489500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250196 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141508 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383414 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383414 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173245 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173245 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.784258 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40018.369644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.643449 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.796319 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.796319 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.784258 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.993536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40013.622893 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.784258 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.993536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40013.622893 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.340325 # Cycle average of tags in use +system.iocache.tagsinuse 1.340010 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750543570000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.340010 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083751 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083751 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5720017806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5720017806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739957804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739957804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739957804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739957804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115260.104046 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137659.265643 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64633068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.632302 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570107996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570107996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9057511 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9064877 # DTB read hits +system.cpu.dtb.read_misses 10317 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6352446 # DTB write hits +system.cpu.dtb.read_accesses 728824 # DTB read accesses +system.cpu.dtb.write_hits 6356219 # DTB write hits system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15409957 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.data_hits 15421096 # DTB hits +system.cpu.dtb.data_misses 11457 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973520 # ITB hits +system.cpu.dtb.data_accesses 1020753 # DTB accesses +system.cpu.itb.fetch_hits 4974034 # ITB hits system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978517 # ITB accesses +system.cpu.itb.fetch_accesses 4979031 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3831097734 # number of cpu cycles simulated +system.cpu.numCycles 3830985638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56137087 # Number of instructions committed -system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses -system.cpu.num_func_calls 1482242 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls -system.cpu.num_int_insts 52011214 # number of integer instructions -system.cpu.num_fp_insts 324192 # number of float instructions -system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read -system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written -system.cpu.num_mem_refs 15462519 # number of memory refs -system.cpu.num_load_insts 9094324 # Number of load instructions -system.cpu.num_store_insts 6368195 # Number of store instructions -system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles -system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles -system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.936531 # Percentage of idle cycles +system.cpu.committedInsts 56182681 # Number of instructions committed +system.cpu.committedOps 56182681 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054721 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483282 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468098 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054721 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71321767 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521612 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15473677 # number of memory refs +system.cpu.num_load_insts 9101706 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3589415321.998127 # Number of idle cycles +system.cpu.num_busy_cycles 241570316.001874 # Number of busy cycles +system.cpu.not_idle_fraction 0.063057 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.936943 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211976 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74903 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106219 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73536 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73536 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149134 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857766748000 96.99% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 79985500 0.00% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554565500 0.03% 97.02% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57090762000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1915492061000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692306 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814121 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175965 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192868 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192907 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323559 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392153 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45078055000 2.35% 2.35% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5087693000 0.27% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1865326311000 97.38% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927683 # number of replacements -system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use -system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits -system.cpu.icache.overall_hits::total 55220553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses -system.cpu.icache.overall_misses::total 928354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency +system.cpu.icache.replacements 928006 # number of replacements +system.cpu.icache.tagsinuse 508.737243 # Cycle average of tags in use +system.cpu.icache.total_refs 55265829 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928517 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.520535 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 35693107000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.737243 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993627 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265829 # number of overall hits +system.cpu.icache.overall_hits::total 55265829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928677 # number of overall misses +system.cpu.icache.overall_misses::total 928677 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13560162500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13560162500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13560162500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13560162500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13560162500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13560162500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016526 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016526 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016526 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016526 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016526 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016526 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14601.591834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14601.591834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14601.591834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,104 +537,104 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 85 # number of writebacks system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928677 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928677 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928677 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928677 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928677 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928677 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10773446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10773446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10773446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10773446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10773446000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10773446000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11600.853688 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11600.853688 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11600.853688 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11600.853688 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11600.853688 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11600.853688 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390115 # number of replacements -system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1390840 # number of replacements +system.cpu.dcache.tagsinuse 511.984022 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048762 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391352 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.097202 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.984022 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848554 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30092.869598 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25879.289114 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199604500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 31269f9bd..e2b1a3bea 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index be4dcf157..50982556e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:17 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 002831edb..c0313feaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1520101 # Simulator instruction rate (inst/s) -host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22862175544 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 39.88 # Real time elapsed on the host +host_inst_rate 2171864 # Simulator instruction rate (inst/s) +host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32664627860 # Simulator tick rate (ticks/s) +host_mem_usage 382740 # Number of bytes of host memory used +host_seconds 27.91 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -30,237 +30,237 @@ system.realview.nvmem.bw_total::cpu0.inst 22 # T system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory -system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 506468 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6290740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 210652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3309616 # Number of bytes read from this memory +system.physmem.bytes_read::total 49639524 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 506468 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 210652 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4196032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.bytes_written::total 7223120 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14132 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 98365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 51739 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65563 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822335 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 555549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6900362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 231066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3630344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54449985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 555549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 231066 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 786615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4602661 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 7923097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4602661 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127935 # number of replacements -system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use -system.l2c.total_refs 1477463 # Total number of references to valid blocks. -system.l2c.sampled_refs 156884 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.417551 # Average number of references to valid blocks. +system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 555549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6919010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 231066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6932133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62373082 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70681 # number of replacements +system.l2c.tagsinuse 51554.827924 # Cycle average of tags in use +system.l2c.total_refs 1661073 # Total number of references to valid blocks. +system.l2c.sampled_refs 135855 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.226808 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits -system.l2c.Writeback_hits::total 578200 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits -system.l2c.demand_hits::total 1301917 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits -system.l2c.overall_hits::cpu0.inst 485527 # number of overall hits -system.l2c.overall_hits::cpu0.data 281787 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits -system.l2c.overall_hits::cpu1.inst 359854 # number of overall hits -system.l2c.overall_hits::cpu1.data 161413 # number of overall hits -system.l2c.overall_hits::total 1301917 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses -system.l2c.demand_misses::total 183486 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses -system.l2c.overall_misses::cpu0.data 107201 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses -system.l2c.overall_misses::cpu1.data 60967 # number of overall misses -system.l2c.overall_misses::total 183486 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # 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number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 537 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165376 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 83237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248613 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5303 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2204 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 495240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 383310 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4300 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1569 # 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number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.029284 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.038846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018284 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.883357 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800426 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.854628 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.856476 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901304 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873745 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567616 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565025 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566748 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015142 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.261543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000637 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.239065 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110679 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015142 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.261543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000637 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.239065 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110679 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,8 +269,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112464 # number of writebacks -system.l2c.writebacks::total 112464 # number of writebacks +system.l2c.writebacks::writebacks 65563 # number of writebacks +system.l2c.writebacks::total 65563 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -327,7 +327,7 @@ system.cpu0.committedInsts 33900598 # Nu system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses -system.cpu0.num_func_calls 1296918 # number of times a function call or return occured +system.cpu0.num_func_calls 1436598 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls system.cpu0.num_int_insts 39685287 # number of integer instructions system.cpu0.num_fp_insts 5074 # number of float instructions @@ -344,15 +344,15 @@ system.cpu0.not_idle_fraction 0.025030 # Pe system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed -system.cpu0.icache.replacements 497177 # number of replacements -system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use +system.cpu0.icache.replacements 497178 # number of replacements +system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks. +system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits @@ -385,42 +385,42 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks -system.cpu0.icache.writebacks::total 26062 # number of writebacks +system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks +system.cpu0.icache.writebacks::total 31457 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 385595 # number of replacements -system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 380425 # number of replacements +system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits -system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses -system.cpu0.dcache.overall_misses::total 426577 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits +system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses +system.cpu0.dcache.overall_misses::total 422544 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) @@ -433,18 +433,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14721592 system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,8 +453,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks -system.cpu0.dcache.writebacks::total 342703 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks +system.cpu0.dcache.writebacks::total 353901 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -505,7 +505,7 @@ system.cpu1.committedInsts 26714987 # Nu system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses -system.cpu1.num_func_calls 723750 # number of times a function call or return occured +system.cpu1.num_func_calls 761024 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls system.cpu1.num_int_insts 30087808 # number of integer instructions system.cpu1.num_fp_insts 5643 # number of float instructions @@ -563,42 +563,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks -system.cpu1.icache.writebacks::total 12806 # number of writebacks +system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks +system.cpu1.icache.writebacks::total 15197 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 240038 # number of replacements -system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits -system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses -system.cpu1.dcache.overall_misses::total 269979 # number of overall misses +system.cpu1.dcache.replacements 236700 # number of replacements +system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits +system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses +system.cpu1.dcache.overall_misses::total 267280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) @@ -611,18 +611,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 9644704 system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,8 +631,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks -system.cpu1.dcache.writebacks::total 196629 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks +system.cpu1.dcache.writebacks::total 212705 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 99dc32f6e..f14835c6b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index f08c091ef..4dbfc774f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:24 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:36 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 154c8ff44..176436ee7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,51 +4,51 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1412842 # Simulator instruction rate (inst/s) -host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55482154888 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 42.04 # Real time elapsed on the host +host_inst_rate 1988795 # Simulator instruction rate (inst/s) +host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78099767101 # Simulator tick rate (ticks/s) +host_mem_usage 382744 # Number of bytes of host memory used +host_seconds 29.86 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory -system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117012 # number of replacements -system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use -system.l2c.total_refs 1527554 # Total number of references to valid blocks. -system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits -system.l2c.Writeback_hits::total 605735 # number of Writeback hits +system.l2c.replacements 62240 # number of replacements +system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use +system.l2c.total_refs 1717775 # Total number of references to valid blocks. +system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits +system.l2c.Writeback_hits::total 642748 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits -system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits -system.l2c.overall_hits::cpu.inst 835264 # number of overall hits -system.l2c.overall_hits::cpu.data 463541 # number of overall hits -system.l2c.overall_hits::total 1309459 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits +system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits +system.l2c.overall_hits::cpu.inst 838895 # number of overall hits +system.l2c.overall_hits::cpu.data 478181 # number of overall hits +system.l2c.overall_hits::total 1327761 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses -system.l2c.demand_misses::total 172858 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu.inst 14304 # number of overall misses -system.l2c.overall_misses::cpu.data 158515 # number of overall misses -system.l2c.overall_misses::total 172858 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses +system.l2c.demand_misses::total 153949 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu.inst 10602 # number of overall misses +system.l2c.overall_misses::cpu.data 143339 # number of overall misses +system.l2c.overall_misses::total 153949 # number of overall misses system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102725 # number of writebacks -system.l2c.writebacks::total 102725 # number of writebacks +system.l2c.writebacks::writebacks 57860 # number of writebacks +system.l2c.writebacks::total 57860 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -224,7 +224,7 @@ system.cpu.committedInsts 59392246 # Nu system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1972385 # number of times a function call or return occured +system.cpu.num_func_calls 2136013 # number of times a function call or return occured system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls system.cpu.num_int_insts 68281415 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions @@ -282,8 +282,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 44595 # number of writebacks -system.cpu.icache.writebacks::total 44595 # number of writebacks +system.cpu.icache.writebacks::writebacks 50093 # number of writebacks +system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 623347 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use @@ -346,8 +346,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks -system.cpu.dcache.writebacks::total 561140 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks +system.cpu.dcache.writebacks::total 592655 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 08257cec9..f78b6a8fb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index dc9f6d387..ccc6b6e90 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:26:08 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:10 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169707043000 because m5_exit instruction encountered +Exiting @ tick 1169301297000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index c1f17df29..a92b3a054 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169707 # Number of seconds simulated -sim_ticks 1169707043000 # Number of ticks simulated -final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169301 # Number of seconds simulated +sim_ticks 1169301297000 # Number of ticks simulated +final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657704 # Simulator instruction rate (inst/s) -host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12730829062 # Simulator tick rate (ticks/s) -host_mem_usage 382856 # Number of bytes of host memory used -host_seconds 91.88 # Real time elapsed on the host -sim_insts 60429704 # Number of instructions simulated -sim_ops 77281862 # Number of ops (including micro ops) simulated +host_inst_rate 971844 # Simulator instruction rate (inst/s) +host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18805861990 # Simulator tick rate (ticks/s) +host_mem_usage 384788 # Number of bytes of host memory used +host_seconds 62.18 # Real time elapsed on the host +sim_insts 60426768 # Number of instructions simulated +sim_ops 77275723 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -30,309 +30,291 @@ system.realview.nvmem.bw_total::cpu0.inst 17 # T system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory -system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory +system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 125934 # number of replacements -system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use -system.l2c.total_refs 1500548 # Total number of references to valid blocks. -system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. +system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69045 # number of replacements +system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use +system.l2c.total_refs 1684870 # Total number of references to valid blocks. +system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits -system.l2c.Writeback_hits::total 577354 # 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average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,26 +498,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070142 # DTB read hits -system.cpu0.dtb.read_misses 3739 # DTB read misses -system.cpu0.dtb.write_hits 5655287 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 7070010 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 5655317 # DTB write hits +system.cpu0.dtb.write_misses 808 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073881 # DTB read accesses -system.cpu0.dtb.write_accesses 5656089 # DTB write accesses +system.cpu0.dtb.read_accesses 7073752 # DTB read accesses +system.cpu0.dtb.write_accesses 5656125 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725429 # DTB hits -system.cpu0.dtb.misses 4541 # DTB misses -system.cpu0.dtb.accesses 12729970 # DTB accesses -system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.dtb.hits 12725327 # DTB hits +system.cpu0.dtb.misses 4550 # DTB misses +system.cpu0.dtb.accesses 12729877 # DTB accesses +system.cpu0.itb.inst_hits 29439174 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -564,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses -system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses +system.cpu0.itb.hits 29439174 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441837 # DTB accesses -system.cpu0.numCycles 2339414086 # number of cpu cycles simulated +system.cpu0.itb.accesses 29441379 # DTB accesses +system.cpu0.numCycles 2338602594 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28747266 # Number of instructions committed -system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.committedInsts 28746820 # Number of instructions committed +system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1116936 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_func_calls 1241704 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031249 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393398 # number of memory refs -system.cpu0.num_load_insts 7407664 # Number of load instructions -system.cpu0.num_store_insts 5985734 # Number of store instructions -system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles -system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles -system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles +system.cpu0.num_mem_refs 13393278 # number of memory refs +system.cpu0.num_load_insts 7407523 # Number of load instructions +system.cpu0.num_store_insts 5985755 # Number of store instructions +system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles +system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed -system.cpu0.icache.replacements 408172 # number of replacements -system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits -system.cpu0.icache.overall_hits::total 29030930 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses -system.cpu0.icache.overall_misses::total 408685 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency +system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed +system.cpu0.icache.replacements 408143 # number of replacements +system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits +system.cpu0.icache.overall_hits::total 29030502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses +system.cpu0.icache.overall_misses::total 408655 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,122 +615,122 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks +system.cpu0.icache.writebacks::total 20759 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 335831 # number of replacements -system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330129 # number of replacements +system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # 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number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses +system.cpu0.dcache.overall_misses::total 368966 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks -system.cpu0.dcache.writebacks::total 287163 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks +system.cpu0.dcache.writebacks::total 306018 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -834,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8313009 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5829499 # DTB write hits -system.cpu1.dtb.write_misses 1439 # DTB write misses +system.cpu1.dtb.read_hits 8311514 # DTB read hits +system.cpu1.dtb.read_misses 3660 # DTB read misses +system.cpu1.dtb.write_hits 5828200 # DTB write hits +system.cpu1.dtb.write_misses 1442 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316672 # DTB read accesses -system.cpu1.dtb.write_accesses 5830938 # DTB write accesses +system.cpu1.dtb.read_accesses 8315174 # DTB read accesses +system.cpu1.dtb.write_accesses 5829642 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.hits 14139714 # DTB hits system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14147610 # DTB accesses -system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.dtb.accesses 14144816 # DTB accesses +system.cpu1.itb.inst_hits 32283727 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -870,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses -system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses +system.cpu1.itb.hits 32283727 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32288411 # DTB accesses -system.cpu1.numCycles 2338003468 # number of cpu cycles simulated +system.cpu1.itb.accesses 32285898 # DTB accesses +system.cpu1.numCycles 2337184534 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31682438 # Number of instructions committed -system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.committedInsts 31679948 # Number of instructions committed +system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 909270 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_func_calls 962114 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36862651 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14680299 # number of memory refs -system.cpu1.num_load_insts 8634860 # Number of load instructions -system.cpu1.num_store_insts 6045439 # Number of store instructions -system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles -system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles +system.cpu1.num_mem_refs 14677413 # number of memory refs +system.cpu1.num_load_insts 8633313 # Number of load instructions +system.cpu1.num_store_insts 6044100 # Number of store instructions +system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles +system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed -system.cpu1.icache.replacements 454317 # number of replacements -system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use -system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits -system.cpu1.icache.overall_hits::total 31831407 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses -system.cpu1.icache.overall_misses::total 454829 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency +system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed +system.cpu1.icache.replacements 454250 # number of replacements +system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use +system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits +system.cpu1.icache.overall_hits::total 31828961 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454762 # 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average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -951,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks +system.cpu1.icache.writebacks::total 23283 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294642 # number of replacements -system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11964721 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks -system.cpu1.dcache.writebacks::total 254584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks +system.cpu1.dcache.writebacks::total 265856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 6a942652a..d41ee2fc6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index b6cf436ae..4f563f8f5 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:42 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:57 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2591419000000 because m5_exit instruction encountered +Exiting @ tick 2591087067000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 20ffbfc50..f1beadd55 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.591419 # Number of seconds simulated -sim_ticks 2591419000000 # Number of ticks simulated -final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.591087 # Number of seconds simulated +sim_ticks 2591087067000 # Number of ticks simulated +final_tick 2591087067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 555808 # Simulator instruction rate (inst/s) -host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24337050134 # Simulator tick rate (ticks/s) -host_mem_usage 383104 # Number of bytes of host memory used -host_seconds 106.48 # Real time elapsed on the host -sim_insts 59182652 # Number of instructions simulated -sim_ops 75585847 # Number of ops (including micro ops) simulated +host_inst_rate 814871 # Simulator instruction rate (inst/s) +host_op_rate 1040723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35675794467 # Simulator tick rate (ticks/s) +host_mem_usage 385812 # Number of bytes of host memory used +host_seconds 72.63 # Real time elapsed on the host +sim_insts 59182970 # Number of instructions simulated +sim_ops 75586355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory -system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 706144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9051344 # Number of bytes read from this memory +system.physmem.bytes_read::total 132441392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3678592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6694664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17236 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141461 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494129 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57478 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 811496 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47348232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 272528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3493261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51114219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1419710 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1164018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2583728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1419710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47348232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 272528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4657279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53697947 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,141 +61,141 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117210 # number of replacements -system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use -system.l2c.total_refs 1536782 # Total number of references to valid blocks. -system.l2c.sampled_refs 146347 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.500946 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits -system.l2c.Writeback_hits::total 611793 # number of Writeback hits +system.l2c.replacements 61946 # number of replacements +system.l2c.tagsinuse 50741.194054 # Cycle average of tags in use +system.l2c.total_refs 1730603 # Total number of references to valid blocks. +system.l2c.sampled_refs 127327 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.591799 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2543210574000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37737.574743 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 3.884961 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.001325 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6978.831431 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6020.901593 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575830 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.106489 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.091872 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.774249 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8734 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,9 +307,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995950 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230967 # DTB write hits +system.cpu.dtb.read_hits 14996145 # DTB read hits +system.cpu.dtb.read_misses 7343 # DTB read misses +system.cpu.dtb.write_hits 11231074 # DTB write hits system.cpu.dtb.write_misses 2209 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -320,13 +320,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003292 # DTB read accesses -system.cpu.dtb.write_accesses 11233176 # DTB write accesses +system.cpu.dtb.read_accesses 15003488 # DTB read accesses +system.cpu.dtb.write_accesses 11233283 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226917 # DTB hits -system.cpu.dtb.misses 9551 # DTB misses -system.cpu.dtb.accesses 26236468 # DTB accesses -system.cpu.itb.inst_hits 60464458 # ITB inst hits +system.cpu.dtb.hits 26227219 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 26236771 # DTB accesses +system.cpu.itb.inst_hits 60464772 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60468929 # ITB inst accesses -system.cpu.itb.hits 60464458 # DTB hits +system.cpu.itb.inst_accesses 60469243 # ITB inst accesses +system.cpu.itb.hits 60464772 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60468929 # DTB accesses -system.cpu.numCycles 5182838000 # number of cpu cycles simulated +system.cpu.itb.accesses 60469243 # DTB accesses +system.cpu.numCycles 5182174134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59182652 # Number of instructions committed -system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses +system.cpu.committedInsts 59182970 # Number of instructions committed +system.cpu.committedOps 75586355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68355817 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1976025 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls -system.cpu.num_int_insts 68355333 # number of integer instructions +system.cpu.num_func_calls 2139775 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7653714 # number of instructions that are conditional controls +system.cpu.num_int_insts 68355817 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read -system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written +system.cpu.num_int_register_reads 391424329 # number of times the integer registers were read +system.cpu.num_int_register_writes 73137723 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394170 # number of memory refs -system.cpu.num_load_insts 15659823 # Number of load instructions -system.cpu.num_store_insts 11734347 # Number of store instructions -system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles -system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles -system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.882526 # Percentage of idle cycles +system.cpu.num_mem_refs 27394520 # number of memory refs +system.cpu.num_load_insts 15660068 # Number of load instructions +system.cpu.num_store_insts 11734452 # Number of store instructions +system.cpu.num_idle_cycles 4574883884.570234 # Number of idle cycles +system.cpu.num_busy_cycles 607290249.429766 # Number of busy cycles +system.cpu.not_idle_fraction 0.117188 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.882812 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed -system.cpu.icache.replacements 855402 # number of replacements -system.cpu.icache.tagsinuse 510.943261 # Cycle average of tags in use -system.cpu.icache.total_refs 59608544 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855914 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.643146 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18524424000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.943261 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59608544 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59608544 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59608544 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59608544 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59608544 # number of overall hits -system.cpu.icache.overall_hits::total 59608544 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855914 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855914 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855914 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855914 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855914 # number of overall misses -system.cpu.icache.overall_misses::total 855914 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12584924000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12584924000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12584924000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12584924000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12584924000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency +system.cpu.icache.replacements 855597 # number of replacements +system.cpu.icache.tagsinuse 510.944278 # Cycle average of tags in use +system.cpu.icache.total_refs 59608663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856109 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.627422 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18496284000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.944278 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997938 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59608663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59608663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59608663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59608663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59608663 # number of overall hits +system.cpu.icache.overall_hits::total 59608663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856109 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856109 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856109 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856109 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856109 # number of overall misses +system.cpu.icache.overall_misses::total 856109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422495000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12422495000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12422495000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12422495000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12422495000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12422495000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60464772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60464772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60464772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60464772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60464772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60464772 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14510.412810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14510.412810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14510.412810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14510.412810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,114 +424,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 45705 # number of writebacks -system.cpu.icache.writebacks::total 45705 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10014791000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10014791000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10014791000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 50189 # number of writebacks +system.cpu.icache.writebacks::total 50189 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856109 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856109 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856109 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856109 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856109 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856109 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851777000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9851777000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851777000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9851777000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851777000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9851777000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014159 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014159 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014159 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11507.619941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11507.619941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11507.619941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11507.619941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11507.619941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11507.619941 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627094 # number of replacements -system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627131 # number of replacements +system.cpu.dcache.tagsinuse 511.875575 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655898 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627643 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.690053 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.875575 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195546 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973168 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973168 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236327 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247699 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247699 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168714 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168714 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168714 # number of overall hits -system.cpu.dcache.overall_hits::total 23168714 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368647 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368647 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250483 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250483 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11373 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11373 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619130 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619130 # number of overall misses -system.cpu.dcache.overall_misses::total 619130 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5836151500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5836151500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9546175500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9546175500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185299500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185299500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15382327000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15382327000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15382327000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15382327000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223651 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223651 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247700 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973243 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236320 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236320 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247701 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247701 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168984 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168984 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168984 # number of overall hits +system.cpu.dcache.overall_hits::total 23168984 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368641 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368641 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250513 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250513 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619154 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619154 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619154 # number of overall misses +system.cpu.dcache.overall_misses::total 619154 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5550266500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5550266500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238505500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9238505500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 165952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14788772000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14788772000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14788772000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14788772000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23788138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23788138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23788138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23788138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026028 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026028 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026028 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026028 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.020627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15056.020627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36878.347631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36878.347631 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23885.450146 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,54 +540,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks -system.cpu.dcache.writebacks::total 566088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595911 # number of writebacks +system.cpu.dcache.writebacks::total 595911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250513 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +609,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341944663355 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 0d2987eae..18f4bf90b 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:04:41 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:02:50 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 82168f91d..1886c90bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,145 +4,145 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304311 # Simulator instruction rate (inst/s) -host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33369516688 # Simulator tick rate (ticks/s) -host_mem_usage 357276 # Number of bytes of host memory used -host_seconds 153.20 # Real time elapsed on the host -sim_insts 199813913 # Number of instructions simulated -sim_ops 409133277 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory -system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory -system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory -system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 164044 # number of replacements -system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use -system.l2c.total_refs 3332458 # Total number of references to valid blocks. -system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. -system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. +host_inst_rate 1996585 # Simulator instruction rate (inst/s) +host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51080652430 # Simulator tick rate (ticks/s) +host_mem_usage 357308 # Number of bytes of host memory used +host_seconds 100.08 # Real time elapsed on the host +sim_insts 199813912 # Number of instructions simulated +sim_ops 409133288 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 106561 # number of replacements +system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use +system.l2c.total_refs 3457342 # Total number of references to valid blocks. +system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. +system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits -system.l2c.Writeback_hits::total 1529403 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits -system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits -system.l2c.overall_hits::cpu.inst 776101 # number of overall hits -system.l2c.overall_hits::cpu.data 1435764 # number of overall hits -system.l2c.overall_hits::total 2221403 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses -system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses -system.l2c.demand_misses::total 200638 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu.inst 15200 # number of overall misses -system.l2c.overall_misses::cpu.data 185411 # number of overall misses -system.l2c.overall_misses::total 200638 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses +system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits +system.l2c.Writeback_hits::total 1538939 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits +system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.l2c.overall_hits::cpu.inst 777957 # number of overall hits +system.l2c.overall_hits::cpu.data 1454603 # number of overall hits +system.l2c.overall_hits::total 2241838 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses +system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses +system.l2c.demand_misses::total 179910 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.inst 13342 # number of overall misses +system.l2c.overall_misses::cpu.data 166561 # number of overall misses +system.l2c.overall_misses::total 179910 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,8 +151,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 144472 # number of writebacks -system.l2c.writebacks::total 144472 # number of writebacks +system.l2c.writebacks::writebacks 98533 # number of writebacks +system.l2c.writebacks::total 98533 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use @@ -213,32 +213,32 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813913 # Number of instructions committed -system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses +system.cpu.committedInsts 199813912 # Number of instructions committed +system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297244 # number of integer instructions +system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297254 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read -system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written +system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read +system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626519 # number of memory refs -system.cpu.num_load_insts 27217784 # Number of load instructions +system.cpu.num_mem_refs 35626517 # number of memory refs +system.cpu.num_load_insts 27217782 # Number of load instructions system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles +system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790795 # number of replacements +system.cpu.icache.replacements 790793 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. +system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy @@ -249,18 +249,18 @@ system.cpu.icache.demand_hits::cpu.inst 243365777 # nu system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits system.cpu.icache.overall_hits::total 243365777 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses -system.cpu.icache.overall_misses::total 791314 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses +system.cpu.icache.overall_misses::total 791312 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -278,29 +278,29 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 809 # number of writebacks system.cpu.icache.writebacks::total 809 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3435 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3335 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) @@ -309,12 +309,12 @@ system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,42 +323,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7755 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7598 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,42 +367,42 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621277 # number of replacements -system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use +system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits -system.cpu.dcache.overall_hits::total 20139962 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits +system.cpu.dcache.overall_hits::total 20139960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -419,8 +419,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks -system.cpu.dcache.writebacks::total 1525559 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks +system.cpu.dcache.writebacks::total 1534981 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index d30404a01..d9a666d01 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:05:12 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:04:41 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5195470393000 because m5_exit instruction encountered +Exiting @ tick 5187414160000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 9cc951eb3..78491477d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,186 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.195470 # Number of seconds simulated -sim_ticks 5195470393000 # Number of ticks simulated -final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187414 # Number of seconds simulated +sim_ticks 5187414160000 # Number of ticks simulated +final_tick 5187414160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 792632 # Simulator instruction rate (inst/s) -host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29811367673 # Simulator tick rate (ticks/s) -host_mem_usage 354100 # Number of bytes of host memory used -host_seconds 174.28 # Real time elapsed on the host -sim_insts 138138472 # Number of instructions simulated -sim_ops 265147881 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory -system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory -system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory -system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 136133 # number of replacements -system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use -system.l2c.total_refs 3363370 # Total number of references to valid blocks. -system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. -system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. +host_inst_rate 1218225 # Simulator instruction rate (inst/s) +host_op_rate 2338274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45751964384 # Simulator tick rate (ticks/s) +host_mem_usage 354108 # Number of bytes of host memory used +host_seconds 113.38 # Real time elapsed on the host +sim_insts 138123832 # Number of instructions simulated +sim_ops 265116381 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2873600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 823872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9013056 # Number of bytes read from this memory +system.physmem.bytes_read::total 12710848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8119168 # Number of bytes written to this memory +system.physmem.bytes_written::total 8119168 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126862 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126862 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 553956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1737485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2450324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1565167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1565167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 553956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1737485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4015491 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 87121 # number of replacements +system.l2c.tagsinuse 64744.373482 # Cycle average of tags in use +system.l2c.total_refs 3489902 # Total number of references to valid blocks. +system.l2c.sampled_refs 151833 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.985135 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits -system.l2c.Writeback_hits::total 1534567 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits -system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits -system.l2c.overall_hits::cpu.inst 773419 # number of overall hits -system.l2c.overall_hits::cpu.data 1467421 # number of overall hits -system.l2c.overall_hits::total 2250401 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses -system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses -system.l2c.demand_misses::total 170998 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 10 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051788000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 56051788000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218002000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1218002000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269790000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 57269790000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001666 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016337 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021624 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019547 # 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average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40011.418363 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40452.804861 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40314.783791 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40260.744986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40260.744986 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.131732 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.131732 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40011.418363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40094.552639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40087.626699 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40011.418363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40094.552639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40087.626699 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -280,39 +250,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47510 # number of replacements -system.iocache.tagsinuse 0.120586 # Cycle average of tags in use +system.iocache.replacements 47504 # number of replacements +system.iocache.tagsinuse 0.096008 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.warmup_cycle 5048726357000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.096008 # 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miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -321,40 +291,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126330.073897 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126330.073897 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136812.289384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136812.289384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136627.370046 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136627.370046 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 69487644 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11303 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6147.716889 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # 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mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -363,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74305.098927 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74305.098927 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84806.806421 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84806.806421 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -384,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10390940786 # number of cpu cycles simulated +system.cpu.numCycles 10374828320 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 138138472 # Number of instructions committed -system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses +system.cpu.committedInsts 138123832 # Number of instructions committed +system.cpu.committedOps 265116381 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 249524959 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls -system.cpu.num_int_insts 249556386 # number of integer instructions +system.cpu.num_conditional_control_insts 24879442 # number of instructions that are conditional controls +system.cpu.num_int_insts 249524959 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 778086007 # number of times the integer registers were read -system.cpu.num_int_register_writes 422921187 # number of times the integer registers were written +system.cpu.num_int_register_reads 777989618 # number of times the integer registers were read +system.cpu.num_int_register_writes 422868687 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 23169904 # number of memory refs -system.cpu.num_load_insts 14812525 # Number of load instructions -system.cpu.num_store_insts 8357379 # Number of store instructions -system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles -system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles -system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941953 # Percentage of idle cycles +system.cpu.num_mem_refs 23163323 # number of memory refs +system.cpu.num_load_insts 14806608 # Number of load instructions +system.cpu.num_store_insts 8356715 # Number of store instructions +system.cpu.num_idle_cycles 9773126970.350117 # Number of idle cycles +system.cpu.num_busy_cycles 601701349.649884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057996 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942004 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 788139 # number of replacements -system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use -system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits -system.cpu.icache.overall_hits::total 158433932 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses -system.cpu.icache.overall_misses::total 788658 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency +system.cpu.icache.replacements 787531 # number of replacements +system.cpu.icache.tagsinuse 510.360069 # Cycle average of tags in use +system.cpu.icache.total_refs 158416168 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 788043 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 201.024777 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159962400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.360069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996797 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996797 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 158416168 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 158416168 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 158416168 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 158416168 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 158416168 # number of overall hits +system.cpu.icache.overall_hits::total 158416168 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 788050 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788050 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 788050 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 788050 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 788050 # number of overall misses +system.cpu.icache.overall_misses::total 788050 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11574503000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11574503000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11574503000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11574503000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11574503000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11574503000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 159204218 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159204218 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 159204218 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159204218 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 159204218 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 159204218 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004950 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004950 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.004950 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004950 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.004950 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004950 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14687.523634 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14687.523634 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14687.523634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14687.523634 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,82 +431,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 805 # number of writebacks -system.cpu.icache.writebacks::total 805 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1027 # number of writebacks +system.cpu.icache.writebacks::total 1027 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788050 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788050 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788050 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788050 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788050 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788050 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9209308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9209308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9209308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9209308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9209308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9209308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004950 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11686.197576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11686.197576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11686.197576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11686.197576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11686.197576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11686.197576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3754 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3928 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.062395 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7428 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3940 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.885279 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5163621004000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.062395 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191400 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191400 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7428 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7428 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7430 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7430 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7430 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7430 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4796 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4796 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4796 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4796 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4796 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4796 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51199000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51199000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51199000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 51199000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51199000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 51199000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.392343 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.392343 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.392279 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.392279 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.392279 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.392279 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10675.354462 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10675.354462 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10675.354462 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,78 +515,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 763 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 763 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4796 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4796 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4796 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4796 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4796 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4796 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36811000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36811000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36811000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36811000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36811000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36811000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.392343 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.392343 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.392279 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.392279 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7675.354462 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7704 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 8715 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.044713 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12138 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 8729 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.390537 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162053528000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.044713 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315295 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315295 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12140 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12140 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12140 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12140 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12140 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12140 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9925 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9925 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9925 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9925 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9925 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9925 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112013000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112013000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112013000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 112013000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112013000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 112013000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22065 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22065 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22065 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22065 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22065 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22065 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.449807 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.449807 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.449807 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.449807 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.449807 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.449807 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11285.944584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11285.944584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11285.944584 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,90 +595,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2933 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2933 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9925 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9925 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9925 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9925 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9925 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9925 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 82238000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 82238000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 82238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 82238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 82238000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 82238000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.449807 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.449807 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.449807 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8285.944584 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1623424 # number of replacements -system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use -system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621962 # number of replacements +system.cpu.dcache.tagsinuse 511.997374 # Cycle average of tags in use +system.cpu.dcache.total_refs 20006252 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622474 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.330707 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997374 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits -system.cpu.dcache.overall_hits::total 20009191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses -system.cpu.dcache.overall_misses::total 1626168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11972224 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11972224 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8031812 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8031812 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20004036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20004036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20004036 # number of overall hits +system.cpu.dcache.overall_hits::total 20004036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1309841 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1309841 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314876 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314876 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624717 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624717 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624717 # number of overall misses +system.cpu.dcache.overall_misses::total 1624717 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19532720500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19532720500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9225744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9225744000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28758464500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28758464500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28758464500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28758464500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13282065 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13282065 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8346688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8346688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21628753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21628753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21628753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21628753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098617 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098617 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037725 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037725 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075118 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075118 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075118 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075118 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14912.283628 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14912.283628 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29299.610005 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29299.610005 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17700.599243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17700.599243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17700.599243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17700.599243 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -717,46 +687,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks -system.cpu.dcache.writebacks::total 1529951 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538945 # number of writebacks +system.cpu.dcache.writebacks::total 1538945 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309841 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1309841 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314876 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314876 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624717 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624717 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624717 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624717 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15603157000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15603157000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8281105000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8281105000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23884262000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23884262000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23884262000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23884262000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379632500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379632500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77304960000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 77304960000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037725 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037725 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11912.252709 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11912.252709 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26299.575071 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26299.575071 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14700.567545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14700.567545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14700.567545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14700.567545 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index bcee17b83..da5dd186c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:03:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:21 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12450500 because target called exit() +Exiting @ tick 12146500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index e9f17ec08..40a9fef11 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12450500 # Number of ticks simulated -final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12146500 # Number of ticks simulated +final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73568 # Simulator instruction rate (inst/s) -host_op_rate 73552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 143373020 # Simulator tick rate (ticks/s) -host_mem_usage 215332 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 109785 # Simulator instruction rate (inst/s) +host_op_rate 109750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 208686624 # Simulator tick rate (ticks/s) +host_mem_usage 218220 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory -system.physmem.bytes_read::total 31360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 490 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 488 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1943 # DTB read hits -system.cpu.dtb.read_misses 53 # DTB read misses +system.cpu.dtb.read_hits 1978 # DTB read hits +system.cpu.dtb.read_misses 49 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1996 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2027 # DTB read accesses +system.cpu.dtb.write_hits 1059 # DTB write hits +system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1103 # DTB write accesses -system.cpu.dtb.data_hits 3014 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1090 # DTB write accesses +system.cpu.dtb.data_hits 3037 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3099 # DTB accesses -system.cpu.itb.fetch_hits 2367 # ITB hits -system.cpu.itb.fetch_misses 26 # ITB misses +system.cpu.dtb.data_accesses 3117 # DTB accesses +system.cpu.itb.fetch_hits 2279 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2393 # ITB accesses +system.cpu.itb.fetch_accesses 2309 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24902 # number of cpu cycles simulated +system.cpu.numCycles 24294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits +system.cpu.BPredUnit.lookups 2808 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2684 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2587 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups +system.cpu.rename.RunCycles 2519 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10522 # Type of FU issued -system.cpu.iq.rate 0.422536 # Inst issue rate -system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10419 # Type of FU issued +system.cpu.iq.rate 0.428871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79 # number of nop insts executed -system.cpu.iew.exec_refs 3117 # number of memory reference insts executed -system.cpu.iew.exec_branches 1605 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.396675 # Inst execution rate -system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4957 # num instructions producing a value -system.cpu.iew.wb_consumers 6732 # num instructions consuming a value +system.cpu.iew.exec_nop 83 # number of nop insts executed +system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_stores 1093 # Number of stores executed +system.cpu.iew.exec_rate 0.405244 # Inst execution rate +system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4951 # num instructions producing a value +system.cpu.iew.wb_consumers 6720 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back +system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,70 +310,70 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24667 # The number of ROB reads -system.cpu.rob.rob_writes 26868 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24228 # The number of ROB reads +system.cpu.rob.rob_writes 26471 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads -system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12526 # number of integer regfile reads -system.cpu.int_regfile_writes 7116 # number of integer regfile writes +system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12506 # number of integer regfile reads +system.cpu.int_regfile_writes 7104 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use -system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use +system.cpu.icache.total_refs 1829 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits -system.cpu.icache.overall_hits::total 1909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses -system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits +system.cpu.icache.overall_hits::total 1829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses +system.cpu.icache.overall_misses::total 450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use -system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use +system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # 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number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,14 +478,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -494,103 +494,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 176 system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 157d28a7a..2586fc610 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:45:03 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:32 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7015000 because target called exit() +Exiting @ tick 6934000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 119328db2..729742f8d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7015000 # Number of ticks simulated -final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 6934000 # Number of ticks simulated +final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16156 # Simulator instruction rate (inst/s) -host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47467285 # Simulator tick rate (ticks/s) -host_mem_usage 214556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 29510 # Simulator instruction rate (inst/s) +host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85688409 # Simulator tick rate (ticks/s) +host_mem_usage 217944 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory -system.physmem.bytes_read::total 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory -system.physmem.num_reads::total 275 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory +system.physmem.bytes_read::total 17472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory +system.physmem.num_reads::total 273 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 711 # DTB read hits -system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.read_hits 704 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 380 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.read_accesses 740 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 403 # DTB write accesses -system.cpu.dtb.data_hits 1091 # DTB hits -system.cpu.dtb.data_misses 66 # DTB misses +system.cpu.dtb.write_accesses 389 # DTB write accesses +system.cpu.dtb.data_hits 1071 # DTB hits +system.cpu.dtb.data_misses 58 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1157 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 1129 # DTB accesses +system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1100 # ITB accesses +system.cpu.itb.fetch_accesses 1029 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14031 # number of cpu cycles simulated +system.cpu.numCycles 13869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1201 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits +system.cpu.BPredUnit.lookups 1119 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1197 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1133 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups +system.cpu.rename.RunCycles 1046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle +system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4206 # Type of FU issued -system.cpu.iq.rate 0.299765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4026 # Type of FU issued +system.cpu.iq.rate 0.290288 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 368 # number of nop insts executed -system.cpu.iew.exec_refs 1160 # number of memory reference insts executed -system.cpu.iew.exec_branches 681 # Number of branches executed -system.cpu.iew.exec_stores 403 # Number of stores executed -system.cpu.iew.exec_rate 0.285439 # Inst execution rate -system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3813 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1793 # num instructions producing a value -system.cpu.iew.wb_consumers 2339 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_branches 650 # Number of branches executed +system.cpu.iew.exec_stores 389 # Number of stores executed +system.cpu.iew.exec_rate 0.279256 # Inst execution rate +system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1732 # num instructions producing a value +system.cpu.iew.wb_consumers 2249 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back +system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11567 # The number of ROB reads -system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.rob.rob_reads 11123 # The number of ROB reads +system.cpu.rob.rob_writes 11131 # The number of ROB writes system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4832 # number of integer regfile reads -system.cpu.int_regfile_writes 2958 # number of integer regfile writes +system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4695 # number of integer regfile reads +system.cpu.int_regfile_writes 2856 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use -system.cpu.icache.total_refs 817 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use +system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits -system.cpu.icache.overall_hits::total 817 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits +system.cpu.icache.overall_hits::total 752 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses +system.cpu.icache.overall_misses::total 247 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use -system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use +system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 793 # 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number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses -system.cpu.dcache.overall_misses::total 179 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses +system.cpu.dcache.overall_misses::total 182 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,91 +477,91 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 62 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,28 +592,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 9fb63a7a7..c374c028c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:53 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ea50665b2..9b64fc302 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43907 # Simulator instruction rate (inst/s) -host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98312554 # Simulator tick rate (ticks/s) -host_mem_usage 230064 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 40668 # Simulator instruction rate (inst/s) +host_op_rate 50741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91257316 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5752 # number of cpu cycles simulated +system.cpu.checker.numCycles 5742 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -115,319 +115,318 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -566,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -645,27 +644,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,49 +680,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index fc15b65e3..8b9162b5e 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:30 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:42 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 85d0d7401..e182dd250 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49511 # Simulator instruction rate (inst/s) -host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110854808 # Simulator tick rate (ticks/s) -host_mem_usage 229756 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 29768 # Simulator instruction rate (inst/s) +host_op_rate 37142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66801597 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,319 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -521,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # 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number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -600,27 +599,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,49 +635,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a8cf8ab9b..a902d2024 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:03 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:15 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index a4d8f3fa5..2fe5ceaba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 760705 # Simulator instruction rate (inst/s) -host_op_rate 946184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472746039 # Simulator tick rate (ticks/s) -host_mem_usage 219832 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 136961 # Simulator instruction rate (inst/s) +host_op_rate 170823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85547635 # Simulator tick rate (ticks/s) +host_mem_usage 223208 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -121,26 +121,26 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index f818842dc..d40bbcb86 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:52 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:04 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 44b5714ac..ef6865dff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 577592 # Simulator instruction rate (inst/s) -host_op_rate 718947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359450620 # Simulator tick rate (ticks/s) -host_mem_usage 219740 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 62314 # Simulator instruction rate (inst/s) +host_op_rate 77743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38944247 # Simulator tick rate (ticks/s) +host_mem_usage 223212 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index a6d6adcc2..d4a066c4f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:13 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26361000 because target called exit() +Exiting @ tick 26351000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 0449db647..bac15b503 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26361000 # Number of ticks simulated -final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26351000 # Number of ticks simulated +final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366471 # Simulator instruction rate (inst/s) -host_op_rate 454532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2105652624 # Simulator tick rate (ticks/s) -host_mem_usage 228652 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4574 # Number of instructions simulated -sim_ops 5682 # Number of ops (including micro ops) simulated +host_inst_rate 50718 # Simulator instruction rate (inst/s) +host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292657577 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 4565 # Number of instructions simulated +sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52722 # number of cpu cycles simulated +system.cpu.numCycles 52702 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4574 # Number of instructions committed -system.cpu.committedOps 5682 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4565 # Number of instructions committed +system.cpu.committedOps 5672 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28701 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 28656 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52722 # Number of busy cycles +system.cpu.num_busy_cycles 52702 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use -system.cpu.icache.total_refs 4373 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits -system.cpu.icache.overall_hits::total 4373 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits +system.cpu.icache.overall_hits::total 4364 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses @@ -119,18 +119,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12824000 system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency @@ -157,12 +157,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use -system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits -system.cpu.dcache.overall_hits::total 1919 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits +system.cpu.dcache.overall_hits::total 1918 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -207,26 +207,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7224000 system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -259,14 +259,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index c92fa97a1..d99f33506 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:52:53 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12671500 because target called exit() +Exiting @ tick 12478500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 69e82fc15..7981b4fdb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12671500 # Number of ticks simulated -final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12478500 # Number of ticks simulated +final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63611 # Simulator instruction rate (inst/s) -host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155871053 # Simulator tick rate (ticks/s) -host_mem_usage 216124 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84509 # Simulator instruction rate (inst/s) +host_op_rate 84485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203899861 # Simulator tick rate (ticks/s) +host_mem_usage 220092 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25344 # number of cpu cycles simulated +system.cpu.numCycles 24958 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2242 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits +system.cpu.BPredUnit.lookups 2172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2966 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3014 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2873 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -171,120 +171,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8177 # Type of FU issued -system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.FU_type_0::total 8121 # Type of FU issued +system.cpu.iq.rate 0.325387 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1464 # number of nop insts executed -system.cpu.iew.exec_refs 3166 # number of memory reference insts executed -system.cpu.iew.exec_branches 1317 # Number of branches executed -system.cpu.iew.exec_stores 1061 # Number of stores executed -system.cpu.iew.exec_rate 0.306305 # Inst execution rate -system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7307 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2841 # num instructions producing a value -system.cpu.iew.wb_consumers 4060 # num instructions consuming a value +system.cpu.iew.exec_nop 1469 # number of nop insts executed +system.cpu.iew.exec_refs 3191 # number of memory reference insts executed +system.cpu.iew.exec_branches 1304 # Number of branches executed +system.cpu.iew.exec_stores 1065 # Number of stores executed +system.cpu.iew.exec_rate 0.311163 # Inst execution rate +system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2836 # num instructions producing a value +system.cpu.iew.wb_consumers 4075 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back +system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,69 +295,69 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22904 # The number of ROB reads -system.cpu.rob.rob_writes 22029 # The number of ROB writes -system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22599 # The number of ROB reads +system.cpu.rob.rob_writes 21853 # The number of ROB writes +system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10565 # number of integer regfile reads -system.cpu.int_regfile_writes 5131 # number of integer regfile writes +system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10560 # number of integer regfile reads +system.cpu.int_regfile_writes 5130 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 151 # number of misc regfile reads -system.cpu.icache.replacements 19 # number of replacements -system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use -system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use +system.cpu.icache.total_refs 1503 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits -system.cpu.icache.overall_hits::total 1592 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses -system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits +system.cpu.icache.overall_hits::total 1503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,54 +366,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use -system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use +system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1903 # 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number of WriteReq misses @@ -422,38 +422,38 @@ system.cpu.dcache.demand_misses::cpu.data 472 # n system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses system.cpu.dcache.overall_misses::total 472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 91 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses +system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index b797dcfe3..584102e9c 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:59:33 -gem5 started Jun 4 2012 14:44:10 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:53:15 gem5 executing on zizzer -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11243500 because target called exit() +Exiting @ tick 11179000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 975867801..f8f7991bd 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11243500 # Number of ticks simulated -final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11179000 # Number of ticks simulated +final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72271 # Simulator instruction rate (inst/s) -host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140039967 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 61972 # Simulator instruction rate (inst/s) +host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119400246 # Simulator tick rate (ticks/s) +host_mem_usage 216052 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory -system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22488 # number of cpu cycles simulated +system.cpu.numCycles 22359 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2514 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits +system.cpu.BPredUnit.lookups 2487 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2239 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2086 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9284 # Type of FU issued -system.cpu.iq.rate 0.412842 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9264 # Type of FU issued +system.cpu.iq.rate 0.414330 # Inst issue rate +system.cpu.iq.fu_busy_cnt 179 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3258 # number of memory reference insts executed -system.cpu.iew.exec_branches 1391 # Number of branches executed -system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.389274 # Inst execution rate -system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8387 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4351 # num instructions producing a value -system.cpu.iew.wb_consumers 7020 # num instructions consuming a value +system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_branches 1382 # Number of branches executed +system.cpu.iew.exec_stores 1566 # Number of stores executed +system.cpu.iew.exec_rate 0.391654 # Inst execution rate +system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4334 # num instructions producing a value +system.cpu.iew.wb_consumers 6981 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21145 # The number of ROB reads -system.cpu.rob.rob_writes 22688 # The number of ROB writes -system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21079 # The number of ROB reads +system.cpu.rob.rob_writes 22698 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13921 # number of integer regfile reads -system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13891 # number of integer regfile reads +system.cpu.int_regfile_writes 7248 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use -system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use +system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits -system.cpu.icache.overall_hits::total 1462 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits +system.cpu.icache.overall_hits::total 1455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses +system.cpu.icache.overall_misses::total 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,12 +365,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses @@ -383,12 +383,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188129 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency @@ -397,14 +397,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. +system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits @@ -413,46 +413,46 @@ system.cpu.dcache.demand_hits::cpu.data 2216 # nu system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses -system.cpu.dcache.overall_misses::total 399 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses +system.cpu.dcache.overall_misses::total 402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2618 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,58 +461,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033715 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.260551 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.544564 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 30.715987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000937 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006173 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits @@ -520,60 +520,60 @@ system.cpu.l2cache.demand_hits::total 5 # nu system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 403 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses -system.cpu.l2cache.overall_misses::total 449 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1829000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13862000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3503500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15536500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3503500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15536500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987745 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989035 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34380 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34509.433962 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.022333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34449.002217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34449.002217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,49 +583,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12570500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10908500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3183500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14092000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10908500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3183500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14092000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 0e67a0bd3..8da405b24 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:51 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:52 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13973500 because target called exit() +Exiting @ tick 13801000 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 972719e56..3bebb79ad 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13973500 # Number of ticks simulated -final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13801000 # Number of ticks simulated +final_tick 13801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68487 # Simulator instruction rate (inst/s) -host_op_rate 68480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74908448 # Simulator tick rate (ticks/s) -host_mem_usage 215960 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 32086 # Simulator instruction rate (inst/s) +host_op_rate 32085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34665771 # Simulator tick rate (ticks/s) +host_mem_usage 218816 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22592 # Number of bytes read from this memory -system.physmem.bytes_read::total 62784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 353 # Number of read requests responded to by this memory -system.physmem.num_reads::total 981 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2876301571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1616774609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4493076180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2876301571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1616774609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4493076180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory +system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 980 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2898340700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1646257518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4544598218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2898340700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2898340700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2898340700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1646257518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4544598218 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4112 # DTB read hits -system.cpu.dtb.read_misses 99 # DTB read misses +system.cpu.dtb.read_hits 4109 # DTB read hits +system.cpu.dtb.read_misses 91 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4211 # DTB read accesses -system.cpu.dtb.write_hits 2113 # DTB write hits -system.cpu.dtb.write_misses 55 # DTB write misses +system.cpu.dtb.read_accesses 4200 # DTB read accesses +system.cpu.dtb.write_hits 2070 # DTB write hits +system.cpu.dtb.write_misses 61 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2168 # DTB write accesses -system.cpu.dtb.data_hits 6225 # DTB hits -system.cpu.dtb.data_misses 154 # DTB misses +system.cpu.dtb.write_accesses 2131 # DTB write accesses +system.cpu.dtb.data_hits 6179 # DTB hits +system.cpu.dtb.data_misses 152 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6379 # DTB accesses -system.cpu.itb.fetch_hits 5262 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.data_accesses 6331 # DTB accesses +system.cpu.itb.fetch_hits 5033 # ITB hits +system.cpu.itb.fetch_misses 52 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5308 # ITB accesses +system.cpu.itb.fetch_accesses 5085 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,361 +61,360 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 27948 # number of cpu cycles simulated +system.cpu.numCycles 27603 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6404 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits +system.cpu.BPredUnit.lookups 6273 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3546 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1676 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4641 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 749 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 905 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1498 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 35104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6273 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1654 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1752 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5033 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.626541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.950246 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15712 72.80% 72.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465 2.15% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 353 1.64% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 445 2.06% 78.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 412 1.91% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 367 1.70% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 466 2.16% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 577 2.67% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2785 12.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5207 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4929 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.227258 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.271746 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5047 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 472 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2407 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 618 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 398 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30693 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 650 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2407 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30628 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2400 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 805 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4751 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1917 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28414 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1949 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21384 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 35492 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35458 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12218 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5512 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1309 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25261 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21461 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11327 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6314 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21582 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.994393 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.507504 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12693 58.81% 58.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3009 13.94% 72.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2444 11.32% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1529 7.08% 91.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1011 4.68% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 561 2.60% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 239 1.11% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 74 0.34% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 22 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21582 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 115 61.83% 65.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 34.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7347 68.12% 68.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2315 21.46% 89.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1119 10.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10965 # Type of FU issued +system.cpu.iq.FU_type_0::total 10786 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7235 67.78% 67.79% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2307 21.61% 89.43% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1128 10.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10832 # Type of FU issued +system.cpu.iq.FU_type_1::total 10675 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14582 67.95% 67.97% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.97% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.97% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4622 21.54% 89.53% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2247 10.47% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21797 # Type of FU issued -system.cpu.iq.rate 0.779913 # Inst issue rate +system.cpu.iq.FU_type::total 21461 # Type of FU issued +system.cpu.iq.rate 0.777488 # Inst issue rate system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_cnt::1 93 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 186 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004333 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004333 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008667 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 64765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36642 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19216 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1462 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1450 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 444 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2407 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 503 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25446 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 693 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5282 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2108 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2105 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 72 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed -system.cpu.iew.exec_nop::total 141 # number of nop insts executed -system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1640 # Number of branches executed -system.cpu.iew.exec_branches::1 1645 # Number of branches executed -system.cpu.iew.exec_branches::total 3285 # Number of branches executed -system.cpu.iew.exec_stores::0 1099 # Number of stores executed -system.cpu.iew.exec_stores::1 1088 # Number of stores executed -system.cpu.iew.exec_stores::total 2187 # Number of stores executed -system.cpu.iew.exec_rate 0.725276 # Inst execution rate -system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5068 # num instructions producing a value -system.cpu.iew.wb_producers::1 5042 # num instructions producing a value -system.cpu.iew.wb_producers::total 10110 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 66 # number of nop insts executed +system.cpu.iew.exec_nop::total 135 # number of nop insts executed +system.cpu.iew.exec_refs::0 3190 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3171 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6361 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1643 # Number of branches executed +system.cpu.iew.exec_branches::1 1639 # Number of branches executed +system.cpu.iew.exec_branches::total 3282 # Number of branches executed +system.cpu.iew.exec_stores::0 1082 # Number of stores executed +system.cpu.iew.exec_stores::1 1066 # Number of stores executed +system.cpu.iew.exec_stores::total 2148 # Number of stores executed +system.cpu.iew.exec_rate 0.726262 # Inst execution rate +system.cpu.iew.wb_sent::0 9814 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9693 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9690 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9546 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19236 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5036 # num instructions producing a value +system.cpu.iew.wb_producers::1 4985 # num instructions producing a value +system.cpu.iew.wb_producers::total 10021 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6558 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6494 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.765387 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.351049 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.345832 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.696881 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.767917 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.767632 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.767775 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1295 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.595010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.388263 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15949 74.10% 74.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2814 13.07% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1173 5.45% 92.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 493 2.29% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 336 1.56% 96.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 260 1.21% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 183 0.85% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 102 0.47% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21524 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6403 # Number of instructions committed system.cpu.commit.committedInsts::1 6404 # Number of instructions committed system.cpu.commit.committedInsts::total 12807 # Number of instructions committed @@ -446,78 +445,78 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 114163 # The number of ROB reads -system.cpu.rob.rob_writes 54209 # The number of ROB writes -system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 111695 # The number of ROB reads +system.cpu.rob.rob_writes 53212 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6021 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25651 # number of integer regfile reads -system.cpu.int_regfile_writes 14680 # number of integer regfile writes +system.cpu.cpi::0 4.322424 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.321747 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.161043 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.231352 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.231388 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.462740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25345 # number of integer regfile reads +system.cpu.int_regfile_writes 14554 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 7 # number of replacements +system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 7 # number of replacements -system.cpu.icache.tagsinuse 324.653687 # Cycle average of tags in use -system.cpu.icache.total_refs 4369 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 631 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.923930 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 321.631643 # Cycle average of tags in use +system.cpu.icache.total_refs 4144 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.609250 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 324.653687 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.158522 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.158522 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4369 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4369 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4369 # number of overall hits -system.cpu.icache.overall_hits::total 4369 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 893 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 893 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 893 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 893 # number of overall misses -system.cpu.icache.overall_misses::total 893 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31736000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31736000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31736000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31736000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31736000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31736000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5262 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5262 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5262 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5262 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169707 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169707 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169707 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35538.633819 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35538.633819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35538.633819 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 321.631643 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.157047 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.157047 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4144 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4144 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4144 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4144 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4144 # number of overall hits +system.cpu.icache.overall_hits::total 4144 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 889 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 889 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 889 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 889 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 889 # number of overall misses +system.cpu.icache.overall_misses::total 889 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31471500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31471500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31471500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31471500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31471500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31471500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5033 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5033 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5033 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5033 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5033 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5033 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.176634 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.176634 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.176634 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.176634 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.176634 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.176634 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35401.012373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35401.012373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35401.012373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35401.012373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,90 +531,90 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 262 system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 631 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22442500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22442500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22442500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22442500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119916 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.119916 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.119916 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.561014 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22341500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22341500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.124578 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.124578 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.124578 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35632.376396 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35632.376396 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 221.504894 # Cycle average of tags in use -system.cpu.dcache.total_refs 4696 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.303116 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.639601 # Cycle average of tags in use +system.cpu.dcache.total_refs 4700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.239437 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 221.504894 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.054078 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.054078 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3676 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3676 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4696 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4696 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4696 # number of overall hits -system.cpu.dcache.overall_hits::total 4696 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 311 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 311 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 221.639601 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.054111 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.054111 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3679 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3679 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4700 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4700 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4700 # number of overall hits +system.cpu.dcache.overall_hits::total 4700 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 312 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 312 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses system.cpu.dcache.overall_misses::total 1021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11221000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11221000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22533500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22533500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33754500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33754500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3987 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3987 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22399000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22399000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33752000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33752000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33752000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33752000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3991 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3991 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5717 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5717 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078004 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178590 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178590 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36080.385852 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31737.323944 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33060.235064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33060.235064 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 5721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5721 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078176 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.178465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36387.820513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36387.820513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31592.383639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31592.383639 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33057.786484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33057.786484 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,121 +623,121 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 207 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7607500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7607500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5291500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5291500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12899000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12899000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061746 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061746 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36751.207729 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36243.150685 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 666 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 666 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7724000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7724000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5248500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5248500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12972500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12972500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12972500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12972500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36780.952381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36780.952381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36196.551724 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36196.551724 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 449.601344 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 447.061292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.003593 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002395 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 324.972112 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 124.629233 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009917 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003803 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013721 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 628 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 207 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 321.947671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 125.113621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009825 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013643 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 210 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996951 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.293413 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34681.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34572.375127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34572.375127 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34436.800000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34904.761905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34554.491018 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34665.517241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34665.517241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34570.918367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34570.918367 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -747,50 +746,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19659500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6570000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26229500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4611000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4611000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30840500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19555500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6675000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26230500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4577500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4577500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19555500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11252500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19555500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11252500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30808000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996420 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997611 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31412.574850 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.191781 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31288.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31785.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31413.772455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31568.965517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31568.965517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index f0f4b69ef..c81e9ca95 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:02 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:53:48 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 19744500 because target called exit() +Exiting @ tick 19806500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index a887522dd..52156950f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19744500 # Number of ticks simulated -final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19806500 # Number of ticks simulated +final_tick 19806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74885 # Simulator instruction rate (inst/s) -host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102311932 # Simulator tick rate (ticks/s) -host_mem_usage 222004 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 96556 # Simulator instruction rate (inst/s) +host_op_rate 96545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132327745 # Simulator tick rate (ticks/s) +host_mem_usage 221008 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory @@ -19,251 +19,251 @@ system.physmem.bytes_inst_read::total 21632 # Nu system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 484 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092166713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 471764320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1563931033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092166713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092166713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092166713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 471764320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1563931033 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 39490 # number of cpu cycles simulated +system.cpu.numCycles 39614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6899 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits +system.cpu.BPredUnit.lookups 6890 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4576 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5201 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2595 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 11869 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32300 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3054 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3188 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6935 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 5516 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.039755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.210803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21505 69.23% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4746 15.28% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 494 1.59% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 444 1.43% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 682 2.20% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 763 2.46% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 240 0.77% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 277 0.89% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1914 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8680 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 31065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.173928 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.815368 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12513 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7669 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30088 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6922 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8283 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 452 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27408 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 125 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24445 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50953 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50953 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10613 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 705 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2469 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued +system.cpu.iq.iqInstsAdded 23180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 670 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21761 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 8457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21619 69.59% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3603 11.60% 81.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2384 7.67% 88.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1730 5.57% 94.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 898 2.89% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 488 1.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 252 0.81% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 72 0.23% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31065 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54 29.19% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.05% 43.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 105 56.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16056 73.78% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3441 15.81% 89.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2264 10.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21701 # Type of FU issued -system.cpu.iq.rate 0.549532 # Inst issue rate -system.cpu.iq.fu_busy_cnt 179 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21761 # Type of FU issued +system.cpu.iq.rate 0.549326 # Inst issue rate +system.cpu.iq.fu_busy_cnt 185 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008501 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74877 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32333 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19979 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21946 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1421 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1021 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25018 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 406 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2469 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 670 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions +system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1253 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20571 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1163 # number of nop insts executed -system.cpu.iew.exec_refs 5392 # number of memory reference insts executed -system.cpu.iew.exec_branches 4300 # Number of branches executed -system.cpu.iew.exec_stores 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.519397 # Inst execution rate -system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19916 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9270 # num instructions producing a value -system.cpu.iew.wb_consumers 11399 # num instructions consuming a value +system.cpu.iew.exec_nop 1168 # number of nop insts executed +system.cpu.iew.exec_refs 5421 # number of memory reference insts executed +system.cpu.iew.exec_branches 4301 # Number of branches executed +system.cpu.iew.exec_stores 2143 # Number of stores executed +system.cpu.iew.exec_rate 0.519286 # Inst execution rate +system.cpu.iew.wb_sent 20246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19979 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9281 # num instructions producing a value +system.cpu.iew.wb_consumers 11411 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504342 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.813338 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9761 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.203804 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21721 74.61% 74.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4069 13.98% 88.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1444 4.96% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 793 2.72% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.16% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 258 0.89% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 320 1.10% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71 0.24% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29111 # Number of insts commited each cycle system.cpu.commit.committedInsts 15175 # Number of instructions committed system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +274,68 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 52944 # The number of ROB reads -system.cpu.rob.rob_writes 51625 # The number of ROB writes -system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53126 # The number of ROB reads +system.cpu.rob.rob_writes 51851 # The number of ROB writes +system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8549 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads -system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32680 # number of integer regfile reads -system.cpu.int_regfile_writes 18187 # number of integer regfile writes -system.cpu.misc_regfile_reads 7045 # number of misc regfile reads +system.cpu.cpi 2.741643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.741643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.364745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.364745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32757 # number of integer regfile reads +system.cpu.int_regfile_writes 18209 # number of integer regfile writes +system.cpu.misc_regfile_reads 7073 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use -system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 201.055469 # Cycle average of tags in use +system.cpu.icache.total_refs 5034 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.805882 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits -system.cpu.icache.overall_hits::total 5020 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses -system.cpu.icache.overall_misses::total 486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 201.055469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.098172 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.098172 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5034 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5034 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5034 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5034 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5034 # number of overall hits +system.cpu.icache.overall_hits::total 5034 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 482 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 482 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 482 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 482 # number of overall misses +system.cpu.icache.overall_misses::total 482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16634500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16634500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16634500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16634500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16634500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16634500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5516 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5516 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5516 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5516 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087382 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087382 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087382 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34511.410788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34511.410788 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,12 +344,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses @@ -362,12 +362,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061639 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061639 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061639 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency @@ -376,66 +376,66 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use -system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.574586 # Cycle average of tags in use +system.cpu.dcache.total_refs 4084 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.972603 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.574586 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025287 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3044 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3044 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4077 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4077 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4077 # number of overall hits -system.cpu.dcache.overall_hits::total 4077 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4078 # number of overall hits +system.cpu.dcache.overall_hits::total 4078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 526 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 526 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 526 # number of overall misses -system.cpu.dcache.overall_misses::total 526 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4092500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14593500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18686000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18686000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses +system.cpu.dcache.overall_misses::total 524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4022000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4022000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14592500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14592500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18614500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18614500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18614500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18614500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.036709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.036709 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.113864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.113864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.113864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.113864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35523.854962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35523.854962 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,14 +444,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 380 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 378 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 378 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -462,40 +462,40 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 146 system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2978500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2978500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5222000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5222000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5222000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5222000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019937 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031725 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.586962 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006104 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 200.308921 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.278041 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001107 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007220 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -513,17 +513,17 @@ system.cpu.l2cache.demand_misses::total 484 # nu system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses system.cpu.l2cache.overall_misses::total 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11582500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11581500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13751500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13750500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11582500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11581500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16620500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11582500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 16619500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11581500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16620500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16619500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -546,17 +546,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995885 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34264.792899 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34290.523691 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34337.809917 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -576,17 +576,17 @@ system.cpu.l2cache.demand_mshr_misses::total 484 system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10497000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10495000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12464500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10495000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15072000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses @@ -598,17 +598,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050.295858 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31261.904762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.541147 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 51784eba5..b2cdd54e1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,82 +1,82 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:14 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 Iteration 5 completed -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 111402500 because target called exit() +Exiting @ tick 111594500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1590e3eee..ea1876230 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,191 +1,191 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 111402500 # Number of ticks simulated -final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000112 # Number of seconds simulated +sim_ticks 111594500 # Number of ticks simulated +final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133234 # Simulator instruction rate (inst/s) -host_op_rate 133234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13628365 # Simulator tick rate (ticks/s) -host_mem_usage 236536 # Number of bytes of host memory used -host_seconds 8.17 # Real time elapsed on the host -sim_insts 1089093 # Number of instructions simulated -sim_ops 1089093 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +host_inst_rate 200629 # Simulator instruction rate (inst/s) +host_op_rate 200629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20568067 # Simulator tick rate (ticks/s) +host_mem_usage 235024 # Number of bytes of host memory used +host_seconds 5.43 # Real time elapsed on the host +sim_insts 1088531 # Number of instructions simulated +sim_ops 1088531 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 43072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 673 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 222806 # number of cpu cycles simulated +system.cpu0.numCycles 223190 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits +system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked +system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued @@ -214,159 +214,159 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued -system.cpu0.iq.rate 1.906569 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued +system.cpu0.iq.rate 1.905816 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 80538 # number of nop insts executed -system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed -system.cpu0.iew.exec_branches 84187 # Number of branches executed -system.cpu0.iew.exec_stores 82042 # Number of stores executed -system.cpu0.iew.exec_rate 1.901466 # Inst execution rate -system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 250585 # num instructions producing a value -system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value +system.cpu0.iew.exec_nop 80672 # number of nop insts executed +system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed +system.cpu0.iew.exec_branches 84313 # Number of branches executed +system.cpu0.iew.exec_stores 82132 # Number of stores executed +system.cpu0.iew.exec_rate 1.900793 # Inst execution rate +system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 250898 # num instructions producing a value +system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 496189 # Number of instructions committed -system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 496825 # Number of instructions committed +system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 242804 # Number of memory references committed -system.cpu0.commit.loads 161532 # Number of loads committed +system.cpu0.commit.refs 243122 # Number of memory references committed +system.cpu0.commit.loads 161744 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 83160 # Number of branches committed +system.cpu0.commit.branches 83266 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 334226 # Number of committed integer instructions. +system.cpu0.commit.int_insts 334650 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 709866 # The number of ROB reads -system.cpu0.rob.rob_writes 1020791 # The number of ROB writes -system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 416214 # Number of Instructions Simulated -system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated -system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 757980 # number of integer regfile reads -system.cpu0.int_regfile_writes 341432 # number of integer regfile writes +system.cpu0.rob.rob_reads 710993 # The number of ROB reads +system.cpu0.rob.rob_writes 1022511 # The number of ROB writes +system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 416744 # Number of Instructions Simulated +system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated +system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 758967 # number of integer regfile reads +system.cpu0.int_regfile_writes 341941 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads +system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 300 # number of replacements -system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use -system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks. +system.cpu0.icache.replacements 307 # number of replacements +system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use +system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits -system.cpu0.icache.overall_hits::total 5459 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits +system.cpu0.icache.overall_hits::total 5393 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses system.cpu0.icache.overall_misses::total 759 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -375,106 +375,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 8 # number of replacements -system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use -system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use +system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits -system.cpu0.dcache.overall_hits::total 163710 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits +system.cpu0.dcache.overall_hits::total 163940 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses -system.cpu0.dcache.overall_misses::total 1041 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses +system.cpu0.dcache.overall_misses::total 1046 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -483,476 +483,476 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 187393 # number of cpu cycles simulated +system.cpu1.numCycles 187839 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits +system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued -system.cpu1.iq.rate 1.409476 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued +system.cpu1.iq.rate 1.216584 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44378 # number of nop insts executed -system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed -system.cpu1.iew.exec_branches 53738 # Number of branches executed -system.cpu1.iew.exec_stores 42625 # Number of stores executed -system.cpu1.iew.exec_rate 1.402560 # Inst execution rate -system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 149144 # num instructions producing a value -system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value +system.cpu1.iew.exec_nop 37787 # number of nop insts executed +system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47145 # Number of branches executed +system.cpu1.iew.exec_stores 34668 # Number of stores executed +system.cpu1.iew.exec_rate 1.209472 # Inst execution rate +system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126631 # num instructions producing a value +system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 298843 # Number of instructions committed -system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 256347 # Number of instructions committed +system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 129859 # Number of memory references committed -system.cpu1.commit.loads 88054 # Number of loads committed -system.cpu1.commit.membars 4938 # Number of memory barriers committed -system.cpu1.commit.branches 52708 # Number of branches committed +system.cpu1.commit.refs 107314 # Number of memory references committed +system.cpu1.commit.loads 73449 # Number of loads committed +system.cpu1.commit.membars 6235 # Number of memory barriers committed +system.cpu1.commit.branches 46061 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 204694 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175498 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 487255 # The number of ROB reads -system.cpu1.rob.rob_writes 629168 # The number of ROB writes +system.cpu1.rob.rob_reads 442417 # The number of ROB reads +system.cpu1.rob.rob_writes 545088 # The number of ROB writes system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 250401 # Number of Instructions Simulated -system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated -system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 456552 # number of integer regfile reads -system.cpu1.int_regfile_writes 212248 # number of integer regfile writes +system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 213261 # Number of Instructions Simulated +system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated +system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 389025 # number of integer regfile reads +system.cpu1.int_regfile_writes 181950 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads +system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use -system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use +system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits -system.cpu1.icache.overall_hits::total 19304 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses -system.cpu1.icache.overall_misses::total 505 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits +system.cpu1.icache.overall_hits::total 22247 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses +system.cpu1.icache.overall_misses::total 510 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022411 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22250 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22250 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22250 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22250 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8591500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8591500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8591500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8591500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8591500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8591500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019159 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019159 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019159 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 27.650583 # Cycle average of tags in use +system.cpu1.dcache.total_refs 40148 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1384.413793 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits -system.cpu1.dcache.overall_hits::total 92793 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 27.650583 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054005 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054005 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 44622 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 44622 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 33643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 33643 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 78265 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 78265 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 78265 # number of overall hits +system.cpu1.dcache.overall_hits::total 78265 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 425 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 425 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses -system.cpu1.dcache.overall_misses::total 629 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses +system.cpu1.dcache.overall_misses::total 579 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9294500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9294500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3142500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3142500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1219000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1219000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12437000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12437000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12437000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12437000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 33797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 33797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78844 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78844 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78844 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78844 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009435 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009435 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004557 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004557 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.764706 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -961,476 +961,474 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 187102 # number of cpu cycles simulated +system.cpu2.numCycles 187552 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits +system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked +system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued -system.cpu2.iq.rate 1.255545 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued +system.cpu2.iq.rate 1.158932 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39077 # number of nop insts executed -system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 48223 # Number of branches executed -system.cpu2.iew.exec_stores 36178 # Number of stores executed -system.cpu2.iew.exec_rate 1.248153 # Inst execution rate -system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 130712 # num instructions producing a value -system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value +system.cpu2.iew.exec_nop 35864 # number of nop insts executed +system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45260 # Number of branches executed +system.cpu2.iew.exec_stores 31855 # Number of stores executed +system.cpu2.iew.exec_rate 1.151585 # Inst execution rate +system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 119078 # num instructions producing a value +system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 263733 # Number of instructions committed -system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 242999 # Number of instructions committed +system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 111398 # Number of memory references committed -system.cpu2.commit.loads 76032 # Number of loads committed -system.cpu2.commit.membars 5840 # Number of memory barriers committed -system.cpu2.commit.branches 47167 # Number of branches committed +system.cpu2.commit.refs 99705 # Number of memory references committed +system.cpu2.commit.loads 68688 # Number of loads committed +system.cpu2.commit.membars 7170 # Number of memory barriers committed +system.cpu2.commit.branches 44148 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 180680 # Number of committed integer instructions. +system.cpu2.commit.int_insts 165976 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 450492 # The number of ROB reads -system.cpu2.rob.rob_writes 562082 # The number of ROB writes -system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 219944 # Number of Instructions Simulated -system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated -system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 401453 # number of integer regfile reads -system.cpu2.int_regfile_writes 187612 # number of integer regfile writes +system.cpu2.rob.rob_reads 431829 # The number of ROB reads +system.cpu2.rob.rob_writes 519243 # The number of ROB writes +system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 200891 # Number of Instructions Simulated +system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated +system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 366578 # number of integer regfile reads +system.cpu2.int_regfile_writes 171642 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads +system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 325 # number of replacements -system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use -system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks. +system.cpu2.icache.replacements 324 # number of replacements +system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use +system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits -system.cpu2.icache.overall_hits::total 21358 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses -system.cpu2.icache.overall_misses::total 512 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency 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number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1439,368 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 186832 # number of cpu cycles simulated +system.cpu3.numCycles 187286 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits +system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued -system.cpu3.iq.rate 1.169655 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued +system.cpu3.iq.rate 1.448848 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36198 # number of nop insts executed -system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed -system.cpu3.iew.exec_branches 45494 # Number of branches executed -system.cpu3.iew.exec_stores 32232 # Number of stores executed -system.cpu3.iew.exec_rate 1.162692 # Inst execution rate -system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 119982 # num instructions producing a value -system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value +system.cpu3.iew.exec_nop 45763 # number of nop insts executed +system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed +system.cpu3.iew.exec_branches 55022 # Number of branches executed +system.cpu3.iew.exec_stores 44284 # Number of stores executed +system.cpu3.iew.exec_rate 1.441587 # Inst execution rate +system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 153664 # num instructions producing a value +system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 244729 # Number of instructions committed -system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 306791 # Number of instructions committed +system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 100719 # Number of memory references committed -system.cpu3.commit.loads 69310 # Number of loads committed -system.cpu3.commit.membars 7019 # Number of memory barriers committed -system.cpu3.commit.branches 44389 # Number of branches committed +system.cpu3.commit.refs 134284 # Number of memory references committed +system.cpu3.commit.loads 90840 # Number of loads committed +system.cpu3.commit.membars 4481 # Number of memory barriers committed +system.cpu3.commit.branches 53890 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 167227 # Number of committed integer instructions. +system.cpu3.commit.int_insts 210289 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 432891 # The number of ROB reads -system.cpu3.rob.rob_writes 522404 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 202534 # Number of Instructions Simulated -system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated -system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 369217 # number of integer regfile reads -system.cpu3.int_regfile_writes 172842 # number of integer regfile writes +system.cpu3.rob.rob_reads 496513 # The number of ROB reads +system.cpu3.rob.rob_writes 647676 # The number of ROB writes +system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257635 # Number of Instructions Simulated +system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated +system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 470214 # number of integer regfile reads +system.cpu3.int_regfile_writes 218594 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads +system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 320 # number of replacements -system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use -system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks. +system.cpu3.icache.replacements 322 # number of replacements +system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use +system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits -system.cpu3.icache.overall_hits::total 23951 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 18566 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 18566 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 18566 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 18566 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 18566 # number of overall hits +system.cpu3.icache.overall_hits::total 18566 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 496 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 496 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 496 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 496 # number of overall misses +system.cpu3.icache.overall_misses::total 496 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6966500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19062 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19062 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19062 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19062 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026020 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026020 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026020 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026020 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026020 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026020 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14045.362903 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14045.362903 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1809,106 +1805,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 60 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 60 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 60 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5084500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5084500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5084500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5084500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5084500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5084500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022873 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.022873 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.022873 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use -system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 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-system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 26.205436 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.051182 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.051182 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 52477 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 52477 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 43221 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 43221 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 95698 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 95698 # number of demand (read+write) hits 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miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8617000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2850000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2850000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1161500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1161500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11467000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11467000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11467000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11467000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 52901 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 52901 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 43371 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 43371 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 73 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 96272 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 96272 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 96272 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 96272 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008015 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.008015 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003459 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003459 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835616 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835616 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005962 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005962 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005962 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005962 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19000 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19000 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1917,298 +1913,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 264 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 310 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 310 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 310 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 61 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1797000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1797000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1508500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1508500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 978500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 978500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3305500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3305500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3305500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3305500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003025 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003025 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002398 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002398 # mshr miss rate for WriteReq accesses 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WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 441.136869 # Cycle average of tags in use -system.l2c.total_refs 1471 # Total number of references to valid blocks. -system.l2c.sampled_refs 544 # Sample count of references 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miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::total 26829000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses 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rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.310761 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # 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+system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.310761 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 7edc0f615..4b3a2eb90 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:23 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index a670e1cab..382c1c71b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1597903 # Simulator instruction rate (inst/s) -host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206906108 # Simulator tick rate (ticks/s) -host_mem_usage 1149840 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_inst_rate 1588944 # Simulator instruction rate (inst/s) +host_op_rate 1588869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205745598 # Simulator tick rate (ticks/s) +host_mem_usage 1148436 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -122,15 +122,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use -system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 150.735434 # Cycle average of tags in use +system.cpu0.dcache.total_refs 81884 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 490.323353 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 150.735434 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.294405 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.294405 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -179,8 +179,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173308 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -246,35 +246,35 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 30.314752 # Cycle average of tags in use +system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 30.314752 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits -system.cpu1.dcache.overall_hits::total 53031 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits +system.cpu1.dcache.overall_hits::total 53033 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses -system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses +system.cpu1.dcache.overall_misses::total 280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) @@ -285,16 +285,16 @@ system.cpu1.dcache.demand_accesses::cpu1.data 53313 system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +303,6 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173308 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,35 +368,35 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 29.603311 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 29.603311 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits -system.cpu2.dcache.overall_hits::total 58190 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits +system.cpu2.dcache.overall_hits::total 58192 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses +system.cpu2.dcache.overall_misses::total 269 # number of overall misses system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) @@ -409,16 +407,16 @@ system.cpu2.dcache.demand_accesses::cpu2.data 58461 system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,8 +425,6 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173307 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -494,35 +490,35 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 28.793270 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 28.793270 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits -system.cpu3.dcache.overall_hits::total 55559 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits +system.cpu3.dcache.overall_hits::total 55561 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses -system.cpu3.dcache.overall_misses::total 261 # number of overall misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) @@ -533,16 +529,16 @@ system.cpu3.dcache.demand_accesses::cpu3.data 55820 system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,16 +547,14 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 371.980910 # Cycle average of tags in use -system.l2c.total_refs 1223 # Total number of references to valid blocks. -system.l2c.sampled_refs 426 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. +system.l2c.tagsinuse 366.557230 # Cycle average of tags in use +system.l2c.total_refs 1220 # Total number of references to valid blocks. +system.l2c.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.966368 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor @@ -569,7 +563,7 @@ system.l2c.occ_blocks::cpu2.inst 1.930518 # Av system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy +system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy @@ -578,38 +572,38 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005593 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 185 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1226 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses @@ -620,10 +614,10 @@ system.l2c.ReadReq_misses::cpu3.inst 2 # nu system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -650,19 +644,19 @@ system.l2c.overall_misses::total 559 # nu system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -671,35 +665,35 @@ system.l2c.ReadExReq_accesses::total 136 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -708,21 +702,21 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 3d54c9924..145ab230c 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:33 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:12 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done @@ -79,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262298000 because target called exit() +Exiting @ tick 262299000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 36b8c656f..c654a221f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262298000 # Number of ticks simulated -final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262299000 # Number of ticks simulated +final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070900 # Simulator instruction rate (inst/s) -host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 424091073 # Simulator tick rate (ticks/s) -host_mem_usage 232420 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -sim_insts 662307 # Number of instructions simulated -sim_ops 662307 # Number of ops (including micro ops) simulated +host_inst_rate 1271827 # Simulator instruction rate (inst/s) +host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503510999 # Simulator tick rate (ticks/s) +host_mem_usage 230932 # Number of bytes of host memory used +host_seconds 0.52 # Real time elapsed on the host +sim_insts 662502 # Number of instructions simulated +sim_ops 662502 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,31 +34,31 @@ system.physmem.num_reads::cpu2.data 16 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524596 # number of cpu cycles simulated +system.cpu0.numCycles 524598 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158353 # Number of instructions committed @@ -77,18 +77,18 @@ system.cpu0.num_mem_refs 73905 # nu system.cpu0.num_load_insts 48930 # Number of load instructions system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524596 # Number of busy cycles +system.cpu0.num_busy_cycles 524598 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits @@ -158,15 +158,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use -system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits @@ -187,16 +187,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) @@ -217,16 +217,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,8 +235,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses @@ -247,16 +247,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses @@ -267,84 +267,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524596 # number of cpu cycles simulated +system.cpu1.numCycles 524598 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172325 # Number of instructions committed -system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses +system.cpu1.committedInsts 172389 # Number of instructions committed +system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107932 # number of integer instructions +system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107964 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written +system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47898 # number of memory refs -system.cpu1.num_load_insts 39616 # Number of load instructions +system.cpu1.num_mem_refs 47914 # number of memory refs +system.cpu1.num_load_insts 39632 # Number of load instructions system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles -system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles +system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles +system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use -system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use +system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits -system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits +system.cpu1.icache.overall_hits::total 172056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 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20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency 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number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524596 # number of cpu cycles simulated +system.cpu2.numCycles 524598 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165499 # Number of instructions committed -system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses +system.cpu2.committedInsts 165564 # Number of instructions committed +system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112355 # number of integer instructions +system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112387 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written +system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read +system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57941 # number of memory refs -system.cpu2.num_load_insts 41852 # Number of load instructions +system.cpu2.num_mem_refs 57957 # number of memory refs +system.cpu2.num_load_insts 41868 # Number of load instructions system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles -system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles +system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles +system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use -system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use +system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits -system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits +system.cpu2.icache.overall_hits::total 165231 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses @@ -547,18 +545,18 @@ system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency @@ -585,12 +583,12 @@ system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency @@ -598,75 +596,75 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use -system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use +system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits -system.cpu2.dcache.overall_hits::total 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits +system.cpu2.dcache.overall_hits::total 57622 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses -system.cpu2.dcache.overall_misses::total 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses +system.cpu2.dcache.overall_misses::total 263 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,116 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524596 # number of cpu cycles simulated +system.cpu3.numCycles 524598 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166130 # Number of instructions committed -system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses +system.cpu3.committedInsts 166196 # Number of instructions committed +system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112098 # number of integer instructions +system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112131 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57243 # number of memory refs -system.cpu3.num_load_insts 41720 # Number of load instructions +system.cpu3.num_mem_refs 57260 # number of memory refs +system.cpu3.num_load_insts 41737 # Number of load instructions system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles -system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles +system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles +system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use -system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use +system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits -system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits +system.cpu3.icache.overall_hits::total 165862 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits -system.cpu3.dcache.overall_hits::total 56903 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits +system.cpu3.dcache.overall_hits::total 56922 # number of overall hits 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-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.demand_misses::cpu3.data 263 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 263 # number of overall misses +system.cpu3.dcache.overall_misses::total 263 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2537000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2537000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2026000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2026000 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,65 +891,63 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 265 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1756000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1702000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003714 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004599 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004599 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency 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latency system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,10 +1201,10 @@ system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # n system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 69 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses @@ -1252,47 +1238,47 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 440000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2760000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5680000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 880000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22883000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1301,21 +1287,21 @@ system.l2c.ReadExReq_mshr_miss_rate::total 1 # system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1331,28 +1317,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index afb940009..a874a3f37 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read, 5261 write accesses @25602084 -system.cpu0: completed 10000 read, 5478 write accesses @26185688 -system.cpu4: completed 10000 read, 5410 write accesses @26212882 -system.cpu3: completed 10000 read, 5338 write accesses @26366308 -system.cpu1: completed 10000 read, 5460 write accesses @26447108 -system.cpu7: completed 10000 read, 5362 write accesses @26537664 -system.cpu2: completed 10000 read, 5282 write accesses @26676832 -system.cpu6: completed 10000 read, 5370 write accesses @26707781 -system.cpu3: completed 20000 read, 10741 write accesses @51951998 -system.cpu5: completed 20000 read, 10677 write accesses @52231737 -system.cpu0: completed 20000 read, 11006 write accesses @52523512 -system.cpu4: completed 20000 read, 10704 write accesses @52614186 -system.cpu7: completed 20000 read, 10588 write accesses @52674871 -system.cpu1: completed 20000 read, 10959 write accesses @52986792 -system.cpu2: completed 20000 read, 10676 write accesses @53365626 -system.cpu6: completed 20000 read, 10788 write accesses @53537042 -system.cpu5: completed 30000 read, 16233 write accesses @78528098 -system.cpu3: completed 30000 read, 16192 write accesses @78636475 -system.cpu7: completed 30000 read, 15958 write accesses @79069859 -system.cpu0: completed 30000 read, 16488 write accesses @79082669 -system.cpu4: completed 30000 read, 16215 write accesses @79163244 -system.cpu6: completed 30000 read, 16191 write accesses @79592442 -system.cpu2: completed 30000 read, 16073 write accesses @79845712 -system.cpu1: completed 30000 read, 16466 write accesses @80286691 -system.cpu5: completed 40000 read, 21620 write accesses @103783596 -system.cpu0: completed 40000 read, 21781 write accesses @103983848 -system.cpu7: completed 40000 read, 21333 write accesses @104306510 -system.cpu3: completed 40000 read, 21577 write accesses @104792070 -system.cpu6: completed 40000 read, 21636 write accesses @104882247 -system.cpu4: completed 40000 read, 21525 write accesses @104921736 -system.cpu1: completed 40000 read, 21768 write accesses @105789168 -system.cpu2: completed 40000 read, 21470 write accesses @106255146 -system.cpu5: completed 50000 read, 26996 write accesses @130119835 -system.cpu0: completed 50000 read, 27148 write accesses @130621851 -system.cpu4: completed 50000 read, 26714 write accesses @131102250 -system.cpu7: completed 50000 read, 26744 write accesses @131131435 -system.cpu3: completed 50000 read, 26919 write accesses @131315326 -system.cpu6: completed 50000 read, 27071 write accesses @131463045 -system.cpu2: completed 50000 read, 26691 write accesses @132748289 -system.cpu1: completed 50000 read, 27351 write accesses @133533726 -system.cpu0: completed 60000 read, 32524 write accesses @157291050 -system.cpu5: completed 60000 read, 32351 write accesses @157331674 -system.cpu3: completed 60000 read, 32133 write accesses @157609229 -system.cpu4: completed 60000 read, 32278 write accesses @158092666 -system.cpu7: completed 60000 read, 32237 write accesses @158094050 -system.cpu6: completed 60000 read, 32492 write accesses @158284016 -system.cpu2: completed 60000 read, 32099 write accesses @159310066 -system.cpu1: completed 60000 read, 32786 write accesses @160315811 -system.cpu5: completed 70000 read, 37785 write accesses @184174146 -system.cpu0: completed 70000 read, 37907 write accesses @184194427 -system.cpu3: completed 70000 read, 37695 write accesses @184756116 -system.cpu7: completed 70000 read, 37537 write accesses @185107500 -system.cpu6: completed 70000 read, 37865 write accesses @185115722 -system.cpu4: completed 70000 read, 37642 write accesses @185437602 -system.cpu2: completed 70000 read, 37459 write accesses @186101472 -system.cpu1: completed 70000 read, 38271 write accesses @187053767 -system.cpu0: completed 80000 read, 43182 write accesses @210453706 -system.cpu7: completed 80000 read, 43001 write accesses @210994557 -system.cpu5: completed 80000 read, 43199 write accesses @211075215 -system.cpu3: completed 80000 read, 43061 write accesses @211165517 -system.cpu4: completed 80000 read, 43118 write accesses @211798954 -system.cpu6: completed 80000 read, 43219 write accesses @211876903 -system.cpu2: completed 80000 read, 43025 write accesses @212410812 -system.cpu1: completed 80000 read, 43805 write accesses @214554639 -system.cpu0: completed 90000 read, 48653 write accesses @236986702 -system.cpu5: completed 90000 read, 48401 write accesses @237258796 -system.cpu7: completed 90000 read, 48251 write accesses @237456793 -system.cpu4: completed 90000 read, 48341 write accesses @237741580 -system.cpu3: completed 90000 read, 48504 write accesses @237892702 -system.cpu6: completed 90000 read, 48675 write accesses @238620248 -system.cpu2: completed 90000 read, 48457 write accesses @239205755 -system.cpu1: completed 90000 read, 49067 write accesses @239913307 -system.cpu5: completed 100000 read, 53710 write accesses @263488655 +system.cpu4: completed 10000 read, 5380 write accesses @22344646 +system.cpu6: completed 10000 read, 5214 write accesses @22747629 +system.cpu7: completed 10000 read, 5415 write accesses @22929508 +system.cpu2: completed 10000 read, 5407 write accesses @23019836 +system.cpu5: completed 10000 read, 5331 write accesses @23061044 +system.cpu0: completed 10000 read, 5432 write accesses @23140146 +system.cpu3: completed 10000 read, 5376 write accesses @23188049 +system.cpu1: completed 10000 read, 5387 write accesses @23350185 +system.cpu4: completed 20000 read, 10814 write accesses @44761691 +system.cpu7: completed 20000 read, 10827 write accesses @45213444 +system.cpu1: completed 20000 read, 10711 write accesses @45275122 +system.cpu6: completed 20000 read, 10548 write accesses @45324102 +system.cpu3: completed 20000 read, 10701 write accesses @45506880 +system.cpu2: completed 20000 read, 10922 write accesses @45734056 +system.cpu5: completed 20000 read, 10686 write accesses @45942373 +system.cpu0: completed 20000 read, 10937 write accesses @46044746 +system.cpu7: completed 30000 read, 16167 write accesses @66979485 +system.cpu4: completed 30000 read, 16361 write accesses @67223162 +system.cpu6: completed 30000 read, 15931 write accesses @67873351 +system.cpu3: completed 30000 read, 16353 write accesses @68348826 +system.cpu5: completed 30000 read, 16080 write accesses @68377482 +system.cpu1: completed 30000 read, 16196 write accesses @68419268 +system.cpu0: completed 30000 read, 16219 write accesses @68619325 +system.cpu2: completed 30000 read, 16526 write accesses @68648506 +system.cpu4: completed 40000 read, 21581 write accesses @88592659 +system.cpu7: completed 40000 read, 21651 write accesses @88863809 +system.cpu6: completed 40000 read, 21187 write accesses @89230569 +system.cpu1: completed 40000 read, 21556 write accesses @89813083 +system.cpu2: completed 40000 read, 21771 write accesses @90046604 +system.cpu3: completed 40000 read, 21725 write accesses @90210729 +system.cpu5: completed 40000 read, 21435 write accesses @90283858 +system.cpu0: completed 40000 read, 21836 write accesses @90947960 +system.cpu4: completed 50000 read, 27034 write accesses @111338978 +system.cpu6: completed 50000 read, 26346 write accesses @111492478 +system.cpu1: completed 50000 read, 26820 write accesses @112199634 +system.cpu7: completed 50000 read, 27390 write accesses @112358430 +system.cpu5: completed 50000 read, 26711 write accesses @112747804 +system.cpu3: completed 50000 read, 27030 write accesses @113062631 +system.cpu2: completed 50000 read, 27246 write accesses @113387493 +system.cpu0: completed 50000 read, 27088 write accesses @113621350 +system.cpu4: completed 60000 read, 32322 write accesses @134108306 +system.cpu6: completed 60000 read, 31811 write accesses @134700049 +system.cpu2: completed 60000 read, 32452 write accesses @135470855 +system.cpu1: completed 60000 read, 32239 write accesses @135474213 +system.cpu7: completed 60000 read, 32783 write accesses @135487924 +system.cpu5: completed 60000 read, 32297 write accesses @135551091 +system.cpu3: completed 60000 read, 32475 write accesses @135953364 +system.cpu0: completed 60000 read, 32594 write accesses @136506452 +system.cpu4: completed 70000 read, 37624 write accesses @156509147 +system.cpu6: completed 70000 read, 37191 write accesses @157507230 +system.cpu2: completed 70000 read, 37791 write accesses @158024045 +system.cpu7: completed 70000 read, 38252 write accesses @158415918 +system.cpu1: completed 70000 read, 37644 write accesses @158423190 +system.cpu5: completed 70000 read, 37691 write accesses @158678523 +system.cpu3: completed 70000 read, 38021 write accesses @158813067 +system.cpu0: completed 70000 read, 37965 write accesses @159679646 +system.cpu4: completed 80000 read, 42948 write accesses @178855235 +system.cpu6: completed 80000 read, 42510 write accesses @180069540 +system.cpu2: completed 80000 read, 43201 write accesses @180702038 +system.cpu1: completed 80000 read, 43267 write accesses @181114200 +system.cpu7: completed 80000 read, 43705 write accesses @181378010 +system.cpu3: completed 80000 read, 43552 write accesses @181443642 +system.cpu5: completed 80000 read, 43080 write accesses @181574154 +system.cpu0: completed 80000 read, 43418 write accesses @182451715 +system.cpu4: completed 90000 read, 48279 write accesses @201435873 +system.cpu6: completed 90000 read, 47918 write accesses @202390012 +system.cpu2: completed 90000 read, 48513 write accesses @203087400 +system.cpu1: completed 90000 read, 48611 write accesses @203141768 +system.cpu7: completed 90000 read, 48973 write accesses @204050544 +system.cpu5: completed 90000 read, 48423 write accesses @204299514 +system.cpu0: completed 90000 read, 48663 write accesses @204396348 +system.cpu3: completed 90000 read, 48999 write accesses @204475748 +system.cpu4: completed 100000 read, 53697 write accesses @224044586 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 4cc5a9b4f..2045d5848 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:15:53 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:54 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 263488655 because maximum number of loads reached +Exiting @ tick 224044586 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9aa493322..9c1b7f7cc 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,378 +1,378 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263488655 # Number of ticks simulated -final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000224 # Number of seconds simulated +sim_ticks 224044586 # Number of ticks simulated +final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1558675 # Simulator tick rate (ticks/s) -host_mem_usage 343952 # Number of bytes of host memory used -host_seconds 169.05 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 504730 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 513456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 503221 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 509883 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 511138 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 501110 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 514161 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 499881 # Number of bytes read from this memory -system.physmem.bytes_read::total 4057580 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 2601216 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5426 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5406 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5419 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5298 # Number of bytes written to this memory -system.physmem.bytes_written::total 2644316 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 17740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 17646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 17743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 17727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 17848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 17774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 17658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 17742 # Number of read requests responded to by this memory -system.physmem.num_reads::total 141878 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 40644 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5325 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5406 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5472 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5419 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 1915566346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 1948683521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 1909839344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 1935123165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 1939886178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 1901827614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 1951359158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 1897163276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15399448602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9872212525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 20463879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 20592917 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 20209599 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 20517012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 20767498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 20350022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 20566350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 20107128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10035786930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9872212525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 1936030225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 1969276438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 1930048943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 1955640177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 1960653676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 1922177636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 1971925509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 1917270404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 25435235532 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 76856 # number of replacements -system.l2c.tagsinuse 657.714518 # Cycle average of tags in use -system.l2c.total_refs 139150 # Total number of references to valid blocks. -system.l2c.sampled_refs 77525 # Sample count of references to valid blocks. -system.l2c.avg_refs 1.794905 # Average number of references to valid blocks. +host_tick_rate 1786168 # Simulator tick rate (ticks/s) +host_mem_usage 347548 # Number of bytes of host memory used +host_seconds 125.43 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory +system.physmem.bytes_read::total 700372 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory +system.physmem.bytes_written::total 498192 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 14607 # number of replacements +system.l2c.tagsinuse 798.832185 # Cycle average of tags in use +system.l2c.total_refs 150557 # Total number of references to valid blocks. +system.l2c.sampled_refs 15432 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.756156 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 468.019905 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 24.077198 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 23.899612 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 23.566419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 24.461210 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 24.025606 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 23.167376 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 23.494200 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 23.002994 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.457051 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.023513 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.023339 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.023014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.023888 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.023463 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.022624 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.022944 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.022464 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.642299 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10466 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10370 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10579 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10469 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10384 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10463 # number of ReadReq hits -system.l2c.ReadReq_hits::total 83711 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 94038 # number of Writeback hits -system.l2c.Writeback_hits::total 94038 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 457 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 419 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 446 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 463 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 463 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 411 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3504 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2829 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2819 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2765 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2929 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2882 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2913 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 22865 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 13295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 13189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 13480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 13234 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 13217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13313 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13376 # number of demand (read+write) hits -system.l2c.demand_hits::total 106576 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 13295 # number of overall hits -system.l2c.overall_hits::cpu1 13189 # number of overall hits -system.l2c.overall_hits::cpu2 13480 # number of overall hits -system.l2c.overall_hits::cpu3 13234 # number of overall hits -system.l2c.overall_hits::cpu4 13217 # number of overall hits -system.l2c.overall_hits::cpu5 13313 # number of overall hits -system.l2c.overall_hits::cpu6 13472 # number of overall hits -system.l2c.overall_hits::cpu7 13376 # number of overall hits -system.l2c.overall_hits::total 106576 # number of overall hits -system.l2c.ReadReq_misses::cpu0 5163 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 5186 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 5173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 5223 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 5193 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 5114 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 5145 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 4996 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41193 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1644 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1617 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1586 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1626 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1624 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 15498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 15735 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 15459 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 124904 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 94038 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 94038 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2101 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2017 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2063 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2073 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2016 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2089 # 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number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 23997 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 24183 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 24119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 23995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 24009 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 23934 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 24417 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 24015 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 192669 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 23997 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 24183 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 24119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 23995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 24009 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 23934 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 24417 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 24015 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 192669 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.330347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.333376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.328403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.332845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.333248 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.329797 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.776652 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.786224 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.666988 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.662584 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.448468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.449498 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.446844 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.448468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.449498 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.446844 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49616.116600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49615.022334 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49859.635067 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49817.112873 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49741.440015 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49720.418420 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49741.440015 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49720.418420 # average overall miss latency +system.l2c.occ_blocks::writebacks 740.812109 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.661361 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.247095 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.177515 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 6.855610 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.321397 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.120032 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 7.753138 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 6.883928 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.723449 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007482 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007077 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007150 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.006953 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.007571 # 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number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6224 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50082 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17846 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17933 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17750 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17813 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17960 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17904 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17849 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142751 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17846 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17933 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17750 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17813 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17960 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17904 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17849 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142751 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.072699 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.072316 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.070298 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.068463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068434 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.067586 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.071691 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063312 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.069344 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.852876 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.843146 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.842244 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851820 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.857572 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.849801 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.852689 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.844037 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849302 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.689363 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.695849 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.691667 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.684914 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.684639 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.690921 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.681094 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.695373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.689210 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.292951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.290461 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286511 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.289239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285297 # 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miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 49580.374101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 49435.068510 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 49618.515815 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 49482.515385 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49607.316993 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49963.417504 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 49887.468630 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 49885.922957 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 49900.924290 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 49870.753214 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 49939.188902 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 49945.125049 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 49929.225991 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 49902.884281 # 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number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -381,260 +381,257 @@ system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 40644 # number of writebacks -system.l2c.writebacks::total 40644 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 118 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 121 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 142 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 119 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 123 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 114 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 110 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 114 # 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number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 63563227 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 64483276 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 64122909 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 63203179 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 64843827 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 64763487 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 63043487 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 513507057 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 218853383 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 229413457 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 215692606 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 219654421 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 221773547 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 217413717 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 229694076 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 223253131 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1775748338 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 420667865 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 432027701 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 416947090 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 423827669 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 424547164 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 417425240 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 431027478 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 418505547 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3384975754 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 420667865 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 432027701 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 416947090 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 423827669 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 424547164 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 417425240 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 431027478 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 418505547 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3384975754 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400422345 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 391061487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 401502890 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 396621827 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400743471 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 404102628 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 391101960 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 403583386 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3189139994 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 215688086 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 217048117 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 213007261 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 216128145 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 218848364 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214487951 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 216767566 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 211927994 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1723903484 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 616110431 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 608109604 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 614510151 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 612749972 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 619591835 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 618590579 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 607869526 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 615511380 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4913043478 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.322797 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.325598 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.319388 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.325261 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.322103 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.773275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783235 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.661327 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.655102 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.439225 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.439225 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40002.595611 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40001.814722 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40002.626298 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency +system.l2c.writebacks::writebacks 7115 # number of writebacks +system.l2c.writebacks::total 7115 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 9 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 28 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 29 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 28 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 244 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 812 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 809 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 800 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 756 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 777 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 779 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 819 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 719 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6271 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1913 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1872 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2011 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1998 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1916 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1887 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1932 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15450 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4381 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4300 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4303 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4339 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4277 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4283 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4316 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34428 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5193 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5109 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5103 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5054 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5062 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5048 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5035 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40699 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5193 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5109 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5103 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5054 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5062 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5048 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5035 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40699 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 32483716 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 32363556 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 32004501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 30243000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 31083178 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 31162243 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 32763319 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 28723011 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 250826524 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76520708 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 74880632 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76840756 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80440711 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79880909 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76600687 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75440727 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77280682 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 617885812 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 175203645 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 171923291 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 172082750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 173484044 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 171083248 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 171323717 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 169163499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 172603062 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1376867256 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 207687361 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 204286847 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 204087251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 203727044 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 202166426 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 202485960 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 201926818 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 201326073 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1627693780 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 207687361 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 204286847 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 204087251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 203727044 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 202166426 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 202485960 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 201926818 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 201326073 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1627693780 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 393605068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397164440 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396084825 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 395564887 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 396845191 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 392884701 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 399924937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 397605829 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3169679878 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 212842079 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215082041 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 209602015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 213002165 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213521784 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214681989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217761849 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216562185 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1713056107 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 606447147 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 612246481 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 605686840 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 608567052 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 610366975 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 607566690 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 617686786 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 614168014 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4882735985 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070317 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068417 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066357 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067308 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066309 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.070066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061849 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.067671 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852876 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841348 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841805 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851397 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.857143 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.848914 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.852689 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844037 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.848808 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.687324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.694557 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.689583 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.682555 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.682246 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689472 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680451 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.693445 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687433 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285105 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285105 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -663,114 +660,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99815 # number of read accesses completed -system.cpu0.num_writes 53929 # number of write accesses completed +system.cpu0.num_reads 98637 # number of read accesses completed +system.cpu0.num_writes 53345 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 27826 # number of replacements -system.cpu0.l1c.tagsinuse 347.331950 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11604 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 28187 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.411679 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22018 # number of replacements +system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 347.331950 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.678383 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.678383 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 7530 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 7530 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1059 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1059 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 8589 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 8589 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 8589 # number of overall hits -system.cpu0.l1c.overall_hits::total 8589 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 37279 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 37279 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23202 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23202 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60481 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60481 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60481 # number of overall misses -system.cpu0.l1c.overall_misses::total 60481 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1299667421 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1299667421 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1001508092 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1001508092 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2301175513 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2301175513 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2301175513 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2301175513 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44809 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44809 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24261 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69070 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69070 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.831953 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956350 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.875648 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.875648 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.710521 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.774825 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8580 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1119 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9699 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9699 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9699 # number of overall hits +system.cpu0.l1c.overall_hits::total 9699 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35932 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35932 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23215 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23215 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59147 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59147 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59147 # number of overall misses +system.cpu0.l1c.overall_misses::total 59147 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 928213854 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 928213854 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 888665457 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 888665457 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1816879311 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1816879311 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1816879311 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1816879311 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44512 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44512 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24334 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24334 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68846 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68846 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68846 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68846 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807243 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807243 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954015 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954015 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859120 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859120 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859120 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859120 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 213519076 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3673.059398 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3177.792800 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 11972 # number of writebacks -system.cpu0.l1c.writebacks::total 11972 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 37279 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 37279 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23202 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23202 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60481 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60481 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60481 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60481 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262244251 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262244251 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 978215253 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 978215253 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2240459504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2240459504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2240459504 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2240459504 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 894578632 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 894578632 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 569723237 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.831953 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956350 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.875648 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.875648 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks +system.cpu0.l1c.writebacks::total 9668 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35932 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23215 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23215 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59147 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59147 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59147 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59147 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 892144080 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 892144080 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 865359572 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 865359572 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1757503652 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1757503652 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1757503652 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 897451639 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 561857596 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 561857596 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1459309235 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1459309235 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807243 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807243 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954015 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954015 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859120 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859120 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -778,114 +775,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98493 # number of read accesses completed -system.cpu1.num_writes 53671 # number of write accesses completed +system.cpu1.num_reads 99346 # number of read accesses completed +system.cpu1.num_writes 53405 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 27684 # number of replacements -system.cpu1.l1c.tagsinuse 345.656340 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11419 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 28039 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.407254 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21836 # number of replacements +system.cpu1.l1c.tagsinuse 395.252412 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13010 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22258 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.584509 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 345.656340 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.675110 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.675110 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 7429 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 7429 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1066 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 8495 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 8495 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 8495 # number of overall hits -system.cpu1.l1c.overall_hits::total 8495 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 37110 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 37110 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23275 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23275 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60385 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60385 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60385 # number of overall misses -system.cpu1.l1c.overall_misses::total 60385 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1301760811 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1301760811 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1014297005 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1014297005 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2316057816 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2316057816 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2316057816 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2316057816 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44539 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44539 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24341 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24341 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68880 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68880 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.833202 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.956206 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.876670 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.876670 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 395.252412 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.771977 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.771977 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8468 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8468 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9513 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9513 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9513 # number of overall hits +system.cpu1.l1c.overall_hits::total 9513 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36170 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36170 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22843 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22843 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59013 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59013 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59013 # number of overall misses +system.cpu1.l1c.overall_misses::total 59013 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 930956991 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 930956991 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 873445374 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 873445374 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1804402365 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1804402365 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1804402365 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1804402365 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44638 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44638 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23888 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23888 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68526 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68526 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68526 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68526 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.810296 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.810296 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956254 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956254 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861177 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861177 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861177 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861177 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 212850460 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 67062 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3680.878237 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3173.935463 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 11809 # number of writebacks -system.cpu1.l1c.writebacks::total 11809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 37110 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 37110 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23275 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23275 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60385 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60385 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60385 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60385 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1264508347 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1264508347 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 990933889 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 990933889 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2255442236 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2255442236 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2255442236 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2255442236 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 877119159 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 877119159 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 578327433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.833202 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956206 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.876670 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.876670 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9414 # number of writebacks +system.cpu1.l1c.writebacks::total 9414 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36170 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22843 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22843 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59013 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59013 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59013 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59013 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 894646237 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 894646237 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 850514976 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 850514976 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1745161213 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1745161213 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1745161213 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1745161213 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 906808922 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 906808922 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 573615954 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 573615954 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480424876 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480424876 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.810296 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.810296 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956254 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956254 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861177 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861177 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -893,114 +890,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99149 # number of read accesses completed -system.cpu2.num_writes 53185 # number of write accesses completed +system.cpu2.num_reads 99179 # number of read accesses completed +system.cpu2.num_writes 53408 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 27627 # number of replacements -system.cpu2.l1c.tagsinuse 345.430231 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11519 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 27982 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.411657 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21970 # number of replacements +system.cpu2.l1c.tagsinuse 396.422513 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13458 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22394 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.600965 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 345.430231 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.674668 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.674668 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 7576 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 7576 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1069 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1069 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 8645 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 8645 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 8645 # number of overall hits -system.cpu2.l1c.overall_hits::total 8645 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 37144 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 37144 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22885 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22885 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60029 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60029 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60029 # number of overall misses -system.cpu2.l1c.overall_misses::total 60029 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1302790562 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1302790562 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 991654869 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 991654869 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2294445431 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2294445431 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2294445431 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2294445431 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44720 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44720 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23954 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23954 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68674 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68674 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.830590 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955373 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.874115 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.874115 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 396.422513 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.774263 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.774263 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8875 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8875 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1083 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9958 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9958 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9958 # number of overall hits +system.cpu2.l1c.overall_hits::total 9958 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35921 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35921 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23014 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23014 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58935 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58935 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58935 # number of overall misses +system.cpu2.l1c.overall_misses::total 58935 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 936514854 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 936514854 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 882688372 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 882688372 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1819203226 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1819203226 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1819203226 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1819203226 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44796 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44796 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24097 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24097 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68893 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68893 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68893 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68893 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.801880 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.801880 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955057 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955057 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855457 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855457 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855457 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855457 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 215347558 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 67274 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3701.759105 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3201.051788 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 11784 # number of writebacks -system.cpu2.l1c.writebacks::total 11784 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 37144 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 37144 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22885 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22885 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60029 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60029 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60029 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60029 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1265501937 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1265501937 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 968684322 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 968684322 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2234186259 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2234186259 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2234186259 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2234186259 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 900513056 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 900513056 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 566349170 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.830590 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955373 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.874115 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.874115 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9572 # number of writebacks +system.cpu2.l1c.writebacks::total 9572 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35921 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35921 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23014 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23014 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58935 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58935 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 900454097 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 900454097 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 859588304 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 859588304 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1760042401 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1760042401 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1760042401 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1760042401 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 903394412 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 903394412 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 551786925 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 551786925 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1455181337 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1455181337 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.801880 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.801880 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955057 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955057 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855457 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855457 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1008,114 +1005,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99588 # number of read accesses completed -system.cpu3.num_writes 53645 # number of write accesses completed +system.cpu3.num_reads 98310 # number of read accesses completed +system.cpu3.num_writes 53451 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 27837 # number of replacements -system.cpu3.l1c.tagsinuse 347.574885 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11563 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 28190 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.410181 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21775 # number of replacements +system.cpu3.l1c.tagsinuse 395.971374 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13179 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22179 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.594211 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 347.574885 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.678857 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.678857 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 7552 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 7552 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1078 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 8630 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 8630 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 8630 # number of overall hits -system.cpu3.l1c.overall_hits::total 8630 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 37191 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 37191 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23219 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23219 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60410 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60410 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60410 # number of overall misses -system.cpu3.l1c.overall_misses::total 60410 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1312024933 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1312024933 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 995527685 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 995527685 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2307552618 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2307552618 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2307552618 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2307552618 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44743 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44743 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24297 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24297 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69040 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69040 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.831214 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955632 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.875000 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.875000 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.971374 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.773382 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.773382 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8374 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8374 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1100 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1100 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9474 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9474 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9474 # number of overall hits +system.cpu3.l1c.overall_hits::total 9474 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35667 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35667 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23305 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23305 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58972 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58972 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58972 # number of overall misses +system.cpu3.l1c.overall_misses::total 58972 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 919630073 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 919630073 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 893117472 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 893117472 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1812747545 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1812747545 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1812747545 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1812747545 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44041 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44041 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24405 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24405 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68446 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68446 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68446 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68446 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809859 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.809859 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954927 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954927 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861584 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861584 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861584 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861584 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 213693223 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67039 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3691.127910 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3187.595623 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 11956 # number of writebacks -system.cpu3.l1c.writebacks::total 11956 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 37191 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 37191 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23219 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23219 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60410 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60410 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60410 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60410 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1274692143 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1274692143 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 972218785 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 972218785 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2246910928 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2246910928 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2246910928 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2246910928 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 889431937 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 889431937 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 569772276 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.831214 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955632 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.875000 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.875000 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9546 # number of writebacks +system.cpu3.l1c.writebacks::total 9546 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35667 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35667 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23305 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23305 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58972 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58972 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58972 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58972 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 883822339 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 883822339 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869724232 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869724232 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1753546571 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1753546571 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1753546571 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1753546571 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 901886993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 901886993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 561139437 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 561139437 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1463026430 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1463026430 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809859 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809859 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954927 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954927 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861584 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861584 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1123,114 +1120,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99725 # number of read accesses completed -system.cpu4.num_writes 53533 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 53697 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 27683 # number of replacements -system.cpu4.l1c.tagsinuse 347.631602 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11724 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 28041 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.418102 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22069 # number of replacements +system.cpu4.l1c.tagsinuse 396.565187 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13244 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 347.631602 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.678968 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.678968 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 7686 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 7686 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1123 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1123 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 8809 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 8809 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 8809 # number of overall hits -system.cpu4.l1c.overall_hits::total 8809 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 37251 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 37251 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22937 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22937 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60188 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60188 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60188 # number of overall misses -system.cpu4.l1c.overall_misses::total 60188 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1303112178 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1303112178 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 994450363 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 994450363 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2297562541 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2297562541 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2297562541 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2297562541 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44937 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44937 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24060 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68997 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68997 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.828961 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953325 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.872328 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.872328 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 396.565187 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.774541 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.774541 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8614 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8614 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1053 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1053 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9667 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9667 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9667 # number of overall hits +system.cpu4.l1c.overall_hits::total 9667 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36078 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36078 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23045 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23045 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59123 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59123 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59123 # number of overall misses +system.cpu4.l1c.overall_misses::total 59123 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 933502205 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 933502205 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 883607398 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 883607398 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1817109603 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1817109603 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1817109603 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1817109603 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44692 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24098 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24098 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68790 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68790 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68790 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68790 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807259 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807259 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956303 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956303 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859471 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859471 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859471 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859471 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 213249503 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67264 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3690.197653 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3170.336331 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 11763 # number of writebacks -system.cpu4.l1c.writebacks::total 11763 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 37251 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 37251 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22937 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22937 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60188 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60188 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60188 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60188 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1265717116 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1265717116 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 971425596 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 971425596 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2237142712 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2237142712 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2237142712 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2237142712 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 898461911 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 898461911 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 576408625 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.828961 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953325 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.872328 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.872328 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9627 # number of writebacks +system.cpu4.l1c.writebacks::total 9627 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36078 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36078 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23045 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23045 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59123 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59123 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59123 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59123 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 897285830 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 897285830 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 860474190 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 860474190 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1757760020 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1757760020 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1757760020 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1757760020 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 897898466 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 897898466 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 564390024 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 564390024 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1462288490 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1462288490 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807259 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807259 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956303 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956303 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859471 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859471 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1238,114 +1235,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53710 # number of write accesses completed +system.cpu5.num_reads 98755 # number of read accesses completed +system.cpu5.num_writes 53000 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 27832 # number of replacements -system.cpu5.l1c.tagsinuse 346.806811 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11748 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 28191 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.416729 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21964 # number of replacements +system.cpu5.l1c.tagsinuse 395.335157 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13162 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22364 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.588535 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 346.806811 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.677357 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.677357 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 7592 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 7592 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1126 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1126 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 8718 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 8718 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 8718 # number of overall hits -system.cpu5.l1c.overall_hits::total 8718 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 37349 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 37349 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23013 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23013 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60362 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60362 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60362 # number of overall misses -system.cpu5.l1c.overall_misses::total 60362 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1291933371 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1291933371 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 998304045 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 998304045 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2290237416 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2290237416 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2290237416 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2290237416 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44941 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24139 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24139 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69080 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69080 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.831067 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953353 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.873798 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.873798 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 395.335157 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.772139 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.772139 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8580 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8580 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1063 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1063 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9643 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9643 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9643 # number of overall hits +system.cpu5.l1c.overall_hits::total 9643 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36060 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36060 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22989 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22989 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59049 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59049 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59049 # number of overall misses +system.cpu5.l1c.overall_misses::total 59049 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 944228607 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 944228607 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 875107262 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 875107262 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1819335869 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1819335869 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1819335869 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1819335869 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44640 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44640 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24052 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24052 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68692 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68692 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68692 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68692 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807796 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807796 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955804 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.955804 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859620 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859620 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 213071792 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 67023 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3673.840624 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3179.084672 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 11908 # number of writebacks -system.cpu5.l1c.writebacks::total 11908 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 37349 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 37349 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23013 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23013 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60362 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60362 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60362 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60362 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1254436910 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1254436910 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 975203983 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 975203983 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2229640893 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2229640893 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2229640893 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2229640893 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 902856034 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 902856034 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567587171 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.831067 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953353 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.873798 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.873798 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9605 # number of writebacks +system.cpu5.l1c.writebacks::total 9605 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36060 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36060 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22989 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22989 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59049 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59049 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59049 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59049 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 908030320 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 908030320 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 852027269 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 852027269 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1760057589 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1760057589 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1760057589 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1760057589 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 893562759 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 893562759 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567489251 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567489251 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1461052010 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1461052010 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955804 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1353,114 +1350,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99389 # number of read accesses completed -system.cpu6.num_writes 53686 # number of write accesses completed +system.cpu6.num_reads 99515 # number of read accesses completed +system.cpu6.num_writes 53091 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 27861 # number of replacements -system.cpu6.l1c.tagsinuse 347.289326 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11520 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 28198 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.408540 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21875 # number of replacements +system.cpu6.l1c.tagsinuse 395.073790 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13163 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22301 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 347.289326 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.678299 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.678299 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 7543 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 7543 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1119 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 8662 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 8662 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 8662 # number of overall hits -system.cpu6.l1c.overall_hits::total 8662 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 37109 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 37109 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23142 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23142 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60251 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60251 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60251 # number of overall misses -system.cpu6.l1c.overall_misses::total 60251 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1299799162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1299799162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1015775810 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1015775810 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2315574972 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2315574972 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2315574972 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2315574972 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24261 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68913 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68913 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.831071 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953877 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.874305 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.874305 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 395.073790 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.771628 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.771628 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8660 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1070 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1070 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9730 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9730 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9730 # number of overall hits +system.cpu6.l1c.overall_hits::total 9730 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36079 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36079 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22730 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22730 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58809 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58809 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58809 # number of overall misses +system.cpu6.l1c.overall_misses::total 58809 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 942403765 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 942403765 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 866225957 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 866225957 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1808629722 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1808629722 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1808629722 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1808629722 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44739 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44739 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23800 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23800 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68539 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68539 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68539 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68539 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806433 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806433 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955042 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955042 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858037 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858037 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858037 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858037 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 212806358 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66914 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3698.984332 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3180.296470 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 11849 # number of writebacks -system.cpu6.l1c.writebacks::total 11849 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 37109 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 37109 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23142 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23142 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60251 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60251 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60251 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60251 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262548698 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262548698 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 992541214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 992541214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2255089912 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2255089912 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2255089912 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2255089912 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 877981455 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 877981455 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 574689009 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.831071 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953877 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.874305 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.874305 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9438 # number of writebacks +system.cpu6.l1c.writebacks::total 9438 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36079 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36079 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22730 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22730 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58809 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58809 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58809 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58809 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 906189412 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 906189412 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 843405989 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 843405989 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1749595401 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1749595401 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1749595401 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1749595401 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 905213986 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 905213986 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 576398345 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 576398345 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1481612331 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1481612331 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806433 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955042 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955042 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858037 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858037 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1468,114 +1465,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99694 # number of read accesses completed -system.cpu7.num_writes 53501 # number of write accesses completed +system.cpu7.num_reads 98608 # number of read accesses completed +system.cpu7.num_writes 53688 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 27727 # number of replacements -system.cpu7.l1c.tagsinuse 346.094259 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11534 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 28062 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.411018 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 21767 # number of replacements +system.cpu7.l1c.tagsinuse 394.473547 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13199 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 346.094259 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.675965 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.675965 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 7593 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 7593 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1111 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1111 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 8704 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 8704 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 8704 # number of overall hits -system.cpu7.l1c.overall_hits::total 8704 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 37155 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 37155 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23121 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23121 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60276 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60276 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60276 # number of overall misses -system.cpu7.l1c.overall_misses::total 60276 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1287127315 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1287127315 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1006139538 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1006139538 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2293266853 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2293266853 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2293266853 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2293266853 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44748 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44748 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24232 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24232 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68980 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68980 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.830316 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954152 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.873818 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.873818 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 394.473547 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.770456 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.770456 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8649 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8649 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 995 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 995 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9644 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9644 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9644 # number of overall hits +system.cpu7.l1c.overall_hits::total 9644 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35884 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35884 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23099 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23099 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58983 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58983 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58983 # number of overall misses +system.cpu7.l1c.overall_misses::total 58983 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 932010776 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 932010776 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 877703149 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 877703149 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1809713925 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1809713925 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1809713925 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1809713925 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44533 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44533 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24094 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24094 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68627 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68627 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68627 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68627 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805784 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805784 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.958703 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.958703 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859472 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859472 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859472 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859472 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 213241981 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3679.369981 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 11797 # number of writebacks -system.cpu7.l1c.writebacks::total 11797 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 37155 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 37155 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23121 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23121 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60276 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60276 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60276 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60276 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1249829653 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1249829653 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 982928032 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 982928032 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2232757685 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2232757685 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2232757685 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2232757685 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 901961636 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 901961636 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 558194703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.830316 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954152 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.873818 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.873818 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9457 # number of writebacks +system.cpu7.l1c.writebacks::total 9457 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35884 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23099 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58983 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58983 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 895990178 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 854514720 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1750504898 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |