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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-15 15:27:35 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2017-11-21 14:25:56 +0000
commit4d893c215ef82358c62bfbb44dc4fef57c524df0 (patch)
tree5666e520b295a8f17e79146745d1900b14f0c72a
parent2a2c66c16c659af4c3588b6c1646d55c66ad53fe (diff)
downloadgem5-4d893c215ef82358c62bfbb44dc4fef57c524df0.tar.xz
arch-arm: Fix MCR/MRC disassemble
This patch is fixing the Aarch32 MCR/MRC disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the coprocessor register name Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5862 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
-rw-r--r--src/arch/arm/insts/misc.cc6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f63..ec1b9358c 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
- printIntReg(ss, dest);
+ printMiscReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
- ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -273,8 +272,7 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printMnemonic(ss);
printIntReg(ss, dest);
ss << ", ";
- printIntReg(ss, op1);
- ccprintf(ss, ", #%d", imm);
+ printMiscReg(ss, op1);
return ss.str();
}