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| author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-07-23 18:51:16 +0800 |
|---|---|---|
| committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-07-30 09:20:54 +0000 |
| commit | 5bb6210b10bf4a7a678dc41e6f7c9493842247b9 (patch) | |
| tree | 37bc39c9002ddee2dfe9c95ef7e189a0039a709f | |
| parent | a3ac8caba9dba103d61d4b75b1ea3f8061cfabf4 (diff) | |
| download | gem5-5bb6210b10bf4a7a678dc41e6f7c9493842247b9.tar.xz | |
system-arm: Initialize ICC_SRE_EL3 register
Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.
Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | system/arm/aarch64_bootloader/boot.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S index 589f38a4b..5e5e39439 100644 --- a/system/arm/aarch64_bootloader/boot.S +++ b/system/arm/aarch64_bootloader/boot.S @@ -90,6 +90,11 @@ _start: str w0, [x1], #4 str w0, [x1], #4 + /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */ + mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 + orr x10, x10, #0xf // enable 0xf + msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3 + isb 2: mov x0, #1 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable |