moved ev5_trap fully into the fault class.

--HG--
extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db

4 files changed, 30 insertions, 51 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 2bb005eb4..ac0e7e67e 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -164,38 +164,6 @@ AlphaISA::zeroRegisters(CPU *cpu)
 }
 
 void
-ExecContext::ev5_temp_trap(Fault fault)
-{
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", fault->name()));
-
-    assert(!misspeculating());
-    kernelStats->fault(fault);
-
-    if (fault->isA<ArithmeticFault>())
-        panic("Arithmetic traps are unimplemented!");
-
-    // exception restart address
-    if (!fault->isA<InterruptFault>() || !inPalMode())
-        setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
-
-    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
-        fault == InterruptFault && !inPalMode() */) {
-        // traps...  skip faulting instruction.
-        setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
-    }
-
-    if (!inPalMode())
-        AlphaISA::swap_palshadow(&regs, true);
-
-    regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
-        (dynamic_cast<AlphaFault *>(fault.get()))->vect();
-    regs.npc = regs.pc + sizeof(MachInst);
-}
-
-
-void
 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
     bool use_pc = (fault == NoFault);
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index 78613761d..8c7dc3194 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -28,6 +28,9 @@
 
 #include "arch/alpha/faults.hh"
 #include "cpu/exec_context.hh"
+#include "cpu/base.hh"
+#include "base/trace.hh"
+#include "kern/kernel_stats.hh"
 
 namespace AlphaISA
 {
@@ -98,17 +101,30 @@ FaultStat IntegerOverflowFault::_stat;
 
 void AlphaFault::ev5_trap(ExecContext * xc)
 {
-    xc->ev5_temp_trap(this);
-}
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
+    xc->cpu->recordEvent(csprintf("Fault %s", name()));
 
-void AlphaMachineCheckFault::ev5_trap(ExecContext * xc)
-{
-    xc->ev5_temp_trap(this);
-}
+    assert(!xc->misspeculating());
+    xc->kernelStats->fault(this);
 
-void AlphaAlignmentFault::ev5_trap(ExecContext * xc)
-{
-    xc->ev5_temp_trap(this);
+    if (isA<ArithmeticFault>())
+        panic("Arithmetic traps are unimplemented!");
+
+    // exception restart address
+    if (!isA<InterruptFault>() || !xc->inPalMode())
+        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
+
+    if (isA<PalFault>() || isA<ArithmeticFault>()) {
+        // traps...  skip faulting instruction.
+        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+    }
+
+    if (!xc->inPalMode())
+        AlphaISA::swap_palshadow(&(xc->regs), true);
+
+    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
+    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
 }
 
 #endif
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 156faa8fb..829edd490 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -55,9 +55,6 @@ class AlphaMachineCheckFault :
     static FaultVect _vect;
     static FaultStat _stat;
   public:
-#if FULL_SYSTEM
-    void ev5_trap(ExecContext * xc);
-#endif
     FaultVect vect() {return _vect;}
     FaultStat & stat() {return _stat;}
 };
@@ -70,9 +67,6 @@ class AlphaAlignmentFault :
     static FaultVect _vect;
     static FaultStat _stat;
   public:
-#if FULL_SYSTEM
-    void ev5_trap(ExecContext * xc);
-#endif
     FaultVect vect() {return _vect;}
     FaultStat & stat() {return _stat;}
 };
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index daa61bb1c..a1c659b51 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -302,7 +302,7 @@ template <class Impl>
 void
 AlphaFullCPU<Impl>::trap(Fault fault)
 {
-    // Keep in mind that a trap may be initiated by fetch if there's a TLB
+/*    // Keep in mind that a trap may be initiated by fetch if there's a TLB
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
@@ -318,8 +318,9 @@ AlphaFullCPU<Impl>::trap(Fault fault)
     if (!fault->isA<InterruptFault>() || !inPalMode(PC))
         this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
 
-    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
-        fault == InterruptFault && !PC_PAL(regs.pc) */) {
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
+    //    || fault == InterruptFault && !PC_PAL(regs.pc)
+        {
         // traps...  skip faulting instruction
         AlphaISA::MiscReg ipr_exc_addr =
             this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
@@ -332,7 +333,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
 
     this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
                          (dynamic_cast<AlphaFault *>(fault.get()))->vect());
-    this->regFile.setNextPC(PC + sizeof(MachInst));
+    this->regFile.setNextPC(PC + sizeof(MachInst));*/
 }
 
 template <class Impl>