ARM: Rework how unrecognized/unimplemented instructions are handled.

Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.

6 files changed, 99 insertions, 22 deletions

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 2f939ea8c..9e32a23a3 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -142,6 +142,24 @@ ArmFaultBase::invoke(ThreadContext *tc)
     tc->setPC(newPc);
     tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
 }
+
+#else
+
+void
+UndefinedInstruction::invoke(ThreadContext *tc)
+{
+    assert(unknown || mnemonic != NULL);
+    if (unknown) {
+        panic("Attempted to execute unknown instruction "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)",
+              machInst, machInst.opcode, inst2string(machInst));
+    } else {
+        panic("Attempted to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)",
+              mnemonic, machInst, machInst.opcode, inst2string(machInst));
+    }
+}
+
 #endif // FULL_SYSTEM
 
 // return via SUBS pc, lr, xxx; rfe, movs, ldm
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 7f8aa66b6..90a730507 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
@@ -92,7 +104,27 @@ class ArmFault : public ArmFaultBase
 
 
 class Reset                : public ArmFault<Reset> {};
-class UndefinedInstruction : public ArmFault<UndefinedInstruction> {};
+
+class UndefinedInstruction : public ArmFault<UndefinedInstruction>
+{
+#if !FULL_SYSTEM
+  protected:
+    ExtMachInst machInst;
+    bool unknown;
+    const char *mnemonic;
+
+  public:
+    UndefinedInstruction(ExtMachInst _machInst,
+                         bool _unknown,
+                         const char *_mnemonic = NULL) :
+        machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic)
+    {
+    }
+
+    void invoke(ThreadContext *tc);
+#endif
+};
+
 class SupervisorCall       : public ArmFault<SupervisorCall> {};
 class PrefetchAbort        : public ArmFault<PrefetchAbort> {};
 class DataAbort            : public ArmFault<DataAbort> {};
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 35dbe6d52..485d6997e 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -67,20 +67,6 @@ class ArmStaticInst : public StaticInst
     {
     }
 
-    inline static std::string
-    inst2string(MachInst machInst)
-    {
-        std::string str = "";
-        uint32_t mask = (1 << 31);
-
-        while (mask) {
-            str += ((machInst & mask) ? "1" : "0");
-            mask = mask >> 1;
-        }
-
-        return str;
-    }
-
     /// Print a register name for disassembly given the unique
     /// dependence tag number (FP or int).
     void printReg(std::ostream &os, int reg) const;
diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa
index e7bf67f68..a746f8a7b 100644
--- a/src/arch/arm/isa/formats/unimp.isa
+++ b/src/arch/arm/isa/formats/unimp.isa
@@ -1,5 +1,17 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
 // Copyright (c) 2007-2008 The Florida State University
 // All rights reserved.
 //
@@ -112,10 +124,11 @@ output exec {{
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        panic("attempt to execute unimplemented instruction '%s' "
-              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
-              inst2string(machInst));
-        return new UnimpFault("Unimplemented Instruction");
+#if FULL_SYSTEM
+        return new UndefinedInstruction;
+#else
+        return new UndefinedInstruction(machInst, false, mnemonic);
+#endif
     }
 
     Fault
diff --git a/src/arch/arm/isa/formats/unknown.isa b/src/arch/arm/isa/formats/unknown.isa
index 97a0caa6b..e4bb94899 100644
--- a/src/arch/arm/isa/formats/unknown.isa
+++ b/src/arch/arm/isa/formats/unknown.isa
@@ -1,5 +1,17 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
 // Copyright (c) 2007-2008 The Florida State University
 // All rights reserved.
 //
@@ -72,9 +84,11 @@ output exec {{
     Unknown::execute(%(CPU_exec_context)s *xc,
                      Trace::InstRecord *traceData) const
     {
-        panic("attempt to execute unknown instruction "
-              "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
-        return new UnimpFault("Unimplemented Instruction");
+#if FULL_SYSTEM
+        return new UndefinedInstruction;
+#else
+        return new UndefinedInstruction(machInst, true);
+#endif
     }
 }};
 
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 5739ba3cd..b2c678c46 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -146,6 +146,20 @@ namespace ArmISA {
         return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
     }
 
+    static inline std::string
+    inst2string(MachInst machInst)
+    {
+        std::string str = "";
+        uint32_t mask = (1 << 31);
+
+        while (mask) {
+            str += ((machInst & mask) ? "1" : "0");
+            mask = mask >> 1;
+        }
+
+        return str;
+    }
+
 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
     
 Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);