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authorGabe Black <gabeblack@google.com>2014-11-21 17:22:02 -0800
committerGabe Black <gabeblack@google.com>2014-11-21 17:22:02 -0800
commit8bbfb1b39d06f33423f3a0acc661559fd0e3d038 (patch)
tree36840b4ef77b3304efa5bbec0ae5fd841b12c20b
parent708e80d9bb0577662dd7181d4ae947c2cc9b8ac9 (diff)
downloadgem5-8bbfb1b39d06f33423f3a0acc661559fd0e3d038.tar.xz
x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.
There was already a stub device at 0x80, the port traditionally used for an IO delay. 0x80 is also the port used for POST codes sent by firmware, and that may have prompted adding this port as a second option.
-rw-r--r--src/dev/x86/Pc.py8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 1f1f3ca89..8740159c4 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -49,8 +49,9 @@ class Pc(Platform):
south_bridge = SouthBridge()
- # "Non-existant" port used for timing purposes by the linux kernel
- i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+ # "Non-existant" ports used for timing purposes by the linux kernel
+ i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+ i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
@@ -71,7 +72,8 @@ class Pc(Platform):
def attachIO(self, bus, dma_ports = []):
self.south_bridge.attachIO(bus, dma_ports)
- self.i_dont_exist.pio = bus.master
+ self.i_dont_exist1.pio = bus.master
+ self.i_dont_exist2.pio = bus.master
self.behind_pci.pio = bus.master
self.com_1.pio = bus.master
self.fake_com_2.pio = bus.master