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| author | Adrien Pesle <adrien.pesle@arm.com> | 2018-10-11 16:09:07 +0200 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-17 14:47:14 +0000 |
| commit | 9181c2ea16d384c57e6bb4e757ecaf1b52b8e7f1 (patch) | |
| tree | f4830bde400dddc39dd57be7dc0450c95e929ef7 | |
| parent | 0f368d5ebdd4eeff9f475aed244677a4191df5d8 (diff) | |
| download | gem5-9181c2ea16d384c57e6bb4e757ecaf1b52b8e7f1.tar.xz | |
dev-arm: Fix Gicv2 distributor group register
For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.
Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/dev/arm/gic_v2.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index c9c1a4715..4afad89f6 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -336,7 +336,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters bool isGroup0(ContextID ctx, uint32_t int_num) { const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num)); - return bits(group_reg, intNumToBit(int_num)); + return !bits(group_reg, intNumToBit(int_num)); } /** |