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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:47:25 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:47:25 -0400
commita8e3001df85bc1e435a8abe77141ba0f6c9b7f9e (patch)
tree6b74fae6fb0b7ebd79e24289bdea69e035ae4b69
parentb3e55339f90dbf7f719e8f8348356e1ad03d74bb (diff)
downloadgem5-a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e.tar.xz
X86: Bypass unaligned access support for register addressed MSRs.
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/general_io.py14
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/string_io.py14
-rw-r--r--src/arch/x86/isa/insts/system/msrs.py8
-rw-r--r--src/arch/x86/tlb.cc3
4 files changed, 17 insertions, 22 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index 1986a322e..aba318d73 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -84,25 +84,23 @@
microcode = '''
def macroop IN_R_I {
.adjust_imm trimImm(8)
- limm t1, "IntAddrPrefixIO", dataSize=8
- ld reg, intseg, [1, t1, t0], imm, addressSize=8
+ limm t1, imm, dataSize=asz
+ ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
};
def macroop IN_R_R {
- limm t1, "IntAddrPrefixIO", dataSize=8
zexti t2, regm, 15, dataSize=2
- ld reg, intseg, [1, t1, t2], addressSize=8
+ ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
};
def macroop OUT_I_R {
.adjust_imm trimImm(8)
- limm t1, "IntAddrPrefixIO", dataSize=8
- st reg, intseg, [1, t1, t0], imm, addressSize=8
+ limm t1, imm, dataSize=8
+ st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
};
def macroop OUT_R_R {
- limm t1, "IntAddrPrefixIO", dataSize=8
zexti t2, reg, 15, dataSize=2
- st regm, intseg, [1, t1, t2], addressSize=8
+ st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
};
'''
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
index b44203d9c..1b4e086d2 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2007 The Hewlett-Packard Development Company
+# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
@@ -61,10 +61,9 @@ def macroop INS_M_R {
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- limm t1, "IntAddrPrefixIO"
zexti t2, reg, 15, dataSize=2
- ld t6, intseg, [1, t1, t2], addressSize=8
+ ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
st t6, es, [1, t0, rdi]
add rdi, rdi, t3, dataSize=asz
@@ -77,11 +76,10 @@ def macroop INS_E_M_R {
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- limm t1, "IntAddrPrefixIO"
zexti t2, reg, 15, dataSize=2
topOfLoop:
- ld t6, intseg, [1, t1, t2], addressSize=8
+ ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
st t6, es, [1, t0, rdi]
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
@@ -97,11 +95,10 @@ def macroop OUTS_R_M {
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- limm t1, "IntAddrPrefixIO"
zexti t2, reg, 15, dataSize=2
ld t6, ds, [1, t0, rsi]
- st t6, intseg, [1, t1, t2], addressSize=8
+ st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
add rsi, rsi, t3, dataSize=asz
};
@@ -113,12 +110,11 @@ def macroop OUTS_E_R_M {
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- limm t1, "IntAddrPrefixIO"
zexti t2, reg, 15, dataSize=2
topOfLoop:
ld t6, ds, [1, t0, rsi]
- st t6, intseg, [1, t1, t2], addressSize=8
+ st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
add rsi, rsi, t3, dataSize=asz
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index 461ed1054..f3c867398 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -84,8 +84,8 @@
microcode = '''
def macroop RDMSR
{
- limm t1, "IntAddrPrefixMSR >> 3"
- ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+ ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
+ dataSize=8, addressSize=4
mov rax, rax, t2, dataSize=4
srli t2, t2, 32, dataSize=8
mov rdx, rdx, t2, dataSize=4
@@ -93,11 +93,11 @@ def macroop RDMSR
def macroop WRMSR
{
- limm t1, "IntAddrPrefixMSR >> 3"
mov t2, t2, rax, dataSize=4
slli t3, rdx, 32, dataSize=8
or t2, t2, t3, dataSize=8
- st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+ st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
+ dataSize=8, addressSize=4
};
def macroop RDTSC
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index cbd59c19e..b6793245e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -206,10 +206,11 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
// value.
if (seg == SEGMENT_REG_MS) {
DPRINTF(TLB, "Addresses references internal memory.\n");
- Addr prefix = vaddr & IntAddrPrefixMask;
+ Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
if (prefix == IntAddrPrefixCPUID) {
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
+ vaddr = vaddr >> 3;
req->setMmapedIpr(true);
Addr regNum = 0;
switch (vaddr & ~IntAddrPrefixMask) {