diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
87 files changed, 16495 insertions, 17386 deletions
diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc index 033ccbb26..0deaedcf9 100644 --- a/src/mem/simple_dram.cc +++ b/src/mem/simple_dram.cc @@ -520,8 +520,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) writeBursts++; // see if we can merge with an existing item in the write - // queue and keep track of whether we have merged or not, as - // there is only ever one item to merge with + // queue and keep track of whether we have merged or not so we + // can stop at that point and also avoid enqueueing a new + // request bool merged = false; auto w = writeQueue.begin(); @@ -529,6 +530,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) // either of the two could be first, if they are the same // it does not matter which way we go if ((*w)->addr >= addr) { + // the existing one starts after the new one, figure + // out where the new one ends with respect to the + // existing one if ((addr + size) >= ((*w)->addr + (*w)->size)) { // check if the existing one is completely // subsumed in the new one @@ -550,6 +554,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) (*w)->size = (*w)->addr + (*w)->size - addr; } } else { + // the new one starts after the current one, figure + // out where the existing one ends with respect to the + // new one if (((*w)->addr + (*w)->size) >= (addr + size)) { // check if the new one is completely subsumed in the // existing one diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 353384b9f..0cce0ce1e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904274 # Number of seconds simulated -sim_ticks 1904273734500 # Number of ticks simulated -final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.902739 # Number of seconds simulated +sim_ticks 1902738973500 # Number of ticks simulated +final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95291 # Simulator instruction rate (inst/s) -host_op_rate 95291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3200085877 # Simulator tick rate (ticks/s) -host_mem_usage 314408 # Number of bytes of host memory used -host_seconds 595.07 # Real time elapsed on the host -sim_insts 56704659 # Number of instructions simulated -sim_ops 56704659 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory +host_inst_rate 97410 # Simulator instruction rate (inst/s) +host_op_rate 97410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3267297836 # Simulator tick rate (ticks/s) +host_mem_usage 312988 # Number of bytes of host memory used +host_seconds 582.36 # Real time elapsed on the host +sim_insts 56727331 # Number of instructions simulated +sim_ops 56727331 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory -system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory -system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory +system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory +system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451213 # Total number of read requests seen -system.physmem.writeReqs 122920 # Total number of write requests seen -system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28877632 # Total number of bytes read from memory -system.physmem.bytesWritten 7866880 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 28869696 # Total number of bytes read from memory +system.physmem.bytesWritten 7821440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1904269209000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 1902738952500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451213 # Categorize read packet sizes +system.physmem.readPktSize::6 451089 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122920 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122210 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -138,398 +139,396 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation -system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests -system.physmem.totBusLat 2255690000 # Total cycles spent in databus access -system.physmem.totBankLat 5207950000 # Total cycles spent in bank access -system.physmem.avgQLat 14167.07 # Average queueing delay per request -system.physmem.avgBankLat 11544.03 # Average bank access latency per request +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation +system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests +system.physmem.totBusLat 2255080000 # Total cycles spent in databus access +system.physmem.totBankLat 5209710000 # Total cycles spent in bank access +system.physmem.avgQLat 14198.08 # Average queueing delay per request +system.physmem.avgBankLat 11551.05 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30711.10 # Average memory access latency -system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30749.13 # Average memory access latency +system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.33 # Average write queue length over time -system.physmem.readRowHits 435283 # Number of row buffer hits during reads -system.physmem.writeRowHits 98148 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes -system.physmem.avgGap 3316773.66 # Average gap between requests -system.membus.throughput 19353836 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296513 # Transaction distribution -system.membus.trans_dist::ReadResp 296436 # Transaction distribution -system.membus.trans_dist::WriteReq 13046 # Transaction distribution -system.membus.trans_dist::WriteResp 13046 # Transaction distribution -system.membus.trans_dist::Writeback 122920 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9558 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5502 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4874 # Transaction distribution -system.membus.trans_dist::ReadExReq 162935 # Transaction distribution -system.membus.trans_dist::ReadExResp 162546 # Transaction distribution -system.membus.trans_dist::BadAddressError 77 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921574 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 962210 # Packet count per connected master and slave (bytes) +system.physmem.avgWrQLen 14.36 # Average write queue length over time +system.physmem.readRowHits 435126 # Number of row buffer hits during reads +system.physmem.writeRowHits 97620 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes +system.physmem.avgGap 3318929.48 # Average gap between requests +system.membus.throughput 19341454 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296468 # Transaction distribution +system.membus.trans_dist::ReadResp 296394 # Transaction distribution +system.membus.trans_dist::WriteReq 13061 # Transaction distribution +system.membus.trans_dist::WriteResp 13061 # Transaction distribution +system.membus.trans_dist::Writeback 122210 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution +system.membus.trans_dist::ReadExReq 162867 # Transaction distribution +system.membus.trans_dist::ReadExResp 162463 # Transaction distribution +system.membus.trans_dist::BadAddressError 74 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 40482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1046240 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086876 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31436416 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31510170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36744512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36818266 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36818266 # Total data (bytes) +system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36765002 # Total data (bytes) system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1615737499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3831920118 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 344278 # number of replacements -system.l2c.tags.tagsinuse 65254.004539 # Cycle average of tags in use -system.l2c.tags.total_refs 2578331 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409473 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.296706 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53538.058266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5369.862130 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6148.232371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 134.758747 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 63.093024 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093815 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995697 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 876771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 739535 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 198332 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 63825 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1878463 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 821103 # number of Writeback hits -system.l2c.Writeback_hits::total 821103 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 177 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 433 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 156398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 23000 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179398 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 876771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 895933 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 198332 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 86825 # number of demand (read+write) hits -system.l2c.demand_hits::total 2057861 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 876771 # number of overall hits -system.l2c.overall_hits::cpu0.data 895933 # number of overall hits -system.l2c.overall_hits::cpu1.inst 198332 # number of overall hits -system.l2c.overall_hits::cpu1.data 86825 # number of overall hits -system.l2c.overall_hits::total 2057861 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14688 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273591 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 576 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 306 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289161 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2677 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1042 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3719 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 416 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 865 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 116243 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5041 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121284 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14688 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389834 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 576 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5347 # number of demand (read+write) misses -system.l2c.demand_misses::total 410445 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14688 # number of overall misses -system.l2c.overall_misses::cpu0.data 389834 # number of overall misses -system.l2c.overall_misses::cpu1.inst 576 # number of overall misses -system.l2c.overall_misses::cpu1.data 5347 # number of overall misses -system.l2c.overall_misses::total 410445 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1267720492 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17201796982 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 49661500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 29444499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18548623473 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1381450 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4584270 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5965720 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 930960 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 99997 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1030957 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9514647474 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 547564734 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10062212208 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1267720492 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26716444456 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 49661500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 577009233 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28610835681 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1267720492 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26716444456 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 49661500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 577009233 # 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average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -667,15 +666,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.488928 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.488928 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030558 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030558 # Average percentage of cache occupancy +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -684,14 +683,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21574383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21574383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10460928278 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10460928278 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10482502661 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10482502661 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10482502661 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10482502661 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -708,19 +707,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123282.188571 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123282.188571 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251755.108731 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251755.108731 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251216.302658 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251216.302658 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272971 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -734,14 +733,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -750,14 +749,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -771,35 +770,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12622908 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits +system.cpu0.branchPred.lookups 12458299 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9003860 # DTB read hits -system.cpu0.dtb.read_misses 33263 # DTB read misses -system.cpu0.dtb.read_acv 538 # DTB read access violations -system.cpu0.dtb.read_accesses 672573 # DTB read accesses -system.cpu0.dtb.write_hits 5893133 # DTB write hits -system.cpu0.dtb.write_misses 8284 # DTB write misses -system.cpu0.dtb.write_acv 368 # DTB write access violations -system.cpu0.dtb.write_accesses 235576 # DTB write accesses -system.cpu0.dtb.data_hits 14896993 # DTB hits -system.cpu0.dtb.data_misses 41547 # DTB misses -system.cpu0.dtb.data_acv 906 # DTB access violations -system.cpu0.dtb.data_accesses 908149 # DTB accesses -system.cpu0.itb.fetch_hits 1042149 # ITB hits -system.cpu0.itb.fetch_misses 31540 # ITB misses -system.cpu0.itb.fetch_acv 1064 # ITB acv -system.cpu0.itb.fetch_accesses 1073689 # ITB accesses +system.cpu0.dtb.read_hits 8872852 # DTB read hits +system.cpu0.dtb.read_misses 32010 # DTB read misses +system.cpu0.dtb.read_acv 540 # DTB read access violations +system.cpu0.dtb.read_accesses 628428 # DTB read accesses +system.cpu0.dtb.write_hits 5797852 # DTB write hits +system.cpu0.dtb.write_misses 8130 # DTB write misses +system.cpu0.dtb.write_acv 348 # DTB write access violations +system.cpu0.dtb.write_accesses 210128 # DTB write accesses +system.cpu0.dtb.data_hits 14670704 # DTB hits +system.cpu0.dtb.data_misses 40140 # DTB misses +system.cpu0.dtb.data_acv 888 # DTB access violations +system.cpu0.dtb.data_accesses 838556 # DTB accesses +system.cpu0.itb.fetch_hits 994919 # ITB hits +system.cpu0.itb.fetch_misses 28800 # ITB misses +system.cpu0.itb.fetch_acv 922 # ITB acv +system.cpu0.itb.fetch_accesses 1023719 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -812,269 +811,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115698572 # number of cpu cycles simulated +system.cpu0.numCycles 114636003 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71847381 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 384293 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued -system.cpu0.iq.rate 0.450361 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued +system.cpu0.iq.rate 0.448487 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3259244 # number of nop insts executed -system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8231181 # Number of branches executed -system.cpu0.iew.exec_stores 5915227 # Number of stores executed -system.cpu0.iew.exec_rate 0.446898 # Inst execution rate -system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25550537 # num instructions producing a value -system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value +system.cpu0.iew.exec_nop 3225661 # number of nop insts executed +system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8123465 # Number of branches executed +system.cpu0.iew.exec_stores 5819599 # Number of stores executed +system.cpu0.iew.exec_rate 0.445079 # Inst execution rate +system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25247170 # num instructions producing a value +system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51778647 # Number of instructions committed -system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51137491 # Number of instructions committed +system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13979102 # Number of memory references committed -system.cpu0.commit.loads 8265509 # Number of loads committed -system.cpu0.commit.membars 200777 # Number of memory barriers committed -system.cpu0.commit.branches 7822311 # Number of branches committed -system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666551 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13773046 # Number of memory references committed +system.cpu0.commit.loads 8150974 # Number of loads committed +system.cpu0.commit.membars 198820 # Number of memory barriers committed +system.cpu0.commit.branches 7724848 # Number of branches committed +system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions. +system.cpu0.commit.function_calls 655486 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 132380203 # The number of ROB reads -system.cpu0.rob.rob_writes 117743806 # The number of ROB writes -system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48811521 # Number of Instructions Simulated -system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated -system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads -system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads -system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes +system.cpu0.rob.rob_reads 130752703 # The number of ROB reads +system.cpu0.rob.rob_writes 116166541 # The number of ROB writes +system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48197169 # Number of Instructions Simulated +system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated +system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads +system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads +system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads +system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1106,49 +1105,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111303171 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210591002 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks) +system.toL2Bus.throughput 111571177 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210876874 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1436442 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 54598 # Transaction distribution -system.iobus.trans_dist::WriteResp 54598 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1437659 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54613 # Transaction distribution +system.iobus.trans_dist::WriteResp 54613 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1159,25 +1158,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1188,27 +1174,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735378 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735490 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1228,253 +1201,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 890887 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits -system.cpu0.icache.overall_hits::total 6905559 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 937559 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 937559 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 937559 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 937559 # number of overall misses -system.cpu0.icache.overall_misses::total 937559 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13556216106 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13556216106 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13556216106 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13556216106 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13556216106 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13556216106 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7843118 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7843118 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7843118 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7843118 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7843118 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7843118 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119539 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119539 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119539 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14459.053890 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14459.053890 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14459.053890 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14459.053890 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6417 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 876399 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits +system.cpu0.icache.overall_hits::total 6802362 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses +system.cpu0.icache.overall_misses::total 921891 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.168182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45998 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45998 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45998 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45998 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45998 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45998 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 891561 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 891561 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 891561 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 891561 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 891561 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 891561 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11118457121 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11118457121 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11118457121 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11118457121 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11118457121 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11118457121 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113674 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113674 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113674 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.775551 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44872 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44872 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44872 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44872 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44872 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44872 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 877019 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 877019 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 877019 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 877019 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1288020 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.688069 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10644807 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1288532 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.261189 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.688069 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987672 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6550900 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6550900 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3728429 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3728429 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165070 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 165070 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189835 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189835 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10279329 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10279329 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10279329 # number of overall hits -system.cpu0.dcache.overall_hits::total 10279329 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1597921 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1597921 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1777729 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1777729 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20672 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20672 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2669 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2669 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3375650 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3375650 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3375650 # number of overall misses -system.cpu0.dcache.overall_misses::total 3375650 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40268021859 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40268021859 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79880065793 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 79880065793 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301767496 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 301767496 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20162915 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20162915 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 120148087652 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 120148087652 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 120148087652 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 120148087652 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8148821 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8148821 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5506158 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5506158 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185742 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 185742 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13654979 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13654979 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13654979 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13654979 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196092 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.196092 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322862 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322862 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111294 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111294 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247210 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247210 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247210 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247210 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25200.258247 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25200.258247 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44933.769879 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44933.769879 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14597.885836 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14597.885836 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7554.482952 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7554.482952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35592.578511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35592.578511 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2948269 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 1278910 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3667453 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162740 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162740 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187465 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187465 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10108289 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits +system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses +system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks -system.cpu0.dcache.writebacks::total 760237 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks +system.cpu0.dcache.writebacks::total 752999 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1482,35 +1455,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2340238 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits +system.cpu1.branchPred.lookups 2517085 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1733483 # DTB read hits -system.cpu1.dtb.read_misses 9288 # DTB read misses -system.cpu1.dtb.read_acv 9 # DTB read access violations -system.cpu1.dtb.read_accesses 276268 # DTB read accesses -system.cpu1.dtb.write_hits 1103623 # DTB write hits -system.cpu1.dtb.write_misses 1818 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 104203 # DTB write accesses -system.cpu1.dtb.data_hits 2837106 # DTB hits -system.cpu1.dtb.data_misses 11106 # DTB misses -system.cpu1.dtb.data_acv 47 # DTB access violations -system.cpu1.dtb.data_accesses 380471 # DTB accesses -system.cpu1.itb.fetch_hits 375000 # ITB hits -system.cpu1.itb.fetch_misses 5508 # ITB misses -system.cpu1.itb.fetch_acv 148 # ITB acv -system.cpu1.itb.fetch_accesses 380508 # ITB accesses +system.cpu1.dtb.read_hits 1869470 # DTB read hits +system.cpu1.dtb.read_misses 10476 # DTB read misses +system.cpu1.dtb.read_acv 22 # DTB read access violations +system.cpu1.dtb.read_accesses 321268 # DTB read accesses +system.cpu1.dtb.write_hits 1203365 # DTB write hits +system.cpu1.dtb.write_misses 2061 # DTB write misses +system.cpu1.dtb.write_acv 64 # DTB write access violations +system.cpu1.dtb.write_accesses 130567 # DTB write accesses +system.cpu1.dtb.data_hits 3072835 # DTB hits +system.cpu1.dtb.data_misses 12537 # DTB misses +system.cpu1.dtb.data_acv 86 # DTB access violations +system.cpu1.dtb.data_accesses 451835 # DTB accesses +system.cpu1.itb.fetch_hits 424254 # ITB hits +system.cpu1.itb.fetch_misses 6539 # ITB misses +system.cpu1.itb.fetch_acv 190 # ITB acv +system.cpu1.itb.fetch_accesses 430793 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1523,508 +1496,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14113255 # number of cpu cycles simulated +system.cpu1.numCycles 15249987 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12790175 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 140614 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1736625 12.99% 84.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued -system.cpu1.iq.rate 0.603567 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued +system.cpu1.iq.rate 0.605480 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 454104 # number of nop insts executed -system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1252098 # Number of branches executed -system.cpu1.iew.exec_stores 1111067 # Number of stores executed -system.cpu1.iew.exec_rate 0.598269 # Inst execution rate -system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3943473 # num instructions producing a value -system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value +system.cpu1.iew.exec_nop 488162 # number of nop insts executed +system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1362461 # Number of branches executed +system.cpu1.iew.exec_stores 1211286 # Number of stores executed +system.cpu1.iew.exec_rate 0.599873 # Inst execution rate +system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4254481 # num instructions producing a value +system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8297892 # Number of instructions committed -system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8962351 # Number of instructions committed +system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2639087 # Number of memory references committed -system.cpu1.commit.loads 1580128 # Number of loads committed -system.cpu1.commit.membars 40354 # Number of memory barriers committed -system.cpu1.commit.branches 1179945 # Number of branches committed -system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions. -system.cpu1.commit.function_calls 130349 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2852844 # Number of memory references committed +system.cpu1.commit.loads 1698881 # Number of loads committed +system.cpu1.commit.membars 42409 # Number of memory barriers committed +system.cpu1.commit.branches 1280511 # Number of branches committed +system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions. +system.cpu1.commit.function_calls 141484 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22380631 # The number of ROB reads -system.cpu1.rob.rob_writes 19363835 # The number of ROB writes -system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7893138 # Number of Instructions Simulated -system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated -system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads -system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes -system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes -system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads -system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes -system.cpu1.icache.tags.replacements 198364 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits -system.cpu1.icache.overall_hits::total 1103940 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses -system.cpu1.icache.overall_misses::total 205398 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2726676790 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1309338 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1309338 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1309338 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1309338 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1309338 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1309338 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.156872 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.156872 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.156872 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.156872 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.156872 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.156872 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13275.089290 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13275.089290 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13275.089290 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked +system.cpu1.rob.rob_reads 24092433 # The number of ROB reads +system.cpu1.rob.rob_writes 21005155 # The number of ROB writes +system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8530162 # Number of Instructions Simulated +system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated +system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads +system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads +system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes +system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads +system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes +system.cpu1.icache.tags.replacements 214995 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits +system.cpu1.icache.overall_hits::total 1210101 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses +system.cpu1.icache.overall_misses::total 223312 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.166667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6463 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6463 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6463 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6463 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6463 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6463 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 198935 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 198935 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 198935 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 198935 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 198935 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 198935 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2267895657 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2267895657 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2267895657 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2267895657 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2267895657 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2267895657 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151936 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.151936 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.151936 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11400.184266 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150387 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150387 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150387 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 93782 # number of replacements -system.cpu1.dcache.tags.tagsinuse 490.645175 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2322631 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 94098 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.683107 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.645175 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.958291 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1425624 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1425624 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 844173 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 844173 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 28774 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 28774 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27671 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 27671 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2269797 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2269797 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2269797 # number of overall hits -system.cpu1.dcache.overall_hits::total 2269797 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 184725 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 184725 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 178548 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 178548 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4789 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4789 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2902 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2902 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 363273 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 363273 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 363273 # number of overall misses -system.cpu1.dcache.overall_misses::total 363273 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2584165220 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2584165220 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5809552721 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5809552721 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46614997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46614997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21574947 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21574947 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8393717941 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8393717941 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8393717941 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8393717941 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1610349 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1610349 # 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miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114711 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174581 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.174581 # miss rate for WriteReq accesses +system.cpu1.dcache.tags.replacements 104218 # number of replacements +system.cpu1.dcache.tags.tagsinuse 490.671059 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2506866 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 104618 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.962091 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.671059 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958342 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.958342 # 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number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1737315 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1115243 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1115243 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36086 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 36086 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32829 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2852558 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2852558 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2852558 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188162 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.188162 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143742 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143742 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143742 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # 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number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks +system.cpu1.dcache.writebacks::total 69226 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2033,161 +2006,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904272882500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687097 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3568 2.09% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155408 90.82% 93.10% # number of callpals executed -system.cpu0.kern.callpal::rdps 6655 3.89% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed -system.cpu0.kern.callpal::rti 4603 2.69% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 171120 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed +system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 169239 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1286 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2100950500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3569 # number of times the context was actually changed +system.cpu0.kern.swap_context 3515 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed -system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed -system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed +system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed +system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed +system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46877 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 567 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 200 -system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48756 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches +system.cpu1.kern.mode_switch::user 459 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 668 +system.cpu1.kern.mode_good::user 459 +system.cpu1.kern.mode_good::idle 209 +system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1036 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1096 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 59daab93c..c5784a1fd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.860201 # Nu sim_ticks 1860200687500 # Number of ticks simulated final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112423 # Simulator instruction rate (inst/s) -host_op_rate 112423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3947369845 # Simulator tick rate (ticks/s) -host_mem_usage 310252 # Number of bytes of host memory used -host_seconds 471.25 # Real time elapsed on the host +host_inst_rate 95880 # Simulator instruction rate (inst/s) +host_op_rate 95880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3366492305 # Simulator tick rate (ticks/s) +host_mem_usage 308824 # Number of bytes of host memory used +host_seconds 552.56 # Real time elapsed on the host sim_insts 52979577 # Number of instructions simulated sim_ops 52979577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory @@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 518206 # To system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445243 # Total number of read requests seen -system.physmem.writeReqs 117437 # Total number of write requests seen -system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28495552 # Total number of bytes read from memory system.physmem.bytesWritten 7515968 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis @@ -336,17 +337,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_respo system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36055668 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) @@ -360,15 +356,15 @@ system.membus.respLayer1.occupancy 3765192546 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -819,19 +815,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) @@ -848,19 +831,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2705756 # Total data (bytes) system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) @@ -905,12 +875,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) @@ -921,15 +891,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009263 # number of replacements -system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1009263 # number of replacements +system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits @@ -1005,19 +975,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 338298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits @@ -1185,15 +1155,15 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401048 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1401048 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index feb99cd9c..ea150be87 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.842705 # Nu sim_ticks 1842705252000 # Number of ticks simulated final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221595 # Simulator instruction rate (inst/s) -host_op_rate 221595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5621199023 # Simulator tick rate (ticks/s) -host_mem_usage 308252 # Number of bytes of host memory used -host_seconds 327.81 # Real time elapsed on the host +host_inst_rate 308319 # Simulator instruction rate (inst/s) +host_op_rate 308319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7821132493 # Simulator tick rate (ticks/s) +host_mem_usage 307864 # Number of bytes of host memory used +host_seconds 235.61 # Real time elapsed on the host sim_insts 72641883 # Number of instructions simulated sim_ops 72641883 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory @@ -58,14 +58,15 @@ system.physmem.bw_total::cpu1.data 1242973 # To system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99238 # Total number of read requests seen -system.physmem.writeReqs 44800 # Total number of write requests seen -system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 6351232 # Total number of bytes read from memory system.physmem.bytesWritten 2867200 # Total number of bytes written to memory system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis @@ -298,17 +299,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 35966088 # Total data (bytes) system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) @@ -322,27 +318,27 @@ system.membus.respLayer1.occupancy 771793954 # La system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337384 # number of replacements -system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use -system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy +system.l2c.tags.replacements 337384 # number of replacements +system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use +system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits @@ -626,15 +622,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -780,10 +776,10 @@ system.cpu0.num_fp_register_writes 89168 # nu system.cpu0.num_mem_refs 8444409 # number of memory refs system.cpu0.num_load_insts 4931349 # Number of load instructions system.cpu0.num_store_insts 3513060 # Number of store instructions -system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles -system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles -system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles -system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles +system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles +system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles +system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed @@ -912,12 +908,12 @@ system.toL2Bus.trans_dist::UpgradeResp 17 # Tr system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 203464200 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) @@ -942,13 +938,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) @@ -959,13 +948,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) @@ -986,19 +968,19 @@ system.iobus.respLayer0.occupancy 9566000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950451 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 950451 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits @@ -1116,19 +1098,19 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391525 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 1391525 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.453270 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488664 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254587 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256745 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 4073389 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1086662 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 2399601 # number of ReadReq hits @@ -1412,10 +1394,10 @@ system.cpu1.num_fp_register_writes 24577 # nu system.cpu1.num_mem_refs 2116682 # number of memory refs system.cpu1.num_load_insts 1209934 # Number of load instructions system.cpu1.num_store_insts 906748 # Number of store instructions -system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles -system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles -system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles +system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles +system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 03035c465..4688e11b5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,131 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534332 # Number of seconds simulated -sim_ticks 2534332336000 # Number of ticks simulated -final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.524310 # Number of seconds simulated +sim_ticks 2524309551500 # Number of ticks simulated +final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47356 # Simulator instruction rate (inst/s) -host_op_rate 60934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1990051953 # Simulator tick rate (ticks/s) -host_mem_usage 400524 # Number of bytes of host memory used -host_seconds 1273.50 # Real time elapsed on the host -sim_insts 60307773 # Number of instructions simulated -sim_ops 77599321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 67450 # Simulator instruction rate (inst/s) +host_op_rate 86789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2823365435 # Simulator tick rate (ticks/s) +host_mem_usage 397608 # Number of bytes of host memory used +host_seconds 894.08 # Real time elapsed on the host +sim_insts 60305560 # Number of instructions simulated +sim_ops 77596391 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory -system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15101237 # Total number of read requests seen -system.physmem.writeReqs 813162 # Total number of write requests seen -system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966479168 # Total number of bytes read from memory -system.physmem.bytesWritten 52042368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 966197440 # Total number of bytes read from memory +system.physmem.bytesWritten 52040704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534332242000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2524308440000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14946576 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154625 # Categorize read packet sizes +system.physmem.readPktSize::6 154591 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59144 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -139,316 +140,294 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation -system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests -system.physmem.totBusLat 75504790000 # Total cycles spent in databus access -system.physmem.totBankLat 15713238750 # Total cycles spent in bank access -system.physmem.avgQLat 23320.54 # Average queueing delay per request -system.physmem.avgBankLat 1040.55 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation +system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests +system.physmem.totBusLat 75453215000 # Total cycles spent in databus access +system.physmem.totBankLat 15307050000 # Total cycles spent in bank access +system.physmem.avgQLat 19314.15 # Average queueing delay per request +system.physmem.avgBankLat 1014.34 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29361.08 # Average memory access latency -system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25328.49 # Average memory access latency +system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 10.77 # Average write queue length over time -system.physmem.readRowHits 15074158 # Number of row buffer hits during reads -system.physmem.writeRowHits 797610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes -system.physmem.avgGap 159247.75 # Average gap between requests +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 14.41 # Average write queue length over time +system.physmem.readRowHits 15065383 # Number of row buffer hits during reads +system.physmem.writeRowHits 94229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes +system.physmem.avgGap 158662.04 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -461,60 +440,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54715776 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16153842 # Transaction distribution -system.membus.trans_dist::ReadResp 16153842 # Transaction distribution -system.membus.trans_dist::WriteReq 763336 # Transaction distribution -system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149440 # Transaction distribution +system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.trans_dist::WriteReq 763332 # Transaction distribution +system.membus.trans_dist::WriteResp 763332 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution -system.membus.trans_dist::ReadExReq 131438 # Transaction distribution -system.membus.trans_dist::ReadExResp 131438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138667961 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138629141 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -522,15 +491,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48124265 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution -system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution -system.iobus.trans_dist::WriteReq 8158 # Transaction distribution -system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.throughput 48301509 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.trans_dist::WriteReq 8157 # Transaction distribution +system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -550,38 +519,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -601,42 +546,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121962881 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927961 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -676,26 +597,26 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14663186 # Number of BP lookups -system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits +system.cpu.branchPred.lookups 14390442 # Number of BP lookups +system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987443 # DTB read hits -system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227745 # DTB write hits +system.cpu.checker.dtb.read_hits 14986742 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11227334 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -706,13 +627,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994750 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229934 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215188 # DTB hits -system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26224684 # DTB accesses -system.cpu.checker.itb.inst_hits 61481774 # ITB inst hits +system.cpu.checker.dtb.hits 26214076 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26223573 # DTB accesses +system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -729,36 +650,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486245 # ITB inst accesses -system.cpu.checker.itb.hits 61481774 # DTB hits +system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses +system.cpu.checker.itb.hits 61479547 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486245 # DTB accesses -system.cpu.checker.numCycles 77885129 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484018 # DTB accesses +system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389107 # DTB read hits -system.cpu.dtb.read_misses 64168 # DTB read misses -system.cpu.dtb.write_hits 11699261 # DTB write hits -system.cpu.dtb.write_misses 15977 # DTB write misses +system.cpu.dtb.read_hits 51188083 # DTB read hits +system.cpu.dtb.read_misses 64353 # DTB read misses +system.cpu.dtb.write_hits 11697459 # DTB write hits +system.cpu.dtb.write_misses 15788 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6541 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51453275 # DTB read accesses -system.cpu.dtb.write_accesses 11715238 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252436 # DTB read accesses +system.cpu.dtb.write_accesses 11713247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63088368 # DTB hits -system.cpu.dtb.misses 80145 # DTB misses -system.cpu.dtb.accesses 63168513 # DTB accesses -system.cpu.itb.inst_hits 12244686 # ITB inst hits -system.cpu.itb.inst_misses 11272 # ITB inst misses +system.cpu.dtb.hits 62885542 # DTB hits +system.cpu.dtb.misses 80141 # DTB misses +system.cpu.dtb.accesses 62965683 # DTB accesses +system.cpu.itb.inst_hits 11520428 # ITB inst hits +system.cpu.itb.inst_misses 11439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -767,114 +688,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4958 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12255958 # ITB inst accesses -system.cpu.itb.hits 12244686 # DTB hits -system.cpu.itb.misses 11272 # DTB misses -system.cpu.itb.accesses 12255958 # DTB accesses -system.cpu.numCycles 475312551 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11531867 # ITB inst accesses +system.cpu.itb.hits 11520428 # DTB hits +system.cpu.itb.misses 11439 # DTB misses +system.cpu.itb.accesses 11531867 # DTB accesses +system.cpu.numCycles 473080437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -902,416 +823,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued -system.cpu.iq.rate 0.261503 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued +system.cpu.iq.rate 0.259812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222537 # number of nop insts executed -system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed -system.cpu.iew.exec_branches 11556571 # Number of branches executed -system.cpu.iew.exec_stores 12211191 # Number of stores executed -system.cpu.iew.exec_rate 0.255895 # Inst execution rate -system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268516 # num instructions producing a value -system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value +system.cpu.iew.exec_nop 221034 # number of nop insts executed +system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed +system.cpu.iew.exec_branches 11474602 # Number of branches executed +system.cpu.iew.exec_stores 12209197 # Number of stores executed +system.cpu.iew.exec_rate 0.255417 # Inst execution rate +system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47030253 # num instructions producing a value +system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back +system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458154 # Number of instructions committed -system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60455941 # Number of instructions committed +system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386643 # Number of memory references committed -system.cpu.commit.loads 15654562 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961356 # Number of branches committed +system.cpu.commit.refs 27385481 # Number of memory references committed +system.cpu.commit.loads 15653838 # Number of loads committed +system.cpu.commit.membars 403568 # Number of memory barriers committed +system.cpu.commit.branches 9961054 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. -system.cpu.commit.function_calls 991265 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. +system.cpu.commit.function_calls 991205 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243752783 # The number of ROB reads -system.cpu.rob.rob_writes 201807644 # The number of ROB writes -system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307773 # Number of Instructions Simulated -system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated -system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550637147 # number of integer regfile reads -system.cpu.int_regfile_writes 88566596 # number of integer regfile writes -system.cpu.fp_regfile_reads 8370 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads -system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 239241509 # The number of ROB reads +system.cpu.rob.rob_writes 195965670 # The number of ROB writes +system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305560 # Number of Instructions Simulated +system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated +system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547265504 # number of integer regfile reads +system.cpu.int_regfile_writes 87536110 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2916 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads +system.cpu.misc_regfile_writes 831835 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits -system.cpu.icache.overall_hits::total 11180201 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses -system.cpu.icache.overall_misses::total 1060929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked +system.cpu.icache.tags.replacements 979660 # number of replacements +system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits +system.cpu.icache.overall_hits::total 10456897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses +system.cpu.icache.overall_misses::total 1059959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64396 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51354.796312 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885755 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129794 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.528830 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2499257274500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36876.248148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.469348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8188.920307 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6258.158141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.562687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000480 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64363 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489241302000 # 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number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13548 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13548 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699423 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699423 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699423 # number of overall misses -system.cpu.dcache.overall_misses::total 3699423 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144767959567 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144767959567 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked +system.cpu.dcache.tags.replacements 643614 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits +system.cpu.dcache.overall_hits::total 21018772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700946 # 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number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks -system.cpu.dcache.writebacks::total 607541 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks +system.cpu.dcache.writebacks::total 607864 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1594,12 +1515,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1608,16 +1529,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5451e0c81..0edabf3c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,150 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.114023 # Number of seconds simulated -sim_ticks 1114022852000 # Number of ticks simulated -final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104038 # Number of seconds simulated +sim_ticks 1104038330000 # Number of ticks simulated +final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79652 # Simulator instruction rate (inst/s) -host_op_rate 102538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1440387686 # Simulator tick rate (ticks/s) -host_mem_usage 404604 # Number of bytes of host memory used -host_seconds 773.42 # Real time elapsed on the host -sim_insts 61604368 # Number of instructions simulated -sim_ops 79304455 # Number of ops (including micro ops) simulated +host_inst_rate 80920 # Simulator instruction rate (inst/s) +host_op_rate 104171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450259542 # Simulator tick rate (ticks/s) +host_mem_usage 402880 # Number of bytes of host memory used +host_seconds 761.27 # Real time elapsed on the host +sim_insts 61602211 # Number of instructions simulated +sim_ops 79302243 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory +system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823459 # Total number of write requests seen -system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52701376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis +system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 400511872 # Total number of bytes read from memory +system.physmem.bytesWritten 52704704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry -system.physmem.totGap 1114021721000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1104037196000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163045 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66623 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66675 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,366 +161,312 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27423 2 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30559 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30943 1 0.00% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31839 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32223 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32415 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33375 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 5 0.01% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 3 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 2 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 43 0.11% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34527 1 0.00% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 2 0.01% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35167 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36127 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36319 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36383 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37824-37855 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38175 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39263 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39455 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39519 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40863 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41503 2 0.01% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41695 1 0.00% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42271 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43039 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44127 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45599 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46367 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46879 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-47007 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49503 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 2 0.01% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51776-51807 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 2 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.01% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54815 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56095 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56351 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57280-57311 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57631 2 0.01% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57792-57823 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59968-59999 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60447 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61471 4 0.01% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62400-62431 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.01% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63744-63775 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64543 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130880-130911 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 2 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::133632-133663 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::165568-165599 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::175552-175583 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::189440-189471 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 6 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation -system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289130000 # Total cycles spent in databus access -system.physmem.totBankLat 8086320000 # Total cycles spent in bank access -system.physmem.avgQLat 29123.92 # Average queueing delay per request -system.physmem.avgBankLat 1292.19 # Average bank access latency per request +system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation +system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests +system.physmem.totBusLat 31269035000 # Total cycles spent in databus access +system.physmem.totBankLat 7640613750 # Total cycles spent in bank access +system.physmem.avgQLat 19443.72 # Average queueing delay per request +system.physmem.avgBankLat 1221.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35416.11 # Average memory access latency -system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25665.47 # Average memory access latency +system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 6237911 # Number of row buffer hits during reads -system.physmem.writeRowHits 804550 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157316.33 # Average gap between requests +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.74 # Average write queue length over time +system.physmem.readRowHits 6235456 # Number of row buffer hits during reads +system.physmem.writeRowHits 98940 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes +system.physmem.avgGap 155904.23 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -525,307 +476,309 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 61845817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306747 # Transaction distribution -system.membus.trans_dist::ReadResp 7306747 # Transaction distribution -system.membus.trans_dist::WriteReq 767893 # Transaction distribution -system.membus.trans_dist::WriteResp 767893 # Transaction distribution -system.membus.trans_dist::Writeback 66623 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution -system.membus.trans_dist::ReadExReq 138043 # Transaction distribution -system.membus.trans_dist::ReadExResp 137663 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 62410733 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306749 # Transaction distribution +system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.trans_dist::WriteReq 767894 # Transaction distribution +system.membus.trans_dist::WriteResp 767894 # Transaction distribution +system.membus.trans_dist::Writeback 66675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution +system.membus.trans_dist::ReadExReq 138085 # Transaction distribution +system.membus.trans_dist::ReadExResp 137703 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14160695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555723 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17723636 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20138869 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 66482420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68897653 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68897653 # Total data (bytes) +system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903841 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475761000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8620588249 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 9828000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 756000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4823074562 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13762899732 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72713 # number of replacements -system.l2c.tags.tagsinuse 53848.744123 # Cycle average of tags in use -system.l2c.tags.total_refs 1839089 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137893 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.337073 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39490.919089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.921030 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4011.444595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2831.104153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.348710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3706.565293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3793.440412 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602584 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821667 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22072 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4261 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31010 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198052 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403774 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581377 # number of Writeback hits -system.l2c.Writeback_hits::total 581377 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 735 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2076 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 150 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 360 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48293 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106952 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22072 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4261 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386985 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256711 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510726 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22072 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4261 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386985 # number of overall hits -system.l2c.overall_hits::cpu0.data 214948 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31010 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5009 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589730 # number of overall hits -system.l2c.overall_hits::cpu1.data 256711 # number of overall hits -system.l2c.overall_hits::total 1510726 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6380 # number of ReadReq misses +system.l2c.tags.replacements 72758 # number of replacements +system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use +system.l2c.tags.total_refs 1836602 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171096604501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184511569236 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036682 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017650 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098854 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61034.531536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1016,64 +981,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 135543504 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146194613 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks) +system.toL2Bus.throughput 136659470 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146072169 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45913386 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7946 # Transaction distribution -system.iobus.trans_dist::WriteResp 7946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46328621 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.trans_dist::WriteReq 7950 # Transaction distribution +system.iobus.trans_dist::WriteResp 7950 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) @@ -1093,38 +1058,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) @@ -1144,42 +1085,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148561 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1220,43 +1137,43 @@ system.iobus.reqLayer22.utilization 0.0 # La system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6007013 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits +system.cpu0.branchPred.lookups 6002321 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8911671 # DTB read hits -system.cpu0.dtb.read_misses 28579 # DTB read misses -system.cpu0.dtb.write_hits 5140325 # DTB write hits -system.cpu0.dtb.write_misses 5457 # DTB write misses +system.cpu0.dtb.read_hits 8907919 # DTB read hits +system.cpu0.dtb.read_misses 28331 # DTB read misses +system.cpu0.dtb.write_hits 5140728 # DTB write hits +system.cpu0.dtb.write_misses 5464 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8940250 # DTB read accesses -system.cpu0.dtb.write_accesses 5145782 # DTB write accesses +system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936250 # DTB read accesses +system.cpu0.dtb.write_accesses 5146192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051996 # DTB hits -system.cpu0.dtb.misses 34036 # DTB misses -system.cpu0.dtb.accesses 14086032 # DTB accesses -system.cpu0.itb.inst_hits 4224524 # ITB inst hits -system.cpu0.itb.inst_misses 5106 # ITB inst misses +system.cpu0.dtb.hits 14048647 # DTB hits +system.cpu0.dtb.misses 33795 # DTB misses +system.cpu0.dtb.accesses 14082442 # DTB accesses +system.cpu0.itb.inst_hits 4222709 # ITB inst hits +system.cpu0.itb.inst_misses 5005 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1265,534 +1182,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses -system.cpu0.itb.hits 4224524 # DTB hits -system.cpu0.itb.misses 5106 # DTB misses -system.cpu0.itb.accesses 4229630 # DTB accesses -system.cpu0.numCycles 69191123 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses +system.cpu0.itb.hits 4222709 # DTB hits +system.cpu0.itb.misses 5005 # DTB misses +system.cpu0.itb.accesses 4227714 # DTB accesses +system.cpu0.numCycles 69175889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248165 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5684023 13.75% 77.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued -system.cpu0.iq.rate 0.538431 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued +system.cpu0.iq.rate 0.538499 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117476 # number of nop insts executed -system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4856181 # Number of branches executed -system.cpu0.iew.exec_stores 5400494 # Number of stores executed -system.cpu0.iew.exec_rate 0.532957 # Inst execution rate -system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18317228 # num instructions producing a value -system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value +system.cpu0.iew.exec_nop 118484 # number of nop insts executed +system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855002 # Number of branches executed +system.cpu0.iew.exec_stores 5400808 # Number of stores executed +system.cpu0.iew.exec_rate 0.533008 # Inst execution rate +system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18316479 # num instructions producing a value +system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23687602 # Number of instructions committed -system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23686340 # Number of instructions committed +system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430179 # Number of memory references committed -system.cpu0.commit.loads 6278312 # Number of loads committed -system.cpu0.commit.membars 229695 # Number of memory barriers committed -system.cpu0.commit.branches 4246577 # Number of branches committed +system.cpu0.commit.refs 11430263 # Number of memory references committed +system.cpu0.commit.loads 6278477 # Number of loads committed +system.cpu0.commit.membars 229716 # Number of memory barriers committed +system.cpu0.commit.branches 4246456 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489495 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489514 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75722045 # The number of ROB reads -system.cpu0.rob.rob_writes 75784919 # The number of ROB writes -system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23606860 # Number of Instructions Simulated -system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated -system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads -system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 874 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes -system.cpu0.icache.tags.replacements 393301 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits -system.cpu0.icache.overall_hits::total 3798020 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424793 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424793 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424793 # number of overall misses -system.cpu0.icache.overall_misses::total 424793 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5908836480 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5908836480 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4222813 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4222813 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4222813 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4222813 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.919608 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13909.919608 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13909.919608 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3571 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75726854 # The number of ROB reads +system.cpu0.rob.rob_writes 75758265 # The number of ROB writes +system.cpu0.timesIdled 367474 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23605598 # Number of Instructions Simulated +system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated +system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads +system.cpu0.fp_regfile_writes 892 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392795 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits +system.cpu0.icache.overall_hits::total 3796668 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424314 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424314 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424314 # number of overall misses +system.cpu0.icache.overall_misses::total 424314 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.620879 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30958 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30958 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30958 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30958 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30958 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30958 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393835 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393835 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393835 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393835 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393835 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393835 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811729884 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811729884 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811729884 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4811729884 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811729884 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4811729884 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9686500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9686500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093264 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093264 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093264 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.628916 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30982 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30982 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30982 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30982 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30982 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30982 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4803860873 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8948750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8948750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8948750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8948750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093185 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093185 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093185 # 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number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5784459 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159328 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159328 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139329 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139329 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137110 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137110 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8943787 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8943787 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8943787 # number of overall hits -system.cpu0.dcache.overall_hits::total 8943787 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392022 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392022 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6176481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148086 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148086 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10920596 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10920596 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10920596 # 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average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9474 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7234 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 614 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 133 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.429967 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 54.390977 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 276222 # 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number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139147 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139147 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137077 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137077 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8941010 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8941010 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8941010 # number of overall hits +system.cpu0.dcache.overall_hits::total 8941010 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 391790 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 391790 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584826 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584826 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8742 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8742 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976616 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976616 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976616 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976616 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82839349724 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82839349724 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks -system.cpu0.dcache.writebacks::total 256588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1800,38 +1713,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9066954 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits +system.cpu1.branchPred.lookups 8782132 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42909677 # DTB read hits -system.cpu1.dtb.read_misses 36560 # DTB read misses -system.cpu1.dtb.write_hits 6823585 # DTB write hits -system.cpu1.dtb.write_misses 10691 # DTB write misses +system.cpu1.dtb.read_hits 42691295 # DTB read hits +system.cpu1.dtb.read_misses 36496 # DTB read misses +system.cpu1.dtb.write_hits 6824033 # DTB write hits +system.cpu1.dtb.write_misses 10597 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42946237 # DTB read accesses -system.cpu1.dtb.write_accesses 6834276 # DTB write accesses +system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42727791 # DTB read accesses +system.cpu1.dtb.write_accesses 6834630 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49733262 # DTB hits -system.cpu1.dtb.misses 47251 # DTB misses -system.cpu1.dtb.accesses 49780513 # DTB accesses -system.cpu1.itb.inst_hits 8323198 # ITB inst hits -system.cpu1.itb.inst_misses 5400 # ITB inst misses +system.cpu1.dtb.hits 49515328 # DTB hits +system.cpu1.dtb.misses 47093 # DTB misses +system.cpu1.dtb.accesses 49562421 # DTB accesses +system.cpu1.itb.inst_hits 7577708 # ITB inst hits +system.cpu1.itb.inst_misses 5297 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1844,109 +1757,109 @@ system.cpu1.itb.flush_entries 1529 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses -system.cpu1.itb.hits 8323198 # DTB hits -system.cpu1.itb.misses 5400 # DTB misses -system.cpu1.itb.accesses 8328598 # DTB accesses -system.cpu1.numCycles 410695591 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses +system.cpu1.itb.hits 7577708 # DTB hits +system.cpu1.itb.misses 5297 # DTB misses +system.cpu1.itb.accesses 7583005 # DTB accesses +system.cpu1.numCycles 408491180 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84850695 73.63% 73.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8420843 7.31% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available @@ -1975,395 +1888,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued -system.cpu1.iq.rate 0.217032 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued +system.cpu1.iq.rate 0.214723 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103450 # number of nop insts executed -system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6997831 # Number of branches executed -system.cpu1.iew.exec_stores 7109746 # Number of stores executed -system.cpu1.iew.exec_rate 0.211381 # Inst execution rate -system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29958578 # num instructions producing a value -system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value +system.cpu1.iew.exec_nop 103701 # number of nop insts executed +system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912906 # Number of branches executed +system.cpu1.iew.exec_stores 7110178 # Number of stores executed +system.cpu1.iew.exec_rate 0.210505 # Inst execution rate +system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29710424 # num instructions producing a value +system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38067147 # Number of instructions committed -system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38066252 # Number of instructions committed +system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596748 # Number of memory references committed -system.cpu1.commit.loads 9756215 # Number of loads committed -system.cpu1.commit.membars 190139 # Number of memory barriers committed -system.cpu1.commit.branches 5967970 # Number of branches committed +system.cpu1.commit.refs 16596165 # Number of memory references committed +system.cpu1.commit.loads 9755785 # Number of loads committed +system.cpu1.commit.membars 190126 # Number of memory barriers committed +system.cpu1.commit.branches 5967905 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534679 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534650 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 174041277 # The number of ROB reads -system.cpu1.rob.rob_writes 131120872 # The number of ROB writes -system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37997508 # Number of Instructions Simulated -system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated -system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads -system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596092 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits -system.cpu1.icache.overall_hits::total 7679654 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641686 # number of overall misses -system.cpu1.icache.overall_misses::total 641686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8725652874 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8725652874 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.077113 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3474 # number of cycles access was blocked +system.cpu1.rob.rob_reads 169461098 # The number of ROB reads +system.cpu1.rob.rob_writes 125154390 # The number of ROB writes +system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37996613 # Number of Instructions Simulated +system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated +system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads +system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes +system.cpu1.icache.tags.replacements 594712 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits +system.cpu1.icache.overall_hits::total 6935744 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses +system.cpu1.icache.overall_misses::total 640085 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 210 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.542857 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 45060 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 45060 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 45060 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 45060 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596626 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596626 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596626 # 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miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks -system.cpu1.dcache.writebacks::total 324789 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396532 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396532 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1437 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1437 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566627 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566627 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566627 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566627 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228081 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228081 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161620 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161620 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12503 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12503 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10598 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10598 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389701 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389701 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389701 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389701 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2839406051 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2839406051 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6490016907 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7073.142686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7073.142686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.824023 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.824023 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks +system.cpu1.dcache.writebacks::total 324751 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2371,12 +2284,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2385,18 +2298,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 49ef0687e..6a97d3f47 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,131 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534332 # Number of seconds simulated -sim_ticks 2534332336000 # Number of ticks simulated -final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.524310 # Number of seconds simulated +sim_ticks 2524309551500 # Number of ticks simulated +final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60160 # Simulator instruction rate (inst/s) -host_op_rate 77409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2528112838 # Simulator tick rate (ticks/s) -host_mem_usage 401532 # Number of bytes of host memory used -host_seconds 1002.46 # Real time elapsed on the host -sim_insts 60307773 # Number of instructions simulated -sim_ops 77599321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 81082 # Simulator instruction rate (inst/s) +host_op_rate 104330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3394002800 # Simulator tick rate (ticks/s) +host_mem_usage 397632 # Number of bytes of host memory used +host_seconds 743.76 # Real time elapsed on the host +sim_insts 60305560 # Number of instructions simulated +sim_ops 77596391 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory -system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15101237 # Total number of read requests seen -system.physmem.writeReqs 813162 # Total number of write requests seen -system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966479168 # Total number of bytes read from memory -system.physmem.bytesWritten 52042368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 966197440 # Total number of bytes read from memory +system.physmem.bytesWritten 52040704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534332242000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2524308440000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14946576 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154625 # Categorize read packet sizes +system.physmem.readPktSize::6 154591 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59144 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -139,316 +140,294 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation -system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests -system.physmem.totBusLat 75504790000 # Total cycles spent in databus access -system.physmem.totBankLat 15713238750 # Total cycles spent in bank access -system.physmem.avgQLat 23320.54 # Average queueing delay per request -system.physmem.avgBankLat 1040.55 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation +system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests +system.physmem.totBusLat 75453215000 # Total cycles spent in databus access +system.physmem.totBankLat 15307050000 # Total cycles spent in bank access +system.physmem.avgQLat 19314.15 # Average queueing delay per request +system.physmem.avgBankLat 1014.34 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29361.08 # Average memory access latency -system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25328.49 # Average memory access latency +system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 10.77 # Average write queue length over time -system.physmem.readRowHits 15074158 # Number of row buffer hits during reads -system.physmem.writeRowHits 797610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes -system.physmem.avgGap 159247.75 # Average gap between requests +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 14.41 # Average write queue length over time +system.physmem.readRowHits 15065383 # Number of row buffer hits during reads +system.physmem.writeRowHits 94229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes +system.physmem.avgGap 158662.04 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -461,60 +440,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54715776 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16153842 # Transaction distribution -system.membus.trans_dist::ReadResp 16153842 # Transaction distribution -system.membus.trans_dist::WriteReq 763336 # Transaction distribution -system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149440 # Transaction distribution +system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.trans_dist::WriteReq 763332 # Transaction distribution +system.membus.trans_dist::WriteResp 763332 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution -system.membus.trans_dist::ReadExReq 131438 # Transaction distribution -system.membus.trans_dist::ReadExResp 131438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138667961 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138629141 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -522,15 +491,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48124265 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution -system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution -system.iobus.trans_dist::WriteReq 8158 # Transaction distribution -system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.throughput 48301509 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.trans_dist::WriteReq 8157 # Transaction distribution +system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -550,38 +519,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -601,42 +546,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121962881 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927961 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -676,44 +597,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14663186 # Number of BP lookups -system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits +system.cpu.branchPred.lookups 14390442 # Number of BP lookups +system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389107 # DTB read hits -system.cpu.dtb.read_misses 64168 # DTB read misses -system.cpu.dtb.write_hits 11699261 # DTB write hits -system.cpu.dtb.write_misses 15977 # DTB write misses +system.cpu.dtb.read_hits 51188083 # DTB read hits +system.cpu.dtb.read_misses 64353 # DTB read misses +system.cpu.dtb.write_hits 11697459 # DTB write hits +system.cpu.dtb.write_misses 15788 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51453275 # DTB read accesses -system.cpu.dtb.write_accesses 11715238 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252436 # DTB read accesses +system.cpu.dtb.write_accesses 11713247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63088368 # DTB hits -system.cpu.dtb.misses 80145 # DTB misses -system.cpu.dtb.accesses 63168513 # DTB accesses -system.cpu.itb.inst_hits 12244686 # ITB inst hits -system.cpu.itb.inst_misses 11272 # ITB inst misses +system.cpu.dtb.hits 62885542 # DTB hits +system.cpu.dtb.misses 80141 # DTB misses +system.cpu.dtb.accesses 62965683 # DTB accesses +system.cpu.itb.inst_hits 11520428 # ITB inst hits +system.cpu.itb.inst_misses 11439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -722,114 +643,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12255958 # ITB inst accesses -system.cpu.itb.hits 12244686 # DTB hits -system.cpu.itb.misses 11272 # DTB misses -system.cpu.itb.accesses 12255958 # DTB accesses -system.cpu.numCycles 475312551 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11531867 # ITB inst accesses +system.cpu.itb.hits 11520428 # DTB hits +system.cpu.itb.misses 11439 # DTB misses +system.cpu.itb.accesses 11531867 # DTB accesses +system.cpu.numCycles 473080437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -857,416 +778,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued -system.cpu.iq.rate 0.261503 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued +system.cpu.iq.rate 0.259812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222537 # number of nop insts executed -system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed -system.cpu.iew.exec_branches 11556571 # Number of branches executed -system.cpu.iew.exec_stores 12211191 # Number of stores executed -system.cpu.iew.exec_rate 0.255895 # Inst execution rate -system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268516 # num instructions producing a value -system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value +system.cpu.iew.exec_nop 221034 # number of nop insts executed +system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed +system.cpu.iew.exec_branches 11474602 # Number of branches executed +system.cpu.iew.exec_stores 12209197 # Number of stores executed +system.cpu.iew.exec_rate 0.255417 # Inst execution rate +system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47030253 # num instructions producing a value +system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back +system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458154 # Number of instructions committed -system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60455941 # Number of instructions committed +system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386643 # Number of memory references committed -system.cpu.commit.loads 15654562 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961356 # Number of branches committed +system.cpu.commit.refs 27385481 # Number of memory references committed +system.cpu.commit.loads 15653838 # Number of loads committed +system.cpu.commit.membars 403568 # Number of memory barriers committed +system.cpu.commit.branches 9961054 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. -system.cpu.commit.function_calls 991265 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. +system.cpu.commit.function_calls 991205 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243752783 # The number of ROB reads -system.cpu.rob.rob_writes 201807644 # The number of ROB writes -system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307773 # Number of Instructions Simulated -system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated -system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550637144 # number of integer regfile reads -system.cpu.int_regfile_writes 88566595 # number of integer regfile writes -system.cpu.fp_regfile_reads 8370 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads -system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 239241509 # The number of ROB reads +system.cpu.rob.rob_writes 195965670 # The number of ROB writes +system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305560 # Number of Instructions Simulated +system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated +system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547265501 # number of integer regfile reads +system.cpu.int_regfile_writes 87536109 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2916 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads +system.cpu.misc_regfile_writes 831835 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits -system.cpu.icache.overall_hits::total 11180201 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses -system.cpu.icache.overall_misses::total 1060929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked +system.cpu.icache.tags.replacements 979660 # number of replacements +system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits +system.cpu.icache.overall_hits::total 10456897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses +system.cpu.icache.overall_misses::total 1059959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980205 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1387,161 +1308,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643201 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21499493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643713 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.399190 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 48741250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13746666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13746666 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259188 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242891 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242891 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21005854 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # 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average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked +system.cpu.dcache.tags.replacements 643614 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits +system.cpu.dcache.overall_hits::total 21018772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses +system.cpu.dcache.overall_misses::total 3700946 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks -system.cpu.dcache.writebacks::total 607541 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks +system.cpu.dcache.writebacks::total 607864 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1549,12 +1470,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1563,16 +1484,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2906c8c25..9d62fc018 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,163 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403594 # Number of seconds simulated -sim_ticks 2403594294500 # Number of ticks simulated -final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403596 # Number of seconds simulated +sim_ticks 2403595690000 # Number of ticks simulated +final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127977 # Simulator instruction rate (inst/s) -host_op_rate 164357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5098961801 # Simulator tick rate (ticks/s) -host_mem_usage 401544 # Number of bytes of host memory used -host_seconds 471.39 # Real time elapsed on the host -sim_insts 60327163 # Number of instructions simulated -sim_ops 77476179 # Number of ops (including micro ops) simulated +host_inst_rate 160402 # Simulator instruction rate (inst/s) +host_op_rate 206018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6390741250 # Simulator tick rate (ticks/s) +host_mem_usage 398660 # Number of bytes of host memory used +host_seconds 376.11 # Real time elapsed on the host +sim_insts 60328186 # Number of instructions simulated +sim_ops 77484426 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory -system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13478004 # Total number of read requests seen -system.physmem.writeReqs 390132 # Total number of write requests seen -system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 862592256 # Total number of bytes read from memory -system.physmem.bytesWritten 24968448 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 862684288 # Total number of bytes read from memory +system.physmem.bytesWritten 28573504 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402559124000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2402560453500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443872 # Categorize read packet sizes +system.physmem.readPktSize::3 13443840 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34124 # Categorize read packet sizes +system.physmem.readPktSize::6 35594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 373031 # Categorize write packet sizes +system.physmem.writePktSize::2 429373 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17101 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17088 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -173,191 +178,188 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 16973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 16965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 16963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 16956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 16951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 16946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 16929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation -system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests -system.physmem.totBusLat 67390020000 # Total cycles spent in databus access -system.physmem.totBankLat 12458627500 # Total cycles spent in bank access -system.physmem.avgQLat 19290.04 # Average queueing delay per request -system.physmem.avgBankLat 924.37 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation +system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests +system.physmem.totBusLat 67397210000 # Total cycles spent in databus access +system.physmem.totBankLat 12480421250 # Total cycles spent in bank access +system.physmem.avgQLat 19262.87 # Average queueing delay per request +system.physmem.avgBankLat 925.89 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25214.41 # Average memory access latency -system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25188.75 # Average memory access latency +system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.88 # Data bus utilization in percentage +system.physmem.busUtil 2.90 # Data bus utilization in percentage system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.40 # Average write queue length over time -system.physmem.readRowHits 13460829 # Number of row buffer hits during reads -system.physmem.writeRowHits 385299 # Number of row buffer hits during writes +system.physmem.avgWrQLen 0.39 # Average write queue length over time +system.physmem.readRowHits 13462207 # Number of row buffer hits during reads +system.physmem.writeRowHits 40077 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes -system.physmem.avgGap 173243.12 # Average gap between requests +system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes +system.physmem.avgGap 172524.57 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -370,315 +372,323 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55672102 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817032 # Transaction distribution -system.membus.trans_dist::ReadResp 13817032 # Transaction distribution -system.membus.trans_dist::WriteReq 375870 # Transaction distribution -system.membus.trans_dist::WriteResp 375870 # Transaction distribution -system.membus.trans_dist::Writeback 17101 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution -system.membus.trans_dist::ReadExReq 26474 # Transaction distribution -system.membus.trans_dist::ReadExResp 26474 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes) +system.membus.throughput 55673401 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13817014 # Transaction distribution +system.membus.trans_dist::ReadResp 13817014 # Transaction distribution +system.membus.trans_dist::WriteReq 432240 # Transaction distribution +system.membus.trans_dist::WriteResp 432240 # Transaction distribution +system.membus.trans_dist::Writeback 17088 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution +system.membus.trans_dist::ReadExReq 28007 # Transaction distribution +system.membus.trans_dist::ReadExResp 28007 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133813146 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133816346 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63199 # number of replacements -system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use -system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.021904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768287 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3220 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 462102 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166367 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2587 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1159 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 134524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18045 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282039 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 141097 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290004 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597664 # number of Writeback hits -system.l2c.Writeback_hits::total 597664 # number of Writeback hits +system.l2c.tags.replacements 63232 # number of replacements +system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use +system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007852 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768822 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8792 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 468268 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1162 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 128925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18612 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281840 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131110 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits +system.l2c.Writeback_hits::total 597529 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19412 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33407 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113612 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 462102 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 227160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 134524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 85166 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18045 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -831,52 +853,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58801079 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution +system.toL2Bus.throughput 58805533 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141234858 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141242678 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764132 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution -system.iobus.trans_dist::WriteReq 2769 # Transaction distribution -system.iobus.trans_dist::WriteResp 2769 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48764104 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution +system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution +system.iobus.trans_dist::WriteReq 2797 # Transaction distribution +system.iobus.trans_dist::WriteResp 2797 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -892,42 +914,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -943,42 +941,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -986,7 +960,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1018,35 +992,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8066197 # DTB read hits -system.cpu0.dtb.read_misses 6232 # DTB read misses -system.cpu0.dtb.write_hits 6664992 # DTB write hits -system.cpu0.dtb.write_misses 2050 # DTB write misses +system.cpu0.dtb.read_hits 8004008 # DTB read hits +system.cpu0.dtb.read_misses 6222 # DTB read misses +system.cpu0.dtb.write_hits 6595133 # DTB write hits +system.cpu0.dtb.write_misses 2001 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8072429 # DTB read accesses -system.cpu0.dtb.write_accesses 6667042 # DTB write accesses +system.cpu0.dtb.read_accesses 8010230 # DTB read accesses +system.cpu0.dtb.write_accesses 6597134 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14731189 # DTB hits -system.cpu0.dtb.misses 8282 # DTB misses -system.cpu0.dtb.accesses 14739471 # DTB accesses -system.cpu0.itb.inst_hits 32886560 # ITB inst hits -system.cpu0.itb.inst_misses 3493 # ITB inst misses +system.cpu0.dtb.hits 14599141 # DTB hits +system.cpu0.dtb.misses 8223 # DTB misses +system.cpu0.dtb.accesses 14607364 # DTB accesses +system.cpu0.itb.inst_hits 32379967 # ITB inst hits +system.cpu0.itb.inst_misses 3492 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1055,407 +1029,407 @@ system.cpu0.itb.flush_tlb 279 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2599 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32890053 # ITB inst accesses -system.cpu0.itb.hits 32886560 # DTB hits -system.cpu0.itb.misses 3493 # DTB misses -system.cpu0.itb.accesses 32890053 # DTB accesses -system.cpu0.numCycles 114224752 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses +system.cpu0.itb.hits 32379967 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8185092 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4040461 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44608202 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32382649 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8185092 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4040461 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44608202 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076590 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076590 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076590 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6485.426260 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6485.426260 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6485.426260 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4261 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 244 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.688525 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24229 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24229 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24229 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24229 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24229 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24229 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130192 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285230 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 10.396627 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.787658 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966431 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.020306 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013257 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6949237 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1880036 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4481409 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13310682 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5977872 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1354370 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021469 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019323 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049848 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044720 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020904 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1468,26 +1442,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2159851 # DTB read hits -system.cpu1.dtb.read_misses 2083 # DTB read misses -system.cpu1.dtb.write_hits 1460405 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses +system.cpu1.dtb.read_hits 2098287 # DTB read hits +system.cpu1.dtb.read_misses 2070 # DTB read misses +system.cpu1.dtb.write_hits 1420937 # DTB write hits +system.cpu1.dtb.write_misses 371 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2161934 # DTB read accesses -system.cpu1.dtb.write_accesses 1460778 # DTB write accesses +system.cpu1.dtb.read_accesses 2100357 # DTB read accesses +system.cpu1.dtb.write_accesses 1421308 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3620256 # DTB hits -system.cpu1.dtb.misses 2456 # DTB misses -system.cpu1.dtb.accesses 3622712 # DTB accesses -system.cpu1.itb.inst_hits 8340023 # ITB inst hits +system.cpu1.dtb.hits 3519224 # DTB hits +system.cpu1.dtb.misses 2441 # DTB misses +system.cpu1.dtb.accesses 3521665 # DTB accesses +system.cpu1.itb.inst_hits 8185092 # ITB inst hits system.cpu1.itb.inst_misses 1172 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1504,66 +1478,66 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses -system.cpu1.itb.hits 8340023 # DTB hits +system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses +system.cpu1.itb.hits 8185092 # DTB hits system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8341195 # DTB accesses -system.cpu1.numCycles 580203695 # number of cpu cycles simulated +system.cpu1.itb.accesses 8186264 # DTB accesses +system.cpu1.numCycles 580203625 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8134078 # Number of instructions committed -system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses -system.cpu1.num_func_calls 319009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9286356 # number of integer instructions -system.cpu1.num_fp_insts 2127 # number of float instructions -system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read +system.cpu1.committedInsts 7980801 # Number of instructions committed +system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses +system.cpu1.num_func_calls 304668 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9072894 # number of integer instructions +system.cpu1.num_fp_insts 2143 # number of float instructions +system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3795930 # number of memory refs -system.cpu1.num_load_insts 2256544 # Number of load instructions -system.cpu1.num_store_insts 1539386 # Number of store instructions -system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles -system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles -system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles +system.cpu1.num_mem_refs 3686646 # number of memory refs +system.cpu1.num_load_insts 2191239 # Number of load instructions +system.cpu1.num_store_insts 1495407 # Number of store instructions +system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles +system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4707573 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits +system.cpu2.branchPred.lookups 4715473 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881991 # DTB read hits -system.cpu2.dtb.read_misses 22472 # DTB read misses -system.cpu2.dtb.write_hits 3235005 # DTB write hits -system.cpu2.dtb.write_misses 5987 # DTB write misses +system.cpu2.dtb.read_hits 10976033 # DTB read hits +system.cpu2.dtb.read_misses 22752 # DTB read misses +system.cpu2.dtb.write_hits 3346841 # DTB write hits +system.cpu2.dtb.write_misses 6453 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10904463 # DTB read accesses -system.cpu2.dtb.write_accesses 3240992 # DTB write accesses +system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10998785 # DTB read accesses +system.cpu2.dtb.write_accesses 3353294 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14116996 # DTB hits -system.cpu2.dtb.misses 28459 # DTB misses -system.cpu2.dtb.accesses 14145455 # DTB accesses -system.cpu2.itb.inst_hits 3987789 # ITB inst hits -system.cpu2.itb.inst_misses 4600 # ITB inst misses +system.cpu2.dtb.hits 14322874 # DTB hits +system.cpu2.dtb.misses 29205 # DTB misses +system.cpu2.dtb.accesses 14352079 # DTB accesses +system.cpu2.itb.inst_hits 4041881 # ITB inst hits +system.cpu2.itb.inst_misses 4586 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1572,290 +1546,290 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses -system.cpu2.itb.hits 3987789 # DTB hits -system.cpu2.itb.misses 4600 # DTB misses -system.cpu2.itb.accesses 3992389 # DTB accesses -system.cpu2.numCycles 88356031 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses +system.cpu2.itb.hits 4041881 # DTB hits +system.cpu2.itb.misses 4586 # DTB misses +system.cpu2.itb.accesses 4046467 # DTB accesses +system.cpu2.numCycles 88343562 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 159360013 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27348 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued -system.cpu2.iq.rate 0.386431 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued +system.cpu2.iq.rate 0.393716 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 83174 # number of nop insts executed -system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3671566 # Number of branches executed -system.cpu2.iew.exec_stores 3366150 # Number of stores executed -system.cpu2.iew.exec_rate 0.376273 # Inst execution rate -system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15610718 # num instructions producing a value -system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value +system.cpu2.iew.exec_nop 82963 # number of nop insts executed +system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3700003 # Number of branches executed +system.cpu2.iew.exec_stores 3481019 # Number of stores executed +system.cpu2.iew.exec_rate 0.383342 # Inst execution rate +system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16087448 # num instructions producing a value +system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19845047 # Number of instructions committed -system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20506693 # Number of instructions committed +system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8180202 # Number of memory references committed -system.cpu2.commit.loads 4956013 # Number of loads committed -system.cpu2.commit.membars 94398 # Number of memory barriers committed -system.cpu2.commit.branches 3153060 # Number of branches committed -system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294560 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8417234 # Number of memory references committed +system.cpu2.commit.loads 5080715 # Number of loads committed +system.cpu2.commit.membars 94304 # Number of memory barriers committed +system.cpu2.commit.branches 3173719 # Number of branches committed +system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294799 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66215885 # The number of ROB reads -system.cpu2.rob.rob_writes 65102408 # The number of ROB writes -system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19789566 # Number of Instructions Simulated -system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated -system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads -system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.rob.rob_reads 66675347 # The number of ROB reads +system.cpu2.rob.rob_writes 66130617 # The number of ROB writes +system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20451214 # Number of Instructions Simulated +system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated +system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads +system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1864,10 +1838,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index c58b97d9e..62d3d2d33 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,151 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548515 # Number of seconds simulated -sim_ticks 2548515380000 # Number of ticks simulated -final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548576 # Number of seconds simulated +sim_ticks 2548576209000 # Number of ticks simulated +final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61977 # Simulator instruction rate (inst/s) -host_op_rate 79748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2618667230 # Simulator tick rate (ticks/s) -host_mem_usage 403588 # Number of bytes of host memory used -host_seconds 973.21 # Real time elapsed on the host -sim_insts 60316341 # Number of instructions simulated -sim_ops 77611368 # Number of ops (including micro ops) simulated +host_inst_rate 60580 # Simulator instruction rate (inst/s) +host_op_rate 77951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2559708219 # Simulator tick rate (ticks/s) +host_mem_usage 399668 # Number of bytes of host memory used +host_seconds 995.65 # Real time elapsed on the host +sim_insts 60316464 # Number of instructions simulated +sim_ops 77611603 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory +system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293471 # Total number of read requests seen -system.physmem.writeReqs 813167 # Total number of write requests seen -system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782144 # Total number of bytes read from memory -system.physmem.bytesWritten 52042688 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 978779776 # Total number of bytes read from memory +system.physmem.bytesWritten 52041088 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548513467000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548575024500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154613 # Categorize read packet sizes +system.physmem.readPktSize::6 154576 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59142 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59117 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -156,215 +157,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation -system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467280000 # Total cycles spent in databus access -system.physmem.totBankLat 15415042500 # Total cycles spent in bank access -system.physmem.avgQLat 19971.40 # Average queueing delay per request -system.physmem.avgBankLat 1007.95 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation +system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467105000 # Total cycles spent in databus access +system.physmem.totBankLat 15338248750 # Total cycles spent in bank access +system.physmem.avgQLat 19242.51 # Average queueing delay per request +system.physmem.avgBankLat 1002.93 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25979.35 # Average memory access latency -system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25245.45 # Average memory access latency +system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15267858 # Number of row buffer hits during reads -system.physmem.writeRowHits 798688 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 1.08 # Average write queue length over time +system.physmem.readRowHits 15268174 # Number of row buffer hits during reads +system.physmem.writeRowHits 94166 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes -system.physmem.avgGap 158227.53 # Average gap between requests +system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes +system.physmem.avgGap 158231.96 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -377,291 +368,277 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55014417 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346104 # Transaction distribution -system.membus.trans_dist::ReadResp 16346107 # Transaction distribution +system.membus.throughput 55011549 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346066 # Transaction distribution +system.membus.trans_dist::ReadResp 16346069 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59142 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution +system.membus.trans_dist::Writeback 59117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution -system.membus.trans_dist::ReadExReq 131412 # Transaction distribution -system.membus.trans_dist::ReadExResp 131412 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution +system.membus.trans_dist::ReadExReq 131414 # Transaction distribution +system.membus.trans_dist::ReadExResp 131414 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205089 # Total data (bytes) +system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140201125 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64386 # number of replacements -system.l2c.tags.tagsinuse 51442.070809 # Cycle average of tags in use -system.l2c.tags.total_refs 1905390 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.682145 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2511428822500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36972.715861 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.496871 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4611.296465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3332.598424 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.513991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3606.043873 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.404957 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564159 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050851 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055024 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784944 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 33100 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6967 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 497324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183110 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30320 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6628 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 474382 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 204508 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436339 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608377 # number of Writeback hits -system.l2c.Writeback_hits::total 608377 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 25 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.tags.replacements 64349 # number of replacements +system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use +system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # 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average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -852,49 +829,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58503668 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution +system.toL2Bus.throughput 58475740 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148893341 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148824185 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48459921 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution +system.iobus.throughput 48458766 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -916,36 +893,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -967,38 +920,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500853 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500857 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1044,684 +973,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7460849 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits +system.cpu0.branchPred.lookups 7055231 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25704058 # DTB read hits -system.cpu0.dtb.read_misses 39030 # DTB read misses -system.cpu0.dtb.write_hits 5997479 # DTB write hits -system.cpu0.dtb.write_misses 9591 # DTB write misses -system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25604020 # DTB read hits +system.cpu0.dtb.read_misses 37101 # DTB read misses +system.cpu0.dtb.write_hits 6019786 # DTB write hits +system.cpu0.dtb.write_misses 10089 # DTB write misses +system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25743088 # DTB read accesses -system.cpu0.dtb.write_accesses 6007070 # DTB write accesses +system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25641121 # DTB read accesses +system.cpu0.dtb.write_accesses 6029875 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31701537 # DTB hits -system.cpu0.dtb.misses 48621 # DTB misses -system.cpu0.dtb.accesses 31750158 # DTB accesses -system.cpu0.itb.inst_hits 6247488 # ITB inst hits -system.cpu0.itb.inst_misses 7199 # ITB inst misses +system.cpu0.dtb.hits 31623806 # DTB hits +system.cpu0.dtb.misses 47190 # DTB misses +system.cpu0.dtb.accesses 31670996 # DTB accesses +system.cpu0.itb.inst_hits 5711817 # ITB inst hits +system.cpu0.itb.inst_misses 6786 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses -system.cpu0.itb.hits 6247488 # DTB hits -system.cpu0.itb.misses 7199 # DTB misses -system.cpu0.itb.accesses 6254687 # DTB accesses -system.cpu0.numCycles 237974378 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses +system.cpu0.itb.hits 5711817 # DTB hits +system.cpu0.itb.misses 6786 # DTB misses +system.cpu0.itb.accesses 5718603 # DTB accesses +system.cpu0.numCycles 240384739 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 231623806 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 43568 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued -system.cpu0.iq.rate 0.263684 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued +system.cpu0.iq.rate 0.253933 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118007 # number of nop insts executed -system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5809455 # Number of branches executed -system.cpu0.iew.exec_stores 6240870 # Number of stores executed -system.cpu0.iew.exec_rate 0.258195 # Inst execution rate -system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23902926 # num instructions producing a value -system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value +system.cpu0.iew.exec_nop 102592 # number of nop insts executed +system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5606114 # Number of branches executed +system.cpu0.iew.exec_stores 6265595 # Number of stores executed +system.cpu0.iew.exec_rate 0.249606 # Inst execution rate +system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22855569 # num instructions producing a value +system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30484303 # Number of instructions committed -system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29384265 # Number of instructions committed +system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13890935 # Number of memory references committed -system.cpu0.commit.loads 7914672 # Number of loads committed -system.cpu0.commit.membars 201566 # Number of memory barriers committed -system.cpu0.commit.branches 4969836 # Number of branches committed -system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489123 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13675596 # Number of memory references committed +system.cpu0.commit.loads 7670972 # Number of loads committed +system.cpu0.commit.membars 201047 # Number of memory barriers committed +system.cpu0.commit.branches 4859392 # Number of branches committed +system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions. +system.cpu0.commit.function_calls 491145 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123917155 # The number of ROB reads -system.cpu0.rob.rob_writes 103001078 # The number of ROB writes -system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 160418610 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30404601 # Number of Instructions Simulated -system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated -system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 278728087 # number of integer regfile reads -system.cpu0.int_regfile_writes 45052561 # number of integer regfile writes -system.cpu0.fp_regfile_reads 23012 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19792 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15437173 # number of misc regfile reads -system.cpu0.misc_regfile_writes 403324 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984712 # 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number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087501 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090708 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.089037 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087501 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090708 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.089037 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087501 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090708 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.089037 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13733.624831 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.835844 # 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number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643928 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.992040 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21539454 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644440 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.423521 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 49066250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 194.023961 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 317.968079 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.378953 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.621031 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7084507 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6698400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13782907 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3631868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3629961 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261829 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114762 # 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miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301664 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.277344 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289715 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057148 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.151131 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.148701 # 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average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41697.756018 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36942 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 23867 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 298 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.557874 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80.090604 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 643834 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42568250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.929916 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.063436 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497910 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502077 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6778619 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6998983 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777602 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3655456 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3606248 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261704 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1736,330 +1665,330 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7195832 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits +system.cpu1.branchPred.lookups 7417918 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25676963 # DTB read hits -system.cpu1.dtb.read_misses 36626 # DTB read misses -system.cpu1.dtb.write_hits 5717501 # DTB write hits -system.cpu1.dtb.write_misses 9454 # DTB write misses +system.cpu1.dtb.read_hits 25617777 # DTB read hits +system.cpu1.dtb.read_misses 38543 # DTB read misses +system.cpu1.dtb.write_hits 5691491 # DTB write hits +system.cpu1.dtb.write_misses 8859 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25713589 # DTB read accesses -system.cpu1.dtb.write_accesses 5726955 # DTB write accesses +system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25656320 # DTB read accesses +system.cpu1.dtb.write_accesses 5700350 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31394464 # DTB hits -system.cpu1.dtb.misses 46080 # DTB misses -system.cpu1.dtb.accesses 31440544 # DTB accesses -system.cpu1.itb.inst_hits 5739661 # ITB inst hits -system.cpu1.itb.inst_misses 6710 # ITB inst misses +system.cpu1.dtb.hits 31309268 # DTB hits +system.cpu1.dtb.misses 47402 # DTB misses +system.cpu1.dtb.accesses 31356670 # DTB accesses +system.cpu1.itb.inst_hits 5866342 # ITB inst hits +system.cpu1.itb.inst_misses 7403 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses -system.cpu1.itb.hits 5739661 # DTB hits -system.cpu1.itb.misses 6710 # DTB misses -system.cpu1.itb.accesses 5746371 # DTB accesses -system.cpu1.numCycles 238752144 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses +system.cpu1.itb.hits 5866342 # DTB hits +system.cpu1.itb.misses 7403 # DTB misses +system.cpu1.itb.accesses 5873745 # DTB accesses +system.cpu1.numCycles 234836749 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236708688 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47158 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued -system.cpu1.iq.rate 0.256852 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued +system.cpu1.iq.rate 0.264043 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104499 # number of nop insts executed -system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5717498 # Number of branches executed -system.cpu1.iew.exec_stores 5986557 # Number of stores executed -system.cpu1.iew.exec_rate 0.252464 # Inst execution rate -system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23307297 # num instructions producing a value -system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value +system.cpu1.iew.exec_nop 120626 # number of nop insts executed +system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5888736 # Number of branches executed +system.cpu1.iew.exec_stores 5957830 # Number of stores executed +system.cpu1.iew.exec_rate 0.259565 # Inst execution rate +system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24094324 # num instructions producing a value +system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29982419 # Number of instructions committed -system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31082580 # Number of instructions committed +system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13500203 # Number of memory references committed -system.cpu1.commit.loads 7742766 # Number of loads committed -system.cpu1.commit.membars 202217 # Number of memory barriers committed -system.cpu1.commit.branches 4992962 # Number of branches committed -system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions. -system.cpu1.commit.function_calls 502375 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13715634 # Number of memory references committed +system.cpu1.commit.loads 7986542 # Number of loads committed +system.cpu1.commit.membars 202747 # Number of memory barriers committed +system.cpu1.commit.branches 5103464 # Number of branches committed +system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions. +system.cpu1.commit.function_calls 500366 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120638730 # The number of ROB reads -system.cpu1.rob.rob_writes 97745041 # The number of ROB writes -system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29911740 # Number of Instructions Simulated -system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated -system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads -system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.rob.rob_reads 121076761 # The number of ROB reads +system.cpu1.rob.rob_writes 99705340 # The number of ROB writes +system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31000692 # Number of Instructions Simulated +system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated +system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads +system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads +system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2068,10 +1997,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 96aff7e7e..820046126 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,143 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.630645 # Number of seconds simulated -sim_ticks 2630645085500 # Number of ticks simulated -final_tick 2630645085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.630640 # Number of seconds simulated +sim_ticks 2630640106500 # Number of ticks simulated +final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 281405 # Simulator instruction rate (inst/s) -host_op_rate 358084 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12294669184 # Simulator tick rate (ticks/s) -host_mem_usage 398476 # Number of bytes of host memory used -host_seconds 213.97 # Real time elapsed on the host -sim_insts 60211229 # Number of instructions simulated -sim_ops 76617937 # Number of ops (including micro ops) simulated +host_inst_rate 544255 # Simulator instruction rate (inst/s) +host_op_rate 692557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23778611565 # Simulator tick rate (ticks/s) +host_mem_usage 394548 # Number of bytes of host memory used +host_seconds 110.63 # Real time elapsed on the host +sim_insts 60211209 # Number of instructions simulated +sim_ops 76617916 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 305952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4748752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 398080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4312560 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 305952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 398080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1535008 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481144 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory +system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67410 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57659 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383752 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370286 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811697 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47234139 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1805166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 151324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1639355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50946360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 151324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402765 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2549309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47234139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2388676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 151324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2202389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53495669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690881 # Total number of read requests seen -system.physmem.writeReqs 811697 # Total number of write requests seen -system.physmem.cpureqs 214350 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1004216384 # Total number of bytes read from memory -system.physmem.bytesWritten 51948608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134021792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6706328 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 1004216768 # Total number of bytes read from memory +system.physmem.bytesWritten 51949056 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49026 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51463 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51021 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50517 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2630640666000 # Total gap between requests +system.physmem.totGap 2630635687000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6680 # Categorize read packet sizes system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152169 # Categorize read packet sizes +system.physmem.readPktSize::6 152175 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57659 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1131442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1003950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3836084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2878494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2847936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 44268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57666 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,30 +153,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -184,183 +185,180 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37996 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27796.675861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2568.021256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33333.179984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5396 14.20% 14.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3321 8.74% 22.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2191 5.77% 28.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1656 4.36% 33.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1158 3.05% 36.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1048 2.76% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 789 2.08% 40.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 726 1.91% 42.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 577 1.52% 44.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 474 1.25% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 440 1.16% 46.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 388 1.02% 47.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 251 0.66% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 273 0.72% 49.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 221 0.58% 49.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 258 0.68% 50.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 159 0.42% 50.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 126 0.33% 51.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 108 0.28% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 95 0.25% 51.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 80 0.21% 51.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 156 0.41% 52.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 779 2.05% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 205 0.54% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 146 0.38% 55.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 108 0.28% 55.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 84 0.22% 55.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 80 0.21% 56.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 53 0.14% 56.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 48 0.13% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 45 0.12% 56.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 58 0.15% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 47 0.12% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 26 0.07% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 22 0.06% 56.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 19 0.05% 56.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 19 0.05% 57.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 11 0.03% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 13 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 9 0.02% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 10 0.03% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 16 0.04% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 3 0.01% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 9 0.02% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 4 0.01% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 5 0.01% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 5 0.01% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 15 0.04% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 13 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 8 0.02% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 34 0.09% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 1 0.00% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 1 0.00% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 7 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 5 0.01% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 3 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 6 0.02% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 2 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 4 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 2 0.01% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 5 0.01% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 18 0.05% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 4 0.01% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 3 0.01% 57.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 3 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 1 0.00% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 5 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 3 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 6 0.02% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 2 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 308 0.81% 58.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 58.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 2 0.01% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-19007 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 2 0.01% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 1 0.00% 59.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 2 0.01% 59.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 3 0.01% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 15 0.04% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41215 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55872-55935 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57984-58047 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58240-58303 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15141 39.85% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72832-72895 1 0.00% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::80704-80767 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::86848-86911 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::101184-101247 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129728-129791 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 356 0.94% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37996 # Bytes accessed per row activation -system.physmem.totQLat 300645538000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 395312713000 # Sum of mem lat for all requests -system.physmem.totBusLat 78454275000 # Total cycles spent in databus access -system.physmem.totBankLat 16212900000 # Total cycles spent in bank access -system.physmem.avgQLat 19160.56 # Average queueing delay per request -system.physmem.avgBankLat 1033.27 # Average bank access latency per request +system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation +system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests +system.physmem.totBusLat 78454290000 # Total cycles spent in databus access +system.physmem.totBankLat 16228107500 # Total cycles spent in bank access +system.physmem.avgQLat 19121.93 # Average queueing delay per request +system.physmem.avgBankLat 1034.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25193.83 # Average memory access latency +system.physmem.avgMemAccLat 25156.17 # Average memory access latency system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s @@ -368,12 +366,12 @@ system.physmem.avgConsumedWrBW 2.55 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.26 # Average write queue length over time -system.physmem.readRowHits 15666172 # Number of row buffer hits during reads -system.physmem.writeRowHits 798379 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.25 # Average write queue length over time +system.physmem.readRowHits 15666199 # Number of row buffer hits during reads +system.physmem.writeRowHits 93719 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.36 # Row buffer hit rate for writes -system.physmem.avgGap 159407.86 # Average gap between requests +system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes +system.physmem.avgGap 159407.43 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -386,259 +384,249 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54407285 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743607 # Transaction distribution -system.membus.trans_dist::ReadResp 16743607 # Transaction distribution +system.membus.throughput 54407704 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743613 # Transaction distribution +system.membus.trans_dist::ReadResp 16743613 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57659 # Transaction distribution +system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution system.membus.trans_dist::ReadExReq 131350 # Transaction distribution system.membus.trans_dist::ReadExResp 131350 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32956541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343401 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870001 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 140728120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126257 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126257 # Total data (bytes) +system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143127089 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1209137000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 18109692000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3744500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4946454076 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35060518750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62055 # number of replacements -system.l2c.tags.tagsinuse 51615.482729 # Cycle average of tags in use -system.l2c.tags.total_refs 1699189 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127440 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333247 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2575816655500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38219.751550 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2839.791296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3005.850612 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4181.982232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3368.106163 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063812 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787590 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 10006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3588 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 435821 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 185768 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9923 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3635 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 408641 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 184604 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241986 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596408 # number of Writeback hits -system.l2c.Writeback_hits::total 596408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.tags.replacements 62061 # number of replacements +system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use +system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits +system.l2c.Writeback_hits::total 596358 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54618 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114519 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3588 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 435821 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9923 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 408641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239222 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356505 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10006 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3588 # number of overall hits -system.l2c.overall_hits::cpu0.inst 435821 # number of overall hits -system.l2c.overall_hits::cpu0.data 245669 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9923 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3635 # number of overall hits -system.l2c.overall_hits::cpu1.inst 408641 # number of overall hits -system.l2c.overall_hits::cpu1.data 239222 # number of overall hits -system.l2c.overall_hits::total 1356505 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 436599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 244907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 407829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239916 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356382 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3590 # number of overall hits +system.l2c.overall_hits::cpu0.inst 436599 # number of overall hits +system.l2c.overall_hits::cpu0.data 244907 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9919 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3623 # number of overall hits +system.l2c.overall_hits::cpu1.inst 407829 # number of overall hits +system.l2c.overall_hits::cpu1.data 239916 # number of overall hits +system.l2c.overall_hits::total 1356382 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4367 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5353 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4438 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5378 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6220 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51886.775707 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -786,39 +774,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52767546 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471907 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471907 # Transaction distribution +system.toL2Bus.throughput 52764048 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596408 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1724962 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5753498 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 20327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7549494 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54749620 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83783741 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 138641981 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138641981 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170704 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808390000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138632553 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865864500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4428402674 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13102500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30777250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48142811 # Throughput (bytes/s) +system.iobus.throughput 48142902 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution @@ -849,30 +837,6 @@ system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 1 system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) @@ -900,30 +864,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 126646649 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) @@ -976,139 +916,139 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42579543250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7541054 # DTB read hits -system.cpu0.dtb.read_misses 7077 # DTB read misses -system.cpu0.dtb.write_hits 5712165 # DTB write hits -system.cpu0.dtb.write_misses 1789 # DTB write misses +system.cpu0.dtb.read_hits 7542817 # DTB read hits +system.cpu0.dtb.read_misses 7082 # DTB read misses +system.cpu0.dtb.write_hits 5717425 # DTB write hits +system.cpu0.dtb.write_misses 1778 # DTB write misses system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 146 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7548131 # DTB read accesses -system.cpu0.dtb.write_accesses 5713954 # DTB write accesses +system.cpu0.dtb.read_accesses 7549899 # DTB read accesses +system.cpu0.dtb.write_accesses 5719203 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13253219 # DTB hits -system.cpu0.dtb.misses 8866 # DTB misses -system.cpu0.dtb.accesses 13262085 # DTB accesses -system.cpu0.itb.inst_hits 30586267 # ITB inst hits -system.cpu0.itb.inst_misses 3713 # ITB inst misses +system.cpu0.dtb.hits 13260242 # DTB hits +system.cpu0.dtb.misses 8860 # DTB misses +system.cpu0.dtb.accesses 13269102 # DTB accesses +system.cpu0.itb.inst_hits 30610477 # ITB inst hits +system.cpu0.itb.inst_misses 3712 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2774 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30589980 # ITB inst accesses -system.cpu0.itb.hits 30586267 # DTB hits -system.cpu0.itb.misses 3713 # DTB misses -system.cpu0.itb.accesses 30589980 # DTB accesses -system.cpu0.numCycles 2629433969 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses +system.cpu0.itb.hits 30610477 # DTB hits +system.cpu0.itb.misses 3712 # DTB misses +system.cpu0.itb.accesses 30614189 # DTB accesses +system.cpu0.numCycles 2629428479 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29984771 # Number of instructions committed -system.cpu0.committedOps 38337194 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34488518 # Number of integer alu accesses +system.cpu0.committedInsts 30009354 # Number of instructions committed +system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses -system.cpu0.num_func_calls 1080132 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3980914 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34488518 # number of integer instructions +system.cpu0.num_func_calls 1080838 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34511671 # number of integer instructions system.cpu0.num_fp_insts 5157 # number of float instructions -system.cpu0.num_int_register_reads 197896297 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36953400 # number of times the integer registers were written +system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written -system.cpu0.num_mem_refs 13834370 # number of memory refs -system.cpu0.num_load_insts 7870253 # Number of load instructions -system.cpu0.num_store_insts 5964117 # Number of store instructions -system.cpu0.num_idle_cycles -1415422.936618 # Number of idle cycles -system.cpu0.num_busy_cycles 2630849391.936618 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000538 # Percentage of non-idle cycles -system.cpu0.idle_fraction -0.000538 # Percentage of idle cycles +system.cpu0.num_mem_refs 13842126 # number of memory refs +system.cpu0.num_load_insts 7871888 # Number of load instructions +system.cpu0.num_store_insts 5970238 # Number of store instructions +system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles +system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles +system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856159 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.881074 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648644 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856671 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.795724 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19966906250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.109344 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.771730 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410370 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587445 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30145271 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30503373 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648644 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30145271 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30503373 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648644 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30145271 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30503373 # number of overall hits -system.cpu0.icache.overall_hits::total 60648644 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 440996 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 415675 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856671 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30610477 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30894824 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61505301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014435 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013426 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014418 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013444 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014435 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013426 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013928 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13768.215894 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,158 +1057,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 440996 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 415675 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856671 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 440996 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627599 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.878483 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660456 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628111 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.669227 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 657290250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.795545 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.082938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642740 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6630954 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6567853 # 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Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.673351 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 640880250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.734555 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.147121 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.356903 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999769 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6634061 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6564802 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198863 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5075609 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4899184 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13567845 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5018438 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225204 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120975 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120289 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126785 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120973 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12016619 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11776431 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793050 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12016619 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11776431 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793050 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027132 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027268 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025202 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023753 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044617 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026297 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025768 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026297 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025768 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14791.301209 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14686.291843 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14738.912479 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42146.342890 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42095.346413 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42122.038528 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13350.314872 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14396.031302 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.813149 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25808.589964 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25808.589964 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048594 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044613 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046650 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026241 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025820 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026241 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025820 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14780.678872 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1277,77 +1217,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7088073537 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14679279478 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91858515750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90196579000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182055094750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13241304408 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12994136940 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235441348 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105099820158 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103190715940 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290536098 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027132 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027268 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025202 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023753 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks +system.cpu0.dcache.writebacks::total 596358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048585 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044617 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046658 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12777.255202 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12673.845682 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.664628 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39889.324801 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39839.238743 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39865.454334 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11348.215727 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12384.292901 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11829.238754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1360,76 +1300,76 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7458653 # DTB read hits -system.cpu1.dtb.read_misses 7094 # DTB read misses -system.cpu1.dtb.write_hits 5520448 # DTB write hits -system.cpu1.dtb.write_misses 1859 # DTB write misses +system.cpu1.dtb.read_hits 7456887 # DTB read hits +system.cpu1.dtb.read_misses 7096 # DTB read misses +system.cpu1.dtb.write_hits 5515190 # DTB write hits +system.cpu1.dtb.write_misses 1853 # DTB write misses system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6666 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7465747 # DTB read accesses -system.cpu1.dtb.write_accesses 5522307 # DTB write accesses +system.cpu1.dtb.read_accesses 7463983 # DTB read accesses +system.cpu1.dtb.write_accesses 5517043 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12979101 # DTB hits -system.cpu1.dtb.misses 8953 # DTB misses -system.cpu1.dtb.accesses 12988054 # DTB accesses -system.cpu1.itb.inst_hits 30919048 # ITB inst hits -system.cpu1.itb.inst_misses 3673 # ITB inst misses +system.cpu1.dtb.hits 12972077 # DTB hits +system.cpu1.dtb.misses 8949 # DTB misses +system.cpu1.dtb.accesses 12981026 # DTB accesses +system.cpu1.itb.inst_hits 30894824 # ITB inst hits +system.cpu1.itb.inst_misses 3669 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2817 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30922721 # ITB inst accesses -system.cpu1.itb.hits 30919048 # DTB hits -system.cpu1.itb.misses 3673 # DTB misses -system.cpu1.itb.accesses 30922721 # DTB accesses -system.cpu1.numCycles 2631856202 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses +system.cpu1.itb.hits 30894824 # DTB hits +system.cpu1.itb.misses 3669 # DTB misses +system.cpu1.itb.accesses 30898493 # DTB accesses +system.cpu1.numCycles 2631851734 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30226458 # Number of instructions committed -system.cpu1.committedOps 38280743 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34395206 # Number of integer alu accesses +system.cpu1.committedInsts 30201855 # Number of instructions committed +system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses -system.cpu1.num_func_calls 1060216 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3968456 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34395206 # number of integer instructions +system.cpu1.num_func_calls 1059508 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34372038 # number of integer instructions system.cpu1.num_fp_insts 5112 # number of float instructions -system.cpu1.num_int_register_reads 196952140 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37242776 # number of times the integer registers were written +system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written -system.cpu1.num_mem_refs 13565505 # number of memory refs -system.cpu1.num_load_insts 7793640 # Number of load instructions -system.cpu1.num_store_insts 5771865 # Number of store instructions -system.cpu1.num_idle_cycles 4920851591.451757 # Number of idle cycles -system.cpu1.num_busy_cycles -2288995389.451757 # Number of busy cycles -system.cpu1.not_idle_fraction -0.869727 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.869727 # Percentage of idle cycles +system.cpu1.num_mem_refs 13557754 # number of memory refs +system.cpu1.num_load_insts 7792008 # Number of load instructions +system.cpu1.num_store_insts 5765746 # Number of store instructions +system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles +system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1438,10 +1378,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1478947388250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1478947388250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index da1db81af..610192884 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.133763 # Nu sim_ticks 5133762710000 # Number of ticks simulated final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199223 # Simulator instruction rate (inst/s) -host_op_rate 393808 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2508257843 # Simulator tick rate (ticks/s) -host_mem_usage 730904 # Number of bytes of host memory used -host_seconds 2046.74 # Real time elapsed on the host +host_inst_rate 156198 # Simulator instruction rate (inst/s) +host_op_rate 308758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1966557914 # Simulator tick rate (ticks/s) +host_mem_usage 728732 # Number of bytes of host memory used +host_seconds 2610.53 # Real time elapsed on the host sim_insts 407759186 # Number of instructions simulated sim_ops 806023868 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory @@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222526 # Total number of read requests seen -system.physmem.writeReqs 148565 # Total number of write requests seen -system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 14241664 # Total number of bytes read from memory system.physmem.bytesWritten 9508160 # Total number of bytes written to memory system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis @@ -401,39 +402,31 @@ system.membus.trans_dist::MessageReq 1642 # Tr system.membus.trans_dist::MessageResp 1642 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25548207 # Total data (bytes) system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -441,15 +434,15 @@ system.membus.respLayer2.occupancy 3156883661 # La system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -575,26 +568,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) @@ -619,26 +592,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 3276058 # Total data (bytes) system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks) @@ -968,16 +921,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks) @@ -992,15 +945,15 @@ system.cpu.toL2Bus.respLayer2.occupancy 12430241 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 952820 # number of replacements -system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 952820 # number of replacements +system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits @@ -1077,10 +1030,10 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy @@ -1161,10 +1114,10 @@ system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176. system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy @@ -1240,15 +1193,15 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656828 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1656828 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits @@ -1360,23 +1313,23 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111287 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 111287 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.467907 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.772017 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000144 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047729 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.169245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63059 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6479 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 937263 # number of ReadReq hits diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 236f8b6a2..0d5fa424d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.304405 # Nu sim_ticks 5304405061000 # Number of ticks simulated final_tick 5304405061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226332 # Simulator instruction rate (inst/s) -host_op_rate 434274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11093442301 # Simulator tick rate (ticks/s) -host_mem_usage 870272 # Number of bytes of host memory used -host_seconds 478.16 # Real time elapsed on the host +host_inst_rate 96456 # Simulator instruction rate (inst/s) +host_op_rate 185076 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4727720712 # Simulator tick rate (ticks/s) +host_mem_usage 825708 # Number of bytes of host memory used +host_seconds 1121.98 # Real time elapsed on the host sim_insts 108221987 # Number of instructions simulated sim_ops 207651289 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory @@ -72,14 +72,15 @@ system.physmem.bw_total::cpu1.itb.walker 7758 # To system.physmem.bw_total::cpu1.inst 32140877 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 9555659 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 225885267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 804 # Total number of read requests seen -system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47256 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 51456 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -308,29 +309,6 @@ system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupt system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.physmem.port 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1372 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.i_dont_exist.pio 33352 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.com_1.pio 26412 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.cpu0.interrupts.pio 751802 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.cpu0.interrupts.int_slave 2728 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.cpu1.interrupts.int_slave 2670 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) system.piobus.pkt_count::total 1908880 # Packet count per connected master and slave (bytes) system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes) @@ -371,58 +349,35 @@ system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interr system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2744 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 16676 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.com_1.pio 13206 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1503598 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 5456 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 5340 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size::total 5087902 # Cumulative packet size per connected master and slave (bytes) system.piobus.data_through_bus 5087902 # Total data (bytes) -system.piobus.reqLayer0.occupancy 421716677 # Layer occupancy (ticks) +system.piobus.reqLayer0.occupancy 49000 # Layer occupancy (ticks) system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer1.occupancy 49000 # Layer occupancy (ticks) +system.piobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.piobus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks) system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer3.occupancy 10159500 # Layer occupancy (ticks) +system.piobus.reqLayer3.occupancy 140500 # Layer occupancy (ticks) system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks) +system.piobus.reqLayer4.occupancy 1061000 # Layer occupancy (ticks) system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer5.occupancy 1061000 # Layer occupancy (ticks) +system.piobus.reqLayer5.occupancy 97000 # Layer occupancy (ticks) system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer6.occupancy 97000 # Layer occupancy (ticks) +system.piobus.reqLayer6.occupancy 57000 # Layer occupancy (ticks) system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer7.occupancy 57000 # Layer occupancy (ticks) +system.piobus.reqLayer7.occupancy 30437500 # Layer occupancy (ticks) system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer8.occupancy 30437500 # Layer occupancy (ticks) +system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks) system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer9.occupancy 586857000 # Layer occupancy (ticks) +system.piobus.reqLayer9.occupancy 1329000 # Layer occupancy (ticks) system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer10.occupancy 1329000 # Layer occupancy (ticks) +system.piobus.reqLayer10.occupancy 33375500 # Layer occupancy (ticks) system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer11.occupancy 33375500 # Layer occupancy (ticks) +system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.piobus.reqLayer12.occupancy 23058500 # Layer occupancy (ticks) system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer13.occupancy 23058500 # Layer occupancy (ticks) +system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -430,15 +385,15 @@ system.piobus.reqLayer15.occupancy 10500 # La system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer17.occupancy 473807500 # Layer occupancy (ticks) system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer18.occupancy 473807500 # Layer occupancy (ticks) +system.piobus.reqLayer18.occupancy 3197816 # Layer occupancy (ticks) system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer19.occupancy 3197816 # Layer occupancy (ticks) +system.piobus.reqLayer19.occupancy 8805500 # Layer occupancy (ticks) system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer20.occupancy 8805500 # Layer occupancy (ticks) +system.piobus.reqLayer20.occupancy 3140084 # Layer occupancy (ticks) system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer21.occupancy 3140084 # Layer occupancy (ticks) +system.piobus.reqLayer21.occupancy 421716677 # Layer occupancy (ticks) system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer22.occupancy 1081500 # Layer occupancy (ticks) system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 551b52f89..e3d68909a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.139589 # Nu sim_ticks 5139589353000 # Number of ticks simulated final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 286755 # Simulator instruction rate (inst/s) -host_op_rate 569759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6048900638 # Simulator tick rate (ticks/s) -host_mem_usage 936564 # Number of bytes of host memory used -host_seconds 849.67 # Real time elapsed on the host +host_inst_rate 190335 # Simulator instruction rate (inst/s) +host_op_rate 378180 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4014985901 # Simulator tick rate (ticks/s) +host_mem_usage 934028 # Number of bytes of host memory used +host_seconds 1280.10 # Real time elapsed on the host sim_insts 243647713 # Number of instructions simulated sim_ops 484108731 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory @@ -70,14 +70,15 @@ system.physmem.bw_total::cpu2.itb.walker 12 # To system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 96603 # Total number of read requests seen -system.physmem.writeReqs 74912 # Total number of write requests seen -system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 96603 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 74912 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 96603 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 74912 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 6182592 # Total number of bytes read from memory system.physmem.bytesWritten 4794368 # Total number of bytes written to memory system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 12 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis @@ -388,39 +389,31 @@ system.membus.trans_dist::MessageReq 216 # Tr system.membus.trans_dist::MessageResp 216 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 32713165 # Total data (bytes) system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 164366000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314753000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 432000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 793885999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -428,33 +421,33 @@ system.membus.respLayer2.occupancy 1632166487 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 104154 # number of replacements -system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use -system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy +system.l2c.tags.replacements 104154 # number of replacements +system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use +system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits @@ -833,15 +826,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses system.iocache.ReadReq_misses::total 914 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -947,16 +940,16 @@ system.toL2Bus.trans_dist::UpgradeReq 745 # Tr system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 966317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3599461 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 26176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 114965 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4706919 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 30921472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118979348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 89784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 413728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 150404332 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 267998065 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks) @@ -997,22 +990,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1033,22 +1010,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 6479664 # Total data (bytes) system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks) @@ -1107,25 +1068,25 @@ system.cpu0.num_fp_register_writes 0 # nu system.cpu0.num_mem_refs 14736464 # number of memory refs system.cpu0.num_load_insts 10677140 # Number of load instructions system.cpu0.num_store_insts 4059324 # Number of store instructions -system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles -system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles -system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles -system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles +system.cpu0.num_idle_cycles 1727957342.597034 # Number of idle cycles +system.cpu0.num_busy_cycles 93395662.402966 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051278 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948722 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 847048 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 847048 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits @@ -1243,19 +1204,19 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12086.099992 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1634474 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 1634474 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits @@ -1447,10 +1408,10 @@ system.cpu1.num_fp_register_writes 0 # nu system.cpu1.num_mem_refs 4252332 # number of memory refs system.cpu1.num_load_insts 2649427 # Number of load instructions system.cpu1.num_store_insts 1602905 # Number of store instructions -system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles -system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles -system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles -system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles +system.cpu1.num_idle_cycles 2479239642.942777 # Number of idle cycles +system.cpu1.num_busy_cycles 126766142.057223 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951356 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.branchPred.lookups 28549199 # Number of BP lookups diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 307f030d7..14bb680f9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu sim_ticks 26877484000 # Number of ticks simulated final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175198 # Simulator instruction rate (inst/s) -host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51980195 # Simulator tick rate (ticks/s) -host_mem_usage 379404 # Number of bytes of host memory used -host_seconds 517.07 # Real time elapsed on the host +host_inst_rate 190344 # Simulator instruction rate (inst/s) +host_op_rate 191711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56473959 # Simulator tick rate (ticks/s) +host_mem_usage 375760 # Number of bytes of host memory used +host_seconds 475.93 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1671585 # In system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15506 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 992384 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis @@ -214,10 +215,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 992384 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) @@ -546,12 +547,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) @@ -560,15 +561,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1225499 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits @@ -644,19 +645,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits @@ -805,15 +806,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943531 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943531 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 5c365748d..e75e7c0cb 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 662214 # Simulator instruction rate (inst/s) -host_op_rate 666963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1075722156 # Simulator tick rate (ticks/s) -host_mem_usage 375060 # Number of bytes of host memory used -host_seconds 136.78 # Real time elapsed on the host +host_inst_rate 529408 # Simulator instruction rate (inst/s) +host_op_rate 533204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 859987474 # Simulator tick rate (ticks/s) +host_mem_usage 373720 # Number of bytes of host memory used +host_seconds 171.09 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 792 # Tr system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 981760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Tr system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 2c81bb996..7e2d4c700 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 653861 # Simulator instruction rate (inst/s) -host_op_rate 653888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 969395755 # Simulator tick rate (ticks/s) -host_mem_usage 365508 # Number of bytes of host memory used -host_seconds 372.90 # Real time elapsed on the host +host_inst_rate 810264 # Simulator instruction rate (inst/s) +host_op_rate 810297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1201274596 # Simulator tick rate (ticks/s) +host_mem_usage 365008 # Number of bytes of host memory used +host_seconds 300.92 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 1036 # Tr system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 998592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -405,12 +405,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Tr system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index eb92ec68e..9d42f660f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065502 # Nu sim_ticks 65501881000 # Number of ticks simulated final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72627 # Simulator instruction rate (inst/s) -host_op_rate 127885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30111215 # Simulator tick rate (ticks/s) -host_mem_usage 386704 # Number of bytes of host memory used -host_seconds 2175.33 # Real time elapsed on the host +host_inst_rate 73961 # Simulator instruction rate (inst/s) +host_op_rate 130234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30664297 # Simulator tick rate (ticks/s) +host_mem_usage 385548 # Number of bytes of host memory used +host_seconds 2136.10 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 159263 # To system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30410 # Total number of read requests seen -system.physmem.writeReqs 163 # Total number of write requests seen -system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 1946112 # Total number of bytes read from memory system.physmem.bytesWritten 10432 # Total number of bytes written to memory system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis @@ -232,11 +233,9 @@ system.membus.trans_dist::ReadExReq 29004 # Tr system.membus.trans_dist::ReadExResp 29004 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1956480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -519,12 +518,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) @@ -533,15 +532,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1707500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits @@ -617,19 +616,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 474 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 474 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020368 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1993851 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits @@ -755,15 +754,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072469 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072469 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d47d4ffea..2b38a25ba 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 466388 # Simulator instruction rate (inst/s) -host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1080412484 # Simulator tick rate (ticks/s) -host_mem_usage 431468 # Number of bytes of host memory used -host_seconds 338.75 # Real time elapsed on the host +host_inst_rate 324809 # Simulator instruction rate (inst/s) +host_op_rate 571936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 752437231 # Simulator tick rate (ticks/s) +host_mem_usage 382748 # Number of bytes of host memory used +host_seconds 486.40 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory @@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 29024 # Tr system.membus.trans_dist::ReadExResp 29024 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1929536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 318 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -293,15 +291,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d43c28cd4..d58d3f98b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu sim_ticks 202349747500 # Number of ticks simulated final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166059 # Simulator instruction rate (inst/s) -host_op_rate 187221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66507382 # Simulator tick rate (ticks/s) -host_mem_usage 250660 # Number of bytes of host memory used -host_seconds 3042.52 # Real time elapsed on the host +host_inst_rate 95439 # Simulator instruction rate (inst/s) +host_op_rate 107602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38223736 # Simulator tick rate (ticks/s) +host_mem_usage 246676 # Number of bytes of host memory used +host_seconds 5293.82 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 30890515 # To system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148206 # Total number of read requests seen -system.physmem.writeReqs 97667 # Total number of write requests seen -system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 9485120 # Total number of bytes read from memory system.physmem.bytesWritten 6250688 # Total number of bytes written to memory system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis @@ -297,10 +298,10 @@ system.membus.trans_dist::UpgradeReq 7 # Tr system.membus.trans_dist::UpgradeResp 7 # Transaction distribution system.membus.trans_dist::ReadExReq 101306 # Transaction distribution system.membus.trans_dist::ReadExResp 101306 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15735808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) @@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) @@ -642,15 +643,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 26125731 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15008 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15008 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits @@ -726,19 +727,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 25103.227023 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115462 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 115462 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 23019.815136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.702509 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011145 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.113526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 13469 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 804438 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 817907 # number of ReadReq hits @@ -889,15 +890,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192719 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1192719 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index b28088e7d..3138d4062 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 611042 # Simulator instruction rate (inst/s) -host_op_rate 688541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 868024183 # Simulator tick rate (ticks/s) -host_mem_usage 246240 # Number of bytes of host memory used -host_seconds 826.44 # Real time elapsed on the host +host_inst_rate 1130634 # Simulator instruction rate (inst/s) +host_op_rate 1274033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1606137434 # Simulator tick rate (ticks/s) +host_mem_usage 243872 # Number of bytes of host memory used +host_seconds 446.64 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 41855 # Tr system.membus.trans_dist::Writeback 95953 # Transaction distribution system.membus.trans_dist::ReadExReq 100794 # Transaction distribution system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15270528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1434732024 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9788 # number of replacements +system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 109895 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits @@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Tr system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index d91a5905c..4d8b3de9b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.458202 # Nu sim_ticks 458201684000 # Number of ticks simulated final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111882 # Simulator instruction rate (inst/s) -host_op_rate 206882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61997502 # Simulator tick rate (ticks/s) -host_mem_usage 341328 # Number of bytes of host memory used -host_seconds 7390.65 # Real time elapsed on the host +host_inst_rate 77434 # Simulator instruction rate (inst/s) +host_op_rate 143185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42909026 # Simulator tick rate (ticks/s) +host_mem_usage 338808 # Number of bytes of host memory used +host_seconds 10678.45 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 41005663 # To system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385586 # Total number of read requests seen -system.physmem.writeReqs 293576 # Total number of write requests seen -system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 385586 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 293576 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 385586 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 293576 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 24677504 # Total number of bytes read from memory system.physmem.bytesWritten 18788864 # Total number of bytes written to memory system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis @@ -316,11 +317,9 @@ system.membus.trans_dist::ReadExReq 206848 # Tr system.membus.trans_dist::ReadExResp 206848 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 43466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -606,12 +605,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 146337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7664164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7810501 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311349248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311784960 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks) @@ -620,15 +619,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 209959241 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5293 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5293 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 161845824 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 161845824 # number of demand (read+write) hits @@ -704,19 +703,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 3994.146443 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3994.146443 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 3994.146443 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352905 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 352905 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29673.331814 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3696859 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385269 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595527 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199076310000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21119.362848 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.841801 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8330.127165 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.644512 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006831 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.254215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905558 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3661 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1586701 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1590362 # number of ReadReq hits @@ -862,15 +861,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65139.453621 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59112.047244 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59161.253496 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529980 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2529980 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.352551 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396070659 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534076 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.297861 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 5255bf68c..7c10a36f9 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 533286 # Simulator instruction rate (inst/s) -host_op_rate 986105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1062778196 # Simulator tick rate (ticks/s) -host_mem_usage 304632 # Number of bytes of host memory used -host_seconds 1550.53 # Real time elapsed on the host +host_inst_rate 418246 # Simulator instruction rate (inst/s) +host_op_rate 773383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 833516309 # Simulator tick rate (ticks/s) +host_mem_usage 254900 # Number of bytes of host memory used +host_seconds 1977.01 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory @@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 206691 # Tr system.membus.trans_dist::ReadExResp 206691 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 43099456 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1253 # number of replacements +system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 348459 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits @@ -293,15 +291,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits @@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 3f8921752..e5b6926d1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139916 # Nu sim_ticks 139916242500 # Number of ticks simulated final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84616 # Simulator instruction rate (inst/s) -host_op_rate 84616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29697100 # Simulator tick rate (ticks/s) -host_mem_usage 231112 # Number of bytes of host memory used -host_seconds 4711.44 # Real time elapsed on the host +host_inst_rate 80792 # Simulator instruction rate (inst/s) +host_op_rate 80792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28354866 # Simulator tick rate (ticks/s) +host_mem_usage 231004 # Number of bytes of host memory used +host_seconds 4934.47 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1536462 # In system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7328 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 468992 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis @@ -245,10 +246,10 @@ system.membus.trans_dist::ReadReq 4183 # Tr system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution system.membus.trans_dist::ReadExResp 3145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) @@ -357,15 +358,15 @@ system.cpu.stage3.utilization 35.287049 # Pe system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1975 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits @@ -447,12 +448,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Tr system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16759 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 249792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 557056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) @@ -461,19 +462,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 6540750 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -597,15 +598,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1f99291ed..a56a193ad 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu sim_ticks 77521581000 # Number of ticks simulated final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159390 # Simulator instruction rate (inst/s) -host_op_rate 159390 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32899346 # Simulator tick rate (ticks/s) -host_mem_usage 233160 # Number of bytes of host memory used -host_seconds 2356.33 # Real time elapsed on the host +host_inst_rate 226587 # Simulator instruction rate (inst/s) +host_op_rate 226587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46769350 # Simulator tick rate (ticks/s) +host_mem_usage 233048 # Number of bytes of host memory used +host_seconds 1657.53 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2850716 # In system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis @@ -242,10 +243,10 @@ system.membus.trans_dist::ReadReq 4310 # Tr system.membus.trans_dist::ReadResp 4310 # Transaction distribution system.membus.trans_dist::ReadExReq 3132 # Transaction distribution system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 476288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) @@ -561,12 +562,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Tr system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) @@ -575,15 +576,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 6844000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2147 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2147 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits @@ -659,19 +660,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 371.365398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011333 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090912 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752 # number of ReadReq hits @@ -795,15 +796,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 788 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 788 # number of replacements +system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 2e7f2c614..3ed6163c0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1715092 # Simulator instruction rate (inst/s) -host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2440727076 # Simulator tick rate (ticks/s) -host_mem_usage 230984 # Number of bytes of host memory used -host_seconds 232.45 # Real time elapsed on the host +host_inst_rate 1598767 # Simulator instruction rate (inst/s) +host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2275187152 # Simulator tick rate (ticks/s) +host_mem_usage 229960 # Number of bytes of host memory used +host_seconds 249.36 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4032 # Tr system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 459136 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1769 # number of replacements +system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Tr system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 31843ed63..cfe46b65a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu sim_ticks 68375005500 # Number of ticks simulated final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171790 # Simulator instruction rate (inst/s) -host_op_rate 219625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43020256 # Simulator tick rate (ticks/s) -host_mem_usage 254724 # Number of bytes of host memory used -host_seconds 1589.37 # Real time elapsed on the host +host_inst_rate 121198 # Simulator instruction rate (inst/s) +host_op_rate 154946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30350947 # Simulator tick rate (ticks/s) +host_mem_usage 251080 # Number of bytes of host memory used +host_seconds 2252.81 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2839868 # In system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7288 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 466432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis @@ -243,10 +244,10 @@ system.membus.trans_dist::UpgradeReq 5 # Tr system.membus.trans_dist::UpgradeResp 5 # Transaction distribution system.membus.trans_dist::ReadExReq 2821 # Transaction distribution system.membus.trans_dist::ReadExResp 2821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) @@ -575,12 +576,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) @@ -589,15 +590,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 24379238 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13946 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13946 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits @@ -673,19 +674,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 375.051576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084891 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.023833 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12788 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13086 # number of ReadReq hits @@ -832,15 +833,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1414 # number of replacements +system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index e8172a215..313988369 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442791 # Simulator instruction rate (inst/s) -host_op_rate 566092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 853689730 # Simulator tick rate (ticks/s) -host_mem_usage 250392 # Number of bytes of host memory used -host_seconds 615.96 # Real time elapsed on the host +host_inst_rate 414348 # Simulator instruction rate (inst/s) +host_op_rate 529728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 798851724 # Simulator tick rate (ticks/s) +host_mem_usage 248008 # Number of bytes of host memory used +host_seconds 658.24 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3976 # Tr system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 437248 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Tr system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index fb55fbe0e..669d3dfc7 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu sim_ticks 631883288500 # Number of ticks simulated final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129491 # Simulator instruction rate (inst/s) -host_op_rate 129491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44882876 # Simulator tick rate (ticks/s) -host_mem_usage 237188 # Number of bytes of host memory used -host_seconds 14078.49 # Real time elapsed on the host +host_inst_rate 177291 # Simulator instruction rate (inst/s) +host_op_rate 177291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61450789 # Simulator tick rate (ticks/s) +host_mem_usage 236780 # Number of bytes of host memory used +host_seconds 10282.75 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6776745 # To system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476114 # Total number of read requests seen -system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30471232 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis @@ -262,10 +263,10 @@ system.membus.trans_dist::ReadResp 409257 # Tr system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66856 # Transaction distribution system.membus.trans_dist::ReadExResp 66856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34753344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks) @@ -581,12 +582,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Tr system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3179865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 642816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 104827200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks) @@ -595,15 +596,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 15605000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8334 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 8334 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits @@ -679,19 +680,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443335 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 443335 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.040541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.956023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7293 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1053744 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits @@ -817,15 +818,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527799 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1527799 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 3b39f56f2..421623453 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu sim_ticks 2769739533000 # Number of ticks simulated final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1559352 # Simulator instruction rate (inst/s) -host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2149839105 # Simulator tick rate (ticks/s) -host_mem_usage 233980 # Number of bytes of host memory used -host_seconds 1288.35 # Real time elapsed on the host +host_inst_rate 892879 # Simulator instruction rate (inst/s) +host_op_rate 892879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1230989339 # Simulator tick rate (ticks/s) +host_mem_usage 233984 # Number of bytes of host memory used +host_seconds 2250.01 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408476 # Tr system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66873 # Transaction distribution system.membus.trans_dist::ReadExResp 66873 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34704448 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks) @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 9046 # number of replacements -system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9046 # number of replacements +system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442570 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 442570 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1526048 # number of replacements -system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1526048 # number of replacements +system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Tr system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 68bfe2c31..5f69a496c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu sim_ticks 640648369500 # Number of ticks simulated final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99606 # Simulator instruction rate (inst/s) -host_op_rate 135651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46095119 # Simulator tick rate (ticks/s) -host_mem_usage 254320 # Number of bytes of host memory used -host_seconds 13898.40 # Real time elapsed on the host +host_inst_rate 107808 # Simulator instruction rate (inst/s) +host_op_rate 146820 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49890421 # Simulator tick rate (ticks/s) +host_mem_usage 251704 # Number of bytes of host memory used +host_seconds 12841.11 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6603111 # To system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Total number of read requests seen -system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30399488 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis @@ -244,10 +245,10 @@ system.membus.trans_dist::UpgradeReq 4361 # Tr system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution system.membus.trans_dist::ReadExReq 66075 # Transaction distribution system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34629696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) @@ -576,12 +577,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) @@ -590,15 +591,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 43029998 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22329 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 22329 # number of replacements +system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits @@ -674,19 +675,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442208 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 442208 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits @@ -837,15 +838,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532805 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1532805 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index b119e8929..65ea4c6ca 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 575384 # Simulator instruction rate (inst/s) -host_op_rate 780549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 968736790 # Simulator tick rate (ticks/s) -host_mem_usage 250996 # Number of bytes of host memory used -host_seconds 2401.19 # Real time elapsed on the host +host_inst_rate 481372 # Simulator instruction rate (inst/s) +host_op_rate 653016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 810455855 # Simulator tick rate (ticks/s) +host_mem_usage 248632 # Number of bytes of host memory used +host_seconds 2870.14 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408063 # Tr system.membus.trans_dist::Writeback 66099 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34576320 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4652237184 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 18364 # number of replacements -system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 18364 # number of replacements +system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 441378 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 441378 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1529557 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1529557 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Tr system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index fc992598c..c7e2525ee 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.043769 # Nu sim_ticks 43769191000 # Number of ticks simulated final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112888 # Simulator instruction rate (inst/s) -host_op_rate 112888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55931443 # Simulator tick rate (ticks/s) -host_mem_usage 233228 # Number of bytes of host memory used -host_seconds 782.55 # Real time elapsed on the host +host_inst_rate 69144 # Simulator instruction rate (inst/s) +host_op_rate 69144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34257993 # Simulator tick rate (ticks/s) +host_mem_usage 232832 # Number of bytes of host memory used +host_seconds 1277.63 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 166688208 # To system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165515 # Total number of read requests seen -system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 10592960 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis @@ -311,10 +312,10 @@ system.membus.trans_dist::ReadResp 34625 # Tr system.membus.trans_dist::Writeback 113997 # Transaction distribution system.membus.trans_dist::ReadExReq 130890 # Transaction distribution system.membus.trans_dist::ReadExResp 130890 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) @@ -423,15 +424,15 @@ system.cpu.stage3.utilization 25.270124 # Pe system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 84371 # number of replacements +system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits @@ -513,12 +514,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Tr system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) @@ -527,19 +528,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 131178984 # La system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 131591 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits @@ -665,15 +666,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index a1c1e25d4..5b9e2998f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu sim_ticks 24977022500 # Number of ticks simulated final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130696 # Simulator instruction rate (inst/s) -host_op_rate 130696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41014411 # Simulator tick rate (ticks/s) -host_mem_usage 236320 # Number of bytes of host memory used -host_seconds 608.98 # Real time elapsed on the host +host_inst_rate 124025 # Simulator instruction rate (inst/s) +host_op_rate 124025 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38920856 # Simulator tick rate (ticks/s) +host_mem_usage 235900 # Number of bytes of host memory used +host_seconds 641.74 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 292149475 # To system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166305 # Total number of read requests seen -system.physmem.writeReqs 114016 # Total number of write requests seen -system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 10643520 # Total number of bytes read from memory system.physmem.bytesWritten 7297024 # Total number of bytes written to memory system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis @@ -309,10 +310,10 @@ system.membus.trans_dist::ReadResp 35508 # Tr system.membus.trans_dist::Writeback 114016 # Transaction distribution system.membus.trans_dist::ReadExReq 130797 # Transaction distribution system.membus.trans_dist::ReadExResp 130797 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17940544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) @@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Tr system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) @@ -642,15 +643,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 141571734 # La system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91227 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91227 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits @@ -726,19 +727,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 17000.812278 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132400 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 132400 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.805321 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.067817 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 85619 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 34304 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 119923 # number of ReadReq hits @@ -864,15 +865,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201470 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201470 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 060f66d07..bac018361 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671194 # Simulator instruction rate (inst/s) -host_op_rate 671194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1015328507 # Simulator tick rate (ticks/s) -host_mem_usage 233108 # Number of bytes of host memory used -host_seconds 131.62 # Real time elapsed on the host +host_inst_rate 775893 # Simulator instruction rate (inst/s) +host_op_rate 775893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173708198 # Simulator tick rate (ticks/s) +host_mem_usage 233104 # Number of bytes of host memory used +host_seconds 113.86 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 34272 # Tr system.membus.trans_dist::Writeback 113982 # Transaction distribution system.membus.trans_dist::ReadExReq 130881 # Transaction distribution system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17864640 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 131235 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 131235 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Tr system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8607c685b..06aaaa021 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu sim_ticks 26765004500 # Number of ticks simulated final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88779 # Simulator instruction rate (inst/s) -host_op_rate 125988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33510752 # Simulator tick rate (ticks/s) -host_mem_usage 255124 # Number of bytes of host memory used -host_seconds 798.70 # Real time elapsed on the host +host_inst_rate 102307 # Simulator instruction rate (inst/s) +host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38617115 # Simulator tick rate (ticks/s) +host_mem_usage 251228 # Number of bytes of host memory used +host_seconds 693.09 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 200715827 # To system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128790 # Total number of read requests seen -system.physmem.writeReqs 83940 # Total number of write requests seen -system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 8242496 # Total number of bytes read from memory system.physmem.bytesWritten 5372160 # Total number of bytes written to memory system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis @@ -313,10 +314,10 @@ system.membus.trans_dist::UpgradeReq 321 # Tr system.membus.trans_dist::UpgradeResp 321 # Transaction distribution system.membus.trans_dist::ReadExReq 102252 # Transaction distribution system.membus.trans_dist::ReadExResp 102252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 13614656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) @@ -645,12 +646,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) @@ -659,15 +660,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 47827231 # La system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28871 # number of replacements -system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 28871 # number of replacements +system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits @@ -743,19 +744,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95660 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 95660 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits @@ -910,15 +911,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158372 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 158372 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 170d172b3..178d6c7df 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 438025 # Simulator instruction rate (inst/s) -host_op_rate 621131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825892843 # Simulator tick rate (ticks/s) -host_mem_usage 249772 # Number of bytes of host memory used -host_seconds 160.66 # Real time elapsed on the host +host_inst_rate 525201 # Simulator instruction rate (inst/s) +host_op_rate 744748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 990262559 # Simulator tick rate (ticks/s) +host_mem_usage 247408 # Number of bytes of host memory used +host_seconds 133.99 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 25532 # Tr system.membus.trans_dist::Writeback 83909 # Transaction distribution system.membus.trans_dist::ReadExReq 102280 # Transaction distribution system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 13550144 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks) @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 94693 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Tr system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index df352064c..b5bc877a9 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu sim_ticks 202242260000 # Number of ticks simulated final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 840510 # Simulator instruction rate (inst/s) -host_op_rate 851393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1264790801 # Simulator tick rate (ticks/s) -host_mem_usage 241580 # Number of bytes of host memory used -host_seconds 159.90 # Real time elapsed on the host +host_inst_rate 788005 # Simulator instruction rate (inst/s) +host_op_rate 798208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1185781953 # Simulator tick rate (ticks/s) +host_mem_usage 240044 # Number of bytes of host memory used +host_seconds 170.56 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 30277 # Tr system.membus.trans_dist::Writeback 82868 # Transaction distribution system.membus.trans_dist::ReadExReq 101256 # Transaction distribution system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 13721664 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) @@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 98540 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits @@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -415,12 +415,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Tr system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index fe02977f3..b5eeb298e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.017017 # Nu sim_ticks 1017016979500 # Number of ticks simulated final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113008 # Simulator instruction rate (inst/s) -host_op_rate 113008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63156510 # Simulator tick rate (ticks/s) -host_mem_usage 225148 # Number of bytes of host memory used -host_seconds 16103.12 # Real time elapsed on the host +host_inst_rate 89946 # Simulator instruction rate (inst/s) +host_op_rate 89946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50268200 # Simulator tick rate (ticks/s) +host_mem_usage 224748 # Number of bytes of host memory used +host_seconds 20231.82 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 64065511 # To system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959691 # Total number of read requests seen -system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 125420224 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis @@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1178393 # Tr system.membus.trans_dist::Writeback 1018058 # Transaction distribution system.membus.trans_dist::ReadExReq 781298 # Transaction distribution system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575936 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) @@ -428,15 +429,15 @@ system.cpu.stage3.utilization 20.138673 # Pe system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits @@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21917899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 819557696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks) @@ -532,19 +533,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 1466500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1926960 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 1926960 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits @@ -667,15 +668,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107355 # number of replacements -system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107355 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index b939ad0cc..82bf88993 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu sim_ticks 694171131000 # Number of ticks simulated final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169313 # Simulator instruction rate (inst/s) -host_op_rate 169313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67701038 # Simulator tick rate (ticks/s) -host_mem_usage 228220 # Number of bytes of host memory used -host_seconds 10253.48 # Real time elapsed on the host +host_inst_rate 178600 # Simulator instruction rate (inst/s) +host_op_rate 178600 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71414604 # Simulator tick rate (ticks/s) +host_mem_usage 227828 # Number of bytes of host memory used +host_seconds 9720.30 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 94013475 # To system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966438 # Total number of read requests seen -system.physmem.writeReqs 1019710 # Total number of write requests seen -system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 1966438 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 1019710 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 1966438 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 1019710 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 125852032 # Total number of bytes read from memory system.physmem.bytesWritten 65261440 # Total number of bytes written to memory system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 561 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis @@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1191259 # Tr system.membus.trans_dist::Writeback 1019710 # Transaction distribution system.membus.trans_dist::ReadExReq 775179 # Transaction distribution system.membus.trans_dist::ReadExResp 775179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191113472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 191113472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) @@ -635,12 +636,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825936384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 825998016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) @@ -649,15 +650,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1633750 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits @@ -733,19 +734,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933728 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 1933728 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.445357 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000794 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6106292 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6106292 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3725037 # number of Writeback hits @@ -868,15 +869,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176123 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9176123 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 72597a7eb..27c712d4a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 781919 # Simulator instruction rate (inst/s) -host_op_rate 781919 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127211275 # Simulator tick rate (ticks/s) -host_mem_usage 225028 # Number of bytes of host memory used -host_seconds 2327.32 # Real time elapsed on the host +host_inst_rate 1731328 # Simulator instruction rate (inst/s) +host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2495874089 # Simulator tick rate (ticks/s) +host_mem_usage 225024 # Number of bytes of host memory used +host_seconds 1051.09 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1178362 # Tr system.membus.trans_dist::Writeback 1018077 # Transaction distribution system.membus.trans_dist::ReadExReq 781301 # Transaction distribution system.membus.trans_dist::ReadExResp 781301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575360 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926937 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 1926937 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3d9ea108c..f9e4efd28 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu sim_ticks 541686426500 # Number of ticks simulated final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161069 # Simulator instruction rate (inst/s) -host_op_rate 179684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56487595 # Simulator tick rate (ticks/s) -host_mem_usage 246340 # Number of bytes of host memory used -host_seconds 9589.48 # Real time elapsed on the host +host_inst_rate 146656 # Simulator instruction rate (inst/s) +host_op_rate 163606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51433162 # Simulator tick rate (ticks/s) +host_mem_usage 242412 # Number of bytes of host memory used +host_seconds 10531.85 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 130020847 # To system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246464 # Total number of read requests seen -system.physmem.writeReqs 1100477 # Total number of write requests seen -system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 143773696 # Total number of bytes read from memory system.physmem.bytesWritten 70430528 # Total number of bytes written to memory system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis @@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1420070 # Tr system.membus.trans_dist::Writeback 1100477 # Transaction distribution system.membus.trans_dist::ReadExReq 826393 # Transaction distribution system.membus.trans_dist::ReadExResp 826393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 214204160 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) @@ -644,12 +645,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) @@ -658,15 +659,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1321749 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 22 # number of replacements +system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits @@ -742,19 +743,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2213775 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 2213775 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits @@ -889,15 +890,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9598226 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9598226 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 991abe176..0ee21876c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1401168 # Simulator instruction rate (inst/s) -host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2177389973 # Simulator tick rate (ticks/s) -host_mem_usage 243008 # Number of bytes of host memory used -host_seconds 1098.20 # Real time elapsed on the host +host_inst_rate 594937 # Simulator instruction rate (inst/s) +host_op_rate 663956 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 924522029 # Simulator tick rate (ticks/s) +host_mem_usage 240640 # Number of bytes of host memory used +host_seconds 2586.42 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1177898 # Tr system.membus.trans_dist::Writeback 1017198 # Transaction distribution system.membus.trans_dist::ReadExReq 780876 # Transaction distribution system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190462208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 7 # number of replacements +system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 1926075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index cc029b4bd..776ec92d3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 548624 # Simulator instruction rate (inst/s) -host_op_rate 854806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072884756 # Simulator tick rate (ticks/s) -host_mem_usage 295308 # Number of bytes of host memory used -host_seconds 5482.96 # Real time elapsed on the host +host_inst_rate 645050 # Simulator instruction rate (inst/s) +host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1261455450 # Simulator tick rate (ticks/s) +host_mem_usage 245540 # Number of bytes of host memory used +host_seconds 4663.33 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 781295 # Tr system.membus.trans_dist::ReadExResp 781295 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190549120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926197 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 1926197 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -290,15 +288,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -396,12 +394,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Tr system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 9ab9303b1..5350fe782 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041672 # Nu sim_ticks 41671895000 # Number of ticks simulated final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84546 # Simulator instruction rate (inst/s) -host_op_rate 84546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38336000 # Simulator tick rate (ticks/s) -host_mem_usage 228812 # Number of bytes of host memory used -host_seconds 1087.02 # Real time elapsed on the host +host_inst_rate 101828 # Simulator instruction rate (inst/s) +host_op_rate 101828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46172411 # Simulator tick rate (ticks/s) +host_mem_usage 228672 # Number of bytes of host memory used +host_seconds 902.53 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 4291046 # In system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4938 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 316032 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis @@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3216 # Tr system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) @@ -351,15 +352,15 @@ system.cpu.stage3.utilization 21.629101 # Pe system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 7635 # number of replacements +system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits @@ -441,12 +442,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Tr system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 23593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 758400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) @@ -455,19 +456,19 @@ system.cpu.toL2Bus.respLayer0.occupancy 14868500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -591,15 +592,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b5b638e61..b7d057d9f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu sim_ticks 23492267500 # Number of ticks simulated final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122951 # Simulator instruction rate (inst/s) -host_op_rate 122951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34312389 # Simulator tick rate (ticks/s) -host_mem_usage 231868 # Number of bytes of host memory used -host_seconds 684.66 # Real time elapsed on the host +host_inst_rate 120531 # Simulator instruction rate (inst/s) +host_op_rate 120531 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33636905 # Simulator tick rate (ticks/s) +host_mem_usage 231740 # Number of bytes of host memory used +host_seconds 698.41 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 8339084 # In system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 334464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis @@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3520 # Tr system.membus.trans_dist::ReadResp 3520 # Transaction distribution system.membus.trans_dist::ReadExReq 1706 # Transaction distribution system.membus.trans_dist::ReadExResp 1706 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334464 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) @@ -557,12 +558,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Tr system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) @@ -571,15 +572,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 17871250 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9559 # number of replacements -system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9559 # number of replacements +system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits @@ -655,19 +656,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.679636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061269 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8431 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8486 # number of ReadReq hits @@ -791,15 +792,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 847011ac3..be0605d18 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 852211 # Simulator instruction rate (inst/s) -host_op_rate 852211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1100968725 # Simulator tick rate (ticks/s) +host_inst_rate 2022504 # Simulator instruction rate (inst/s) +host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2612866318 # Simulator tick rate (ticks/s) host_mem_usage 228676 # Number of bytes of host memory used -host_seconds 107.84 # Real time elapsed on the host +host_seconds 45.44 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3043 # Tr system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 304960 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Tr system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 191849c1b..cd02e0594 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu sim_ticks 74201024500 # Number of ticks simulated final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81530 # Simulator instruction rate (inst/s) -host_op_rate 89268 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35110326 # Simulator tick rate (ticks/s) -host_mem_usage 249620 # Number of bytes of host memory used -host_seconds 2113.37 # Real time elapsed on the host +host_inst_rate 88798 # Simulator instruction rate (inst/s) +host_op_rate 97225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38240010 # Simulator tick rate (ticks/s) +host_mem_usage 245976 # Number of bytes of host memory used +host_seconds 1940.40 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1769895 # In system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3801 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 243200 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis @@ -238,10 +239,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 1075 # Transaction distribution system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 243200 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) @@ -571,12 +572,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) @@ -585,15 +586,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 6609745 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2391 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2391 # number of replacements +system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits @@ -669,19 +670,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043428 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits @@ -828,15 +829,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 371d1c275..3a3e9e512 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1198657 # Simulator instruction rate (inst/s) -host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618778979 # Simulator tick rate (ticks/s) -host_mem_usage 245268 # Number of bytes of host memory used -host_seconds 143.36 # Real time elapsed on the host +host_inst_rate 705973 # Simulator instruction rate (inst/s) +host_op_rate 773116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 953412259 # Simulator tick rate (ticks/s) +host_mem_usage 242928 # Number of bytes of host memory used +host_seconds 243.41 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 2361 # Tr system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 220992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Tr system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 6ce379f53..471075dde 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942019 # Simulator instruction rate (inst/s) -host_op_rate 942020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1317563963 # Simulator tick rate (ticks/s) -host_mem_usage 238020 # Number of bytes of host memory used -host_seconds 205.35 # Real time elapsed on the host +host_inst_rate 872463 # Simulator instruction rate (inst/s) +host_op_rate 872464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220278409 # Simulator tick rate (ticks/s) +host_mem_usage 236504 # Number of bytes of host memory used +host_seconds 221.72 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4095 # Tr system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 331072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -400,12 +400,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2e8d78059..53040adf9 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144471 # Nu sim_ticks 144470654000 # Number of ticks simulated final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76550 # Simulator instruction rate (inst/s) -host_op_rate 128304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83736451 # Simulator tick rate (ticks/s) -host_mem_usage 279024 # Number of bytes of host memory used -host_seconds 1725.30 # Real time elapsed on the host +host_inst_rate 75912 # Simulator instruction rate (inst/s) +host_op_rate 127236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83039301 # Simulator tick rate (ticks/s) +host_mem_usage 277792 # Number of bytes of host memory used +host_seconds 1739.79 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1500429 # In system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5340 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 341760 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis @@ -242,11 +243,9 @@ system.membus.trans_dist::ReadExReq 1530 # Tr system.membus.trans_dist::ReadExResp 1530 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 341696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -531,12 +530,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks) @@ -545,15 +544,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 10832250 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4654 # number of replacements -system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4654 # number of replacements +system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits @@ -629,19 +628,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067843 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.009533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3232 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3270 # number of ReadReq hits @@ -781,15 +780,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 8e5c309b6..2ebeaa506 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 679792 # Simulator instruction rate (inst/s) -host_op_rate 1139391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1291700674 # Simulator tick rate (ticks/s) -host_mem_usage 272716 # Number of bytes of host memory used -host_seconds 194.28 # Real time elapsed on the host +host_inst_rate 352771 # Simulator instruction rate (inst/s) +host_op_rate 591275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 670313887 # Simulator tick rate (ticks/s) +host_mem_usage 270496 # Number of bytes of host memory used +host_seconds 374.38 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362963 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 1575 # Tr system.membus.trans_dist::ReadExResp 1575 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 303040 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -69,15 +67,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -147,19 +145,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -283,15 +281,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits @@ -389,12 +387,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Tr system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 59af5be58..101a67dc8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1416644 # To system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7cff7197d..ee54d11d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 469015 # To system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 900001468..b46274bd4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.961841 # Nu sim_ticks 1961841175000 # Number of ticks simulated final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1094895 # Simulator instruction rate (inst/s) -host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36191186298 # Simulator tick rate (ticks/s) -host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 54.21 # Real time elapsed on the host +host_inst_rate 1272238 # Simulator instruction rate (inst/s) +host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42053157352 # Simulator tick rate (ticks/s) +host_mem_usage 308880 # Number of bytes of host memory used +host_seconds 46.65 # Real time elapsed on the host sim_insts 59351715 # Number of instructions simulated sim_ops 59351715 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory @@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1351188 # To system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests seen -system.physmem.writeReqs 121037 # Total number of write requests seen -system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28716928 # Total number of bytes read from memory system.physmem.bytesWritten 7746368 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis @@ -332,16 +333,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36531890 # Total data (bytes) system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) @@ -353,23 +350,23 @@ system.membus.respLayer1.occupancy 3812357322 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy +system.l2c.tags.replacements 341780 # number of replacements +system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use +system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits @@ -652,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -941,16 +938,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 894 # Tr system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 205232754 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) @@ -985,19 +982,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) @@ -1014,19 +998,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2730242 # Total data (bytes) system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) @@ -1059,15 +1030,15 @@ system.iobus.respLayer0.occupancy 26795000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 920572 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits @@ -1137,15 +1108,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 1349865 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits @@ -1411,15 +1382,15 @@ system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # nu system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 79630 # number of replacements +system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits @@ -1489,15 +1460,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 40890 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index fef6394c6..0de871519 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.918473 # Nu sim_ticks 1918473094000 # Number of ticks simulated final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 813863 # Simulator instruction rate (inst/s) -host_op_rate 813863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27788392408 # Simulator tick rate (ticks/s) -host_mem_usage 306196 # Number of bytes of host memory used -host_seconds 69.04 # Real time elapsed on the host +host_inst_rate 948634 # Simulator instruction rate (inst/s) +host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32389976926 # Simulator tick rate (ticks/s) +host_mem_usage 304780 # Number of bytes of host memory used +host_seconds 59.23 # Real time elapsed on the host sim_insts 56188014 # Number of instructions simulated sim_ops 56188014 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory @@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 443419 # To system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests seen -system.physmem.writeReqs 115467 # Total number of write requests seen -system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28350528 # Total number of bytes read from memory system.physmem.bytesWritten 7389888 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis @@ -329,16 +330,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 8 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 35784972 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) @@ -350,15 +347,15 @@ system.membus.respLayer1.occupancy 3745756604 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -644,19 +641,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) @@ -673,19 +657,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2706164 # Total data (bytes) system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) @@ -718,15 +689,15 @@ system.iobus.respLayer0.occupancy 23509000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928665 # number of replacements +system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits @@ -796,19 +767,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336065 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 336065 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits @@ -966,15 +937,15 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1390866 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits @@ -1112,12 +1083,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 29541c768..ee810dcc9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -66,14 +66,15 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 486d98045..44e286527 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -49,14 +49,15 @@ system.physmem.bw_total::cpu.itb.walker 82 # To system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 7e08761d9..643b5e070 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,147 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194911 # Number of seconds simulated -sim_ticks 1194911360500 # Number of ticks simulated -final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194884 # Number of seconds simulated +sim_ticks 1194883580500 # Number of ticks simulated +final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 773513 # Simulator instruction rate (inst/s) -host_op_rate 985724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15060857671 # Simulator tick rate (ticks/s) -host_mem_usage 403580 # Number of bytes of host memory used -host_seconds 79.34 # Real time elapsed on the host -sim_insts 61369589 # Number of instructions simulated -sim_ops 78206230 # Number of ops (including micro ops) simulated +host_inst_rate 298011 # Simulator instruction rate (inst/s) +host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5802481089 # Simulator tick rate (ticks/s) +host_mem_usage 399660 # Number of bytes of host memory used +host_seconds 205.93 # Real time elapsed on the host +sim_insts 61368273 # Number of instructions simulated +sim_ops 78202205 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654636 # Total number of read requests seen -system.physmem.writeReqs 821470 # Total number of write requests seen -system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425896704 # Total number of bytes read from memory -system.physmem.bytesWritten 52574080 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed +system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 425896384 # Total number of bytes read from memory +system.physmem.bytesWritten 52573888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194906959500 # Total gap between requests +system.physmem.totGap 1194879167500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159747 # Categorize read packet sizes +system.physmem.readPktSize::6 159742 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64634 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64631 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,31 +157,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -188,302 +189,282 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 3 0.01% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 5 0.01% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 8 0.02% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 3 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation -system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests -system.physmem.totBusLat 33272490000 # Total cycles spent in databus access -system.physmem.totBankLat 8550726250 # Total cycles spent in bank access -system.physmem.avgQLat 19957.54 # Average queueing delay per request -system.physmem.avgBankLat 1284.95 # Average bank access latency per request +system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation +system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests +system.physmem.totBusLat 33270500000 # Total cycles spent in databus access +system.physmem.totBankLat 8590725000 # Total cycles spent in bank access +system.physmem.avgQLat 19013.79 # Average queueing delay per request +system.physmem.avgBankLat 1291.04 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26242.50 # Average memory access latency +system.physmem.avgMemAccLat 25304.84 # Average memory access latency system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 11.97 # Average write queue length over time -system.physmem.readRowHits 6636574 # Number of row buffer hits during reads -system.physmem.writeRowHits 804724 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 14.04 # Average write queue length over time +system.physmem.readRowHits 6636405 # Number of row buffer hits during reads +system.physmem.writeRowHits 97666 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes -system.physmem.avgGap 159830.13 # Average gap between requests +system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes +system.physmem.avgGap 159826.58 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -502,298 +483,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60028739 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703151 # Transaction distribution -system.membus.trans_dist::ReadResp 7703151 # Transaction distribution -system.membus.trans_dist::WriteReq 767201 # Transaction distribution -system.membus.trans_dist::WriteResp 767201 # Transaction distribution -system.membus.trans_dist::Writeback 64634 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution -system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.throughput 60029719 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703148 # Transaction distribution +system.membus.trans_dist::ReadResp 7703148 # Transaction distribution +system.membus.trans_dist::WriteReq 767203 # Transaction distribution +system.membus.trans_dist::WriteResp 767203 # Transaction distribution +system.membus.trans_dist::Writeback 64631 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution +system.membus.trans_dist::ReadExReq 137763 # Transaction distribution system.membus.trans_dist::ReadExResp 137302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71729022 # Total data (bytes) +system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728526 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69629 # number of replacements -system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use -system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40041.185718 # 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average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -975,62 +944,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118431561 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137209194 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks) +system.toL2Bus.throughput 118384606 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137140510 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45438010 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution +system.iobus.throughput 45439063 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1052,36 +1021,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1103,38 +1048,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294394 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294390 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1180,15 +1101,15 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9651794 # DTB read hits -system.cpu0.dtb.read_misses 3741 # DTB read misses -system.cpu0.dtb.write_hits 7596285 # DTB write hits +system.cpu0.dtb.read_hits 9653247 # DTB read hits +system.cpu0.dtb.read_misses 3738 # DTB read misses +system.cpu0.dtb.write_hits 7597488 # DTB write hits system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1196,16 +1117,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9655535 # DTB read accesses -system.cpu0.dtb.write_accesses 7597870 # DTB write accesses +system.cpu0.dtb.read_accesses 9656985 # DTB read accesses +system.cpu0.dtb.write_accesses 7599073 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17248079 # DTB hits -system.cpu0.dtb.misses 5326 # DTB misses -system.cpu0.dtb.accesses 17253405 # DTB accesses -system.cpu0.itb.inst_hits 43295611 # ITB inst hits +system.cpu0.dtb.hits 17250735 # DTB hits +system.cpu0.dtb.misses 5323 # DTB misses +system.cpu0.dtb.accesses 17256058 # DTB accesses +system.cpu0.itb.inst_hits 43297764 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1222,79 +1143,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses -system.cpu0.itb.hits 43295611 # DTB hits +system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses +system.cpu0.itb.hits 43297764 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43297816 # DTB accesses -system.cpu0.numCycles 2389822721 # number of cpu cycles simulated +system.cpu0.itb.accesses 43299969 # DTB accesses +system.cpu0.numCycles 2389767161 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42568710 # Number of instructions committed -system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses +system.cpu0.committedInsts 42570861 # Number of instructions committed +system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403445 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48055390 # number of integer instructions +system.cpu0.num_func_calls 1403492 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48060351 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18017454 # number of memory refs -system.cpu0.num_load_insts 10035613 # Number of load instructions -system.cpu0.num_store_insts 7981841 # Number of store instructions -system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles -system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles +system.cpu0.num_mem_refs 18020156 # number of memory refs +system.cpu0.num_load_insts 10037111 # Number of load instructions +system.cpu0.num_store_insts 7983045 # Number of store instructions +system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles +system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490004 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits -system.cpu0.icache.overall_hits::total 42805077 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses -system.cpu0.icache.overall_misses::total 490517 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency +system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490078 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits +system.cpu0.icache.overall_hits::total 42807156 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses +system.cpu0.icache.overall_misses::total 490591 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1303,120 +1224,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 406612 # number of replacements -system.cpu0.dcache.tags.tagsinuse 470.882465 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 15965290 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 407124 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6493762 # 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average overall miss latency +system.cpu0.dcache.tags.replacements 406634 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # 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number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # 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miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1425,66 +1346,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks -system.cpu0.dcache.writebacks::total 376581 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263761 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3349960502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7149928209 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7149928209 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78594000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78594000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25787113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25787113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks +system.cpu0.dcache.writebacks::total 376568 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1494,26 +1415,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5707792 # DTB read hits -system.cpu1.dtb.read_misses 3579 # DTB read misses -system.cpu1.dtb.write_hits 3874264 # DTB write hits -system.cpu1.dtb.write_misses 643 # DTB write misses +system.cpu1.dtb.read_hits 5705173 # DTB read hits +system.cpu1.dtb.read_misses 3576 # DTB read misses +system.cpu1.dtb.write_hits 3872049 # DTB write hits +system.cpu1.dtb.write_misses 645 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5711371 # DTB read accesses -system.cpu1.dtb.write_accesses 3874907 # DTB write accesses +system.cpu1.dtb.read_accesses 5708749 # DTB read accesses +system.cpu1.dtb.write_accesses 3872694 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9582056 # DTB hits -system.cpu1.dtb.misses 4222 # DTB misses -system.cpu1.dtb.accesses 9586278 # DTB accesses -system.cpu1.itb.inst_hits 19381456 # ITB inst hits +system.cpu1.dtb.hits 9577222 # DTB hits +system.cpu1.dtb.misses 4221 # DTB misses +system.cpu1.dtb.accesses 9581443 # DTB accesses +system.cpu1.itb.inst_hits 19377969 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1530,79 +1451,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses -system.cpu1.itb.hits 19381456 # DTB hits +system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses +system.cpu1.itb.hits 19377969 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19383627 # DTB accesses -system.cpu1.numCycles 2388389320 # number of cpu cycles simulated +system.cpu1.itb.accesses 19380140 # DTB accesses +system.cpu1.numCycles 2388332817 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18800879 # Number of instructions committed -system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses +system.cpu1.committedInsts 18797412 # Number of instructions committed +system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22271769 # number of integer instructions +system.cpu1.num_func_calls 796668 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22263010 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10017504 # number of memory refs -system.cpu1.num_load_insts 5984439 # Number of load instructions -system.cpu1.num_store_insts 4033065 # Number of store instructions -system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles -system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles +system.cpu1.num_mem_refs 10012651 # number of memory refs +system.cpu1.num_load_insts 5981805 # Number of load instructions +system.cpu1.num_store_insts 4030846 # Number of store instructions +system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles +system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376544 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927614 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19004396 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19004396 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19004396 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19004396 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19004396 # number of overall hits -system.cpu1.icache.overall_hits::total 19004396 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377056 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377056 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377056 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377056 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377056 # number of overall misses -system.cpu1.icache.overall_misses::total 377056 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154731460 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5154731460 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5154731460 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5154731460 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5154731460 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5154731460 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19381452 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19381452 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19381452 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19381452 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19381452 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19381452 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019454 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019454 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019454 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019454 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019454 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019454 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13670.997040 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13670.997040 # average overall miss latency +system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376539 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits +system.cpu1.icache.overall_hits::total 19000914 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses +system.cpu1.icache.overall_misses::total 377051 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1611,120 +1532,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377056 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377056 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377056 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377056 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377056 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377056 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398633040 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398633040 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398633040 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4398633040 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398633040 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4398633040 # 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average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks -system.cpu1.dcache.writebacks::total 200060 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133951 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133951 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112879 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112879 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks +system.cpu1.dcache.writebacks::total 199438 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1800,12 +1721,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1814,10 +1735,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 955e513bb..efd49eb78 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615733 # Number of seconds simulated -sim_ticks 2615733285000 # Number of ticks simulated -final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615716 # Number of seconds simulated +sim_ticks 2615716222000 # Number of ticks simulated +final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250012 # Simulator instruction rate (inst/s) -host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10863402189 # Simulator tick rate (ticks/s) -host_mem_usage 396412 # Number of bytes of host memory used -host_seconds 240.78 # Real time elapsed on the host -sim_insts 60198861 # Number of instructions simulated -sim_ops 76605713 # Number of ops (including micro ops) simulated +host_inst_rate 250038 # Simulator instruction rate (inst/s) +host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10864403710 # Simulator tick rate (ticks/s) +host_mem_usage 394540 # Number of bytes of host memory used +host_seconds 240.76 # Real time elapsed on the host +sim_insts 60199078 # Number of instructions simulated +sim_ops 76605946 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory -system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494770 # Total number of read requests seen -system.physmem.writeReqs 811989 # Total number of write requests seen -system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991665280 # Total number of bytes read from memory +system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 991665344 # Total number of bytes read from memory system.physmem.bytesWritten 51967296 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615728912000 # Total gap between requests +system.physmem.totGap 2615711849000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152694 # Categorize read packet sizes +system.physmem.readPktSize::6 152695 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes @@ -107,23 +108,23 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 57971 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,346 +140,300 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation -system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests -system.physmem.totBusLat 77472355000 # Total cycles spent in databus access -system.physmem.totBankLat 16272657500 # Total cycles spent in bank access -system.physmem.avgQLat 19568.21 # Average queueing delay per request -system.physmem.avgBankLat 1050.22 # Average bank access latency per request +system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation +system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests +system.physmem.totBusLat 77465575000 # Total cycles spent in databus access +system.physmem.totBankLat 16358058750 # Total cycles spent in bank access +system.physmem.avgQLat 19154.87 # Average queueing delay per request +system.physmem.avgBankLat 1055.83 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25618.44 # Average memory access latency +system.physmem.avgMemAccLat 25210.70 # Average memory access latency system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s @@ -486,12 +441,12 @@ system.physmem.avgConsumedWrBW 2.57 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.84 # Average write queue length over time -system.physmem.readRowHits 15469547 # Number of row buffer hits during reads -system.physmem.writeRowHits 798405 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.76 # Average write queue length over time +system.physmem.readRowHits 15468398 # Number of row buffer hits during reads +system.physmem.writeRowHits 93875 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes -system.physmem.avgGap 160407.65 # Average gap between requests +system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes +system.physmem.avgGap 160406.60 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -504,9 +459,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54136540 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546595 # Transaction distribution -system.membus.trans_dist::ReadResp 16546595 # Transaction distribution +system.membus.throughput 54136917 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546596 # Transaction distribution +system.membus.trans_dist::ReadResp 16546596 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution system.membus.trans_dist::Writeback 57971 # Transaction distribution @@ -516,47 +471,37 @@ system.membus.trans_dist::ReadExReq 132250 # Tr system.membus.trans_dist::ReadExResp 132250 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141606749 # Total data (bytes) +system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141606813 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -564,7 +509,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47815955 # Throughput (bytes/s) +system.iobus.throughput 47816267 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution @@ -595,30 +540,6 @@ system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 1 system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) @@ -646,30 +567,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 125073785 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) @@ -722,30 +619,30 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996132 # DTB read hits -system.cpu.dtb.read_misses 7340 # DTB read misses -system.cpu.dtb.write_hits 11230462 # DTB write hits -system.cpu.dtb.write_misses 2218 # DTB write misses +system.cpu.dtb.read_hits 14996146 # DTB read hits +system.cpu.dtb.read_misses 7341 # DTB read misses +system.cpu.dtb.write_hits 11230467 # DTB write hits +system.cpu.dtb.write_misses 2217 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003472 # DTB read accesses -system.cpu.dtb.write_accesses 11232680 # DTB write accesses +system.cpu.dtb.read_accesses 15003487 # DTB read accesses +system.cpu.dtb.write_accesses 11232684 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226594 # DTB hits +system.cpu.dtb.hits 26226613 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236152 # DTB accesses -system.cpu.itb.inst_hits 61492700 # ITB inst hits +system.cpu.dtb.accesses 26236171 # DTB accesses +system.cpu.itb.inst_hits 61492923 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -762,79 +659,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61497171 # ITB inst accesses -system.cpu.itb.hits 61492700 # DTB hits +system.cpu.itb.inst_accesses 61497394 # ITB inst accesses +system.cpu.itb.hits 61492923 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61497171 # DTB accesses -system.cpu.numCycles 5231466570 # number of cpu cycles simulated +system.cpu.itb.accesses 61497394 # DTB accesses +system.cpu.numCycles 5231432444 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60198861 # Number of instructions committed -system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses +system.cpu.committedInsts 60199078 # Number of instructions committed +system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140458 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872503 # number of integer instructions +system.cpu.num_func_calls 2140465 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872726 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read -system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written +system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read +system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394052 # number of memory refs -system.cpu.num_load_insts 15660178 # Number of load instructions -system.cpu.num_store_insts 11733874 # Number of store instructions -system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875848 # Percentage of idle cycles +system.cpu.num_mem_refs 27394080 # number of memory refs +system.cpu.num_load_insts 15660200 # Number of load instructions +system.cpu.num_store_insts 11733880 # Number of store instructions +system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875855 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856294 # number of replacements -system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits -system.cpu.icache.overall_hits::total 60635894 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses -system.cpu.icache.overall_misses::total 856806 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1114,79 +1011,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626803 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits +system.cpu.dcache.tags.replacements 626805 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195774 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 618715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618715 # number of overall misses +system.cpu.dcache.overall_misses::total 618715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5384538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1195,54 +1092,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks -system.cpu.dcache.writebacks::total 595786 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # 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number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1250,44 +1147,44 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution +system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1296,10 +1193,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b5f8111f8..31f47079e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 662335 # Simulator instruction rate (inst/s) -host_op_rate 851722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25577480180 # Simulator tick rate (ticks/s) -host_mem_usage 396424 # Number of bytes of host memory used -host_seconds 91.21 # Real time elapsed on the host +host_inst_rate 691261 # Simulator instruction rate (inst/s) +host_op_rate 888919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26694508777 # Simulator tick rate (ticks/s) +host_mem_usage 395580 # Number of bytes of host memory used +host_seconds 87.39 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -62,14 +62,15 @@ system.physmem.bw_total::cpu0.data 3386724 # To system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -223,27 +224,27 @@ system.realview.nvmem.bw_total::total 9 # To system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use -system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.replacements 62242 # number of replacements +system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -450,23 +451,23 @@ system.cpu0.num_fp_register_writes 1428 # nu system.cpu0.num_mem_refs 15013057 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles -system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles -system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles +system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles +system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles +system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 850590 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -512,17 +513,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623334 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -660,18 +661,18 @@ system.cpu1.num_fp_register_writes 1352 # nu system.cpu1.num_mem_refs 12348580 # number of memory refs system.cpu1.num_load_insts 7334866 # Number of load instructions system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles -system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles -system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles +system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles +system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 56bd99bdd..4e0947e27 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112102 # Nu sim_ticks 5112102211000 # Number of ticks simulated final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 878832 # Simulator instruction rate (inst/s) -host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22473674513 # Simulator tick rate (ticks/s) -host_mem_usage 586256 # Number of bytes of host memory used -host_seconds 227.47 # Real time elapsed on the host +host_inst_rate 856407 # Simulator instruction rate (inst/s) +host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21900233108 # Simulator tick rate (ticks/s) +host_mem_usage 584104 # Number of bytes of host memory used +host_seconds 233.43 # Real time elapsed on the host sim_insts 199908396 # Number of instructions simulated sim_ops 409304707 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory @@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 63 # To system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -195,15 +196,15 @@ system.physmem.avgGap nan # Av system.membus.throughput 9632725 # Throughput (bytes/s) system.membus.data_through_bus 49243475 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -277,15 +278,15 @@ system.cpu.not_idle_fraction 0.044374 # Pe system.cpu.idle_fraction 0.955626 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 790522 # number of replacements +system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits @@ -320,10 +321,10 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy @@ -368,10 +369,10 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526 system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy @@ -411,15 +412,15 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622027 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1622027 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits @@ -466,23 +467,23 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) -system.cpu.l2cache.tags.replacements 105931 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 105931 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index bb1dca70a..c9dd91320 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.196173 # Nu sim_ticks 5196173457000 # Number of ticks simulated final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766970 # Simulator instruction rate (inst/s) -host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31067837744 # Simulator tick rate (ticks/s) -host_mem_usage 586132 # Number of bytes of host memory used -host_seconds 167.25 # Real time elapsed on the host +host_inst_rate 457062 # Simulator instruction rate (inst/s) +host_op_rate 881101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18514311716 # Simulator tick rate (ticks/s) +host_mem_usage 585140 # Number of bytes of host memory used +host_seconds 280.66 # Real time elapsed on the host sim_insts 128277551 # Number of instructions simulated sim_ops 247287193 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory @@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198391 # Total number of read requests seen -system.physmem.writeReqs 126842 # Total number of write requests seen -system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 198391 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 126842 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 198391 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 126842 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 12697024 # Total number of bytes read from memory system.physmem.bytesWritten 8117888 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis @@ -358,39 +359,31 @@ system.membus.trans_dist::MessageReq 1655 # Tr system.membus.trans_dist::MessageResp 1655 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 22488073 # Total data (bytes) system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 256571500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359320500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1351024000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -532,26 +525,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) @@ -576,26 +549,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 3280192 # Total data (bytes) system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks) @@ -1032,16 +985,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9728f1e09..dde2aed4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 25046000 # Number of ticks simulated final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25238 # Simulator instruction rate (inst/s) -host_op_rate 25236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98905790 # Simulator tick rate (ticks/s) -host_mem_usage 225424 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 22373 # Simulator instruction rate (inst/s) +host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87684145 # Simulator tick rate (ticks/s) +host_mem_usage 225308 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 766589475 # In system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 29952 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 396 # Tr system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 937 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) @@ -307,15 +308,15 @@ system.cpu.stage3.utilization 2.663047 # Pe system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -396,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) @@ -410,17 +411,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 512750 # La system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -535,15 +536,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 38483afa5..60f469d0d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20671000 # Number of ticks simulated final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25591 # Simulator instruction rate (inst/s) -host_op_rate 25589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83008053 # Simulator tick rate (ticks/s) -host_mem_usage 227468 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 24570 # Simulator instruction rate (inst/s) +host_op_rate 24568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79697022 # Simulator tick rate (ticks/s) +host_mem_usage 227340 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 969087127 # In system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 31168 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 415 # Tr system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 975 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) @@ -511,12 +512,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 416 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) @@ -525,15 +526,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 531250 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits @@ -609,17 +610,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -734,15 +735,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2ce4c669d..6038d0a3c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19861 # Simulator instruction rate (inst/s) -host_op_rate 19860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101141711 # Simulator tick rate (ticks/s) -host_mem_usage 224276 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 27670 # Simulator instruction rate (inst/s) +host_op_rate 27667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140894748 # Simulator tick rate (ticks/s) +host_mem_usage 224272 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 373 # Tr system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -403,12 +403,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 374 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 07e82d1ad..746096984 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11933500 # Number of ticks simulated final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492 # Simulator instruction rate (inst/s) -host_op_rate 492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2461163 # Simulator tick rate (ticks/s) -host_mem_usage 226156 # Number of bytes of host memory used -host_seconds 4.85 # Real time elapsed on the host +host_inst_rate 64 # Simulator instruction rate (inst/s) +host_op_rate 64 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321705 # Simulator tick rate (ticks/s) +host_mem_usage 226036 # Number of bytes of host memory used +host_seconds 37.09 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1008254075 # In system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 17472 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis @@ -190,10 +191,10 @@ system.membus.trans_dist::ReadReq 249 # Tr system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 546 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 546 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) @@ -507,12 +508,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 249 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) @@ -521,15 +522,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 318000 # La system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits @@ -605,17 +606,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -724,15 +725,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 034aea3e9..0eefef01d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252355 # Simulator instruction rate (inst/s) -host_op_rate 251860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611932908 # Simulator tick rate (ticks/s) -host_mem_usage 223992 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 70 # Simulator instruction rate (inst/s) +host_op_rate 70 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446596 # Simulator tick rate (ticks/s) +host_mem_usage 222964 # Number of bytes of host memory used +host_seconds 37.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 218 # Tr system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 490 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15680 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 218 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 22dbcae6d..81f115ce9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31208 # Simulator instruction rate (inst/s) -host_op_rate 38937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112083077 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 32065 # Simulator instruction rate (inst/s) +host_op_rate 40006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115159682 # Simulator tick rate (ticks/s) +host_mem_usage 240696 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) @@ -563,12 +564,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) @@ -577,15 +578,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits @@ -661,17 +662,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -795,15 +796,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 3ccfc050f..ace16d792 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66928 # Simulator instruction rate (inst/s) -host_op_rate 83502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 240363471 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 36590 # Simulator instruction rate (inst/s) +host_op_rate 45651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131406771 # Simulator tick rate (ticks/s) +host_mem_usage 240696 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) @@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) @@ -532,15 +533,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 485250 # La system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits @@ -616,17 +617,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -750,15 +751,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 7a58b161f..13e2763d6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220478 # Simulator instruction rate (inst/s) -host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1251201624 # Simulator tick rate (ticks/s) -host_mem_usage 241012 # Number of bytes of host memory used +host_inst_rate 229244 # Simulator instruction rate (inst/s) +host_op_rate 284503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1301168988 # Simulator tick rate (ticks/s) +host_mem_usage 238660 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 307 # Tr system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 22400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits @@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 339 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index b2a150376..aeb0e2e25 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24587000 # Number of ticks simulated final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41260 # Simulator instruction rate (inst/s) -host_op_rate 41253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174426700 # Simulator tick rate (ticks/s) -host_mem_usage 226212 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 52979 # Simulator instruction rate (inst/s) +host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223940501 # Simulator tick rate (ticks/s) +host_mem_usage 224928 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 825151503 # In system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 29120 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 404 # Tr system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 910 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) @@ -293,15 +294,15 @@ system.cpu.stage3.utilization 2.517539 # Pe system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -382,12 +383,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) @@ -396,17 +397,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 543000 # La system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -521,15 +522,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 6a930873f..f0a85d261 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21805500 # Number of ticks simulated final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79844 # Simulator instruction rate (inst/s) -host_op_rate 79828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337538221 # Simulator tick rate (ticks/s) -host_mem_usage 228256 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 44396 # Simulator instruction rate (inst/s) +host_op_rate 44386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187676879 # Simulator tick rate (ticks/s) +host_mem_usage 228012 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 983238174 # In system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30528 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 426 # Tr system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) @@ -495,12 +496,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 429 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) @@ -509,15 +510,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 573500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits @@ -593,17 +594,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -718,15 +719,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index bfb8470a6..d3256ea4d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482351 # Simulator instruction rate (inst/s) -host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2613274672 # Simulator tick rate (ticks/s) -host_mem_usage 225064 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 304637 # Simulator instruction rate (inst/s) +host_op_rate 304230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1653175117 # Simulator tick rate (ticks/s) +host_mem_usage 224940 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 388 # Tr system.membus.trans_dist::ReadResp 388 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28096 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) @@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -389,12 +389,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 390 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 50311c18c..9bd3a3844 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18469500 # Number of ticks simulated final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54927 # Simulator instruction rate (inst/s) -host_op_rate 54916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175080000 # Simulator tick rate (ticks/s) -host_mem_usage 224296 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 100626 # Simulator instruction rate (inst/s) +host_op_rate 100602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 320728752 # Simulator tick rate (ticks/s) +host_mem_usage 223260 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1195484447 # In system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28544 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 399 # Tr system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) @@ -493,12 +494,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) @@ -507,15 +508,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 590750 # La system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -591,17 +592,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -719,15 +720,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 6e991864c..68c96c714 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20802500 # Number of ticks simulated final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39959 # Simulator instruction rate (inst/s) -host_op_rate 39952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155990706 # Simulator tick rate (ticks/s) -host_mem_usage 232536 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 86492 # Simulator instruction rate (inst/s) +host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337526822 # Simulator tick rate (ticks/s) +host_mem_usage 231936 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 889123903 # In system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 27072 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 342 # Tr system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 846 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) @@ -275,15 +276,15 @@ system.cpu.stage3.utilization 2.343412 # Pe system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 345 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) @@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 489750 # La system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -506,15 +507,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index c4b2117ab..b76f909df 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413138 # Simulator instruction rate (inst/s) -host_op_rate 412367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2148212772 # Simulator tick rate (ticks/s) -host_mem_usage 231400 # Number of bytes of host memory used +host_inst_rate 441877 # Simulator instruction rate (inst/s) +host_op_rate 441389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2300957264 # Simulator tick rate (ticks/s) +host_mem_usage 230904 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 308 # Tr system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 778 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 24896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -374,12 +374,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 311 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 7c9257554..cfacb8ad4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19639500 # Number of ticks simulated final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28578 # Simulator instruction rate (inst/s) -host_op_rate 51768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104294046 # Simulator tick rate (ticks/s) -host_mem_usage 245432 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 30549 # Simulator instruction rate (inst/s) +host_op_rate 55338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111488682 # Simulator tick rate (ticks/s) +host_mem_usage 243516 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 892894422 # In system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 26624 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis @@ -195,11 +196,9 @@ system.membus.trans_dist::ReadExReq 77 # Tr system.membus.trans_dist::ReadExResp 77 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -478,12 +477,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 342 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) @@ -492,15 +491,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 463250 # La system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits @@ -576,17 +575,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -704,15 +703,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index f38f31bd7..0aa71b968 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90736 # Simulator instruction rate (inst/s) -host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 477859669 # Simulator tick rate (ticks/s) -host_mem_usage 289160 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 186481 # Simulator instruction rate (inst/s) +host_op_rate 337520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 981039317 # Simulator tick rate (ticks/s) +host_mem_usage 241472 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 79 # Tr system.membus.trans_dist::ReadExResp 79 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 23104 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -69,15 +67,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -147,17 +145,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -272,15 +270,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -375,12 +373,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 283 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 099eda912..d195e9d48 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24404000 # Number of ticks simulated final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52847 # Simulator instruction rate (inst/s) -host_op_rate 52845 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101181200 # Simulator tick rate (ticks/s) -host_mem_usage 228064 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 780 # Simulator instruction rate (inst/s) +host_op_rate 780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1494307 # Simulator tick rate (ticks/s) +host_mem_usage 227936 # Number of bytes of host memory used +host_seconds 16.33 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1636453040 # In system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 62336 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis @@ -205,10 +206,10 @@ system.membus.trans_dist::ReadReq 828 # Tr system.membus.trans_dist::ReadResp 828 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 62336 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) @@ -452,41 +453,7 @@ system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Ty system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::total 10798 # Type of FU issued -system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued -system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued -system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21796 # Type of FU issued +system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued system.cpu.iq.rate 0.446557 # Inst issue rate system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested @@ -662,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 830 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) @@ -676,17 +643,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 1029500 # La system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements::0 6 # number of replacements -system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements::0 6 # number of replacements +system.cpu.icache.tags.replacements::1 0 # number of replacements +system.cpu.icache.tags.replacements::total 6 # number of replacements +system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits @@ -762,19 +729,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements::0 0 # number of replacements -system.cpu.l2cache.tags.replacements::1 0 # number of replacements -system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements::0 0 # number of replacements +system.cpu.l2cache.tags.replacements::1 0 # number of replacements +system.cpu.l2cache.tags.replacements::total 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009464 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -889,17 +856,17 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements::0 0 # number of replacements -system.cpu.dcache.tags.replacements::1 0 # number of replacements -system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements::0 0 # number of replacements +system.cpu.dcache.tags.replacements::1 0 # number of replacements +system.cpu.dcache.tags.replacements::total 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 60e6f3a9f..0c812fe4f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 27282000 # Number of ticks simulated final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50184 # Simulator instruction rate (inst/s) -host_op_rate 50180 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90285398 # Simulator tick rate (ticks/s) -host_mem_usage 232468 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 96636 # Simulator instruction rate (inst/s) +host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173854426 # Simulator tick rate (ticks/s) +host_mem_usage 231852 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 699068983 # In system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 27904 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis @@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 351 # Tr system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 871 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) @@ -275,15 +276,15 @@ system.cpu.stage3.utilization 5.274443 # Pe system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 354 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) @@ -378,17 +379,17 @@ system.cpu.toL2Bus.respLayer0.occupancy 507000 # La system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -503,15 +504,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 5128d5dc2..46cdc1496 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26524500 # Number of ticks simulated final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52714 # Simulator instruction rate (inst/s) -host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96835127 # Simulator tick rate (ticks/s) -host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 95044 # Simulator instruction rate (inst/s) +host_op_rate 95035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174603061 # Simulator tick rate (ticks/s) +host_mem_usage 232868 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 808309299 # In system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 30848 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis @@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 399 # Tr system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 964 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) @@ -472,12 +473,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 401 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) @@ -486,15 +487,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 570000 # La system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits @@ -570,17 +571,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -695,15 +696,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index ac8c29d55..45bd7d946 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 479032 # Simulator instruction rate (inst/s) -host_op_rate 478642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1304958787 # Simulator tick rate (ticks/s) -host_mem_usage 231320 # Number of bytes of host memory used +host_inst_rate 554996 # Simulator instruction rate (inst/s) +host_op_rate 554737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1512828488 # Simulator tick rate (ticks/s) +host_mem_usage 230824 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 331 # Tr system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 832 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -375,12 +375,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 333 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index aa46bcce7..53e641a1b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 110804500 # Number of ticks simulated final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110530 # Simulator instruction rate (inst/s) -host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11745373 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 9.43 # Real time elapsed on the host +host_inst_rate 170931 # Simulator instruction rate (inst/s) +host_op_rate 170931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18163832 # Simulator tick rate (ticks/s) +host_mem_usage 247816 # Number of bytes of host memory used +host_seconds 6.10 # Real time elapsed on the host sim_insts 1042724 # Number of instructions simulated sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -57,14 +57,15 @@ system.physmem.bw_total::cpu2.data 11551877 # To system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis @@ -229,16 +230,421 @@ system.membus.trans_dist::UpgradeReq 287 # Tr system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use +system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # 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number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution @@ -247,24 +653,24 @@ system.toL2Bus.trans_dist::UpgradeReq 290 # Tr system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) @@ -548,15 +954,15 @@ system.cpu0.int_regfile_writes 325227 # nu system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits @@ -632,15 +1038,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits @@ -1025,15 +1431,15 @@ system.cpu1.int_regfile_writes 148477 # nu system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits @@ -1109,15 +1515,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits @@ -1500,15 +1906,15 @@ system.cpu2.int_regfile_writes 188531 # nu system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits @@ -1584,15 +1990,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits @@ -1975,15 +2381,15 @@ system.cpu3.int_regfile_writes 211087 # nu system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits @@ -2059,15 +2465,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits @@ -2185,410 +2591,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 229 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 349 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 421 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 543 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 674 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 359 # number of overall misses -system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 16 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 76 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 428 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 4a2827ac8..8ba84a629 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146225 # Simulator instruction rate (inst/s) -host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57909206 # Simulator tick rate (ticks/s) -host_mem_usage 244388 # Number of bytes of host memory used -host_seconds 4.54 # Real time elapsed on the host +host_inst_rate 681070 # Simulator instruction rate (inst/s) +host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 269712940 # Simulator tick rate (ticks/s) +host_mem_usage 243700 # Number of bytes of host memory used +host_seconds 0.97 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -64,16 +64,424 @@ system.membus.trans_dist::UpgradeReq 272 # Tr system.membus.trans_dist::UpgradeResp 77 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution @@ -82,24 +490,24 @@ system.toL2Bus.trans_dist::UpgradeReq 274 # Tr system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) @@ -143,15 +551,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -221,15 +629,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -363,15 +771,15 @@ system.cpu1.num_idle_cycles 69347.869793 # Nu system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits @@ -441,15 +849,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits @@ -581,15 +989,15 @@ system.cpu2.num_idle_cycles 69604.869303 # Nu system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits @@ -659,15 +1067,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits @@ -799,15 +1207,15 @@ system.cpu3.num_idle_cycles 69869.868798 # Nu system.cpu3.num_busy_cycles 455718.131202 # Number of busy cycles system.cpu3.not_idle_fraction 0.867063 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.132937 # Percentage of idle cycles -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 65.598437 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits @@ -877,15 +1285,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits @@ -995,413 +1403,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 182 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 0a30250cf..6f84c5ba1 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000653 # Nu sim_ticks 652606500 # Number of ticks simulated final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 176079756 # Simulator tick rate (ticks/s) -host_mem_usage 355636 # Number of bytes of host memory used -host_seconds 3.71 # Real time elapsed on the host +host_tick_rate 158104978 # Simulator tick rate (ticks/s) +host_mem_usage 355504 # Number of bytes of host memory used +host_seconds 4.13 # Real time elapsed on the host system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory @@ -84,41 +84,41 @@ system.membus.trans_dist::UpgradeReq 57414 # Tr system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution system.membus.trans_dist::ReadExReq 48586 # Transaction distribution system.membus.trans_dist::ReadExResp 3092 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1086481 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 47.7 # Layer utilization (%) -system.l2c.tags.replacements 13254 # number of replacements -system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use -system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy +system.l2c.tags.replacements 13254 # number of replacements +system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use +system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits @@ -690,24 +690,24 @@ system.toL2Bus.trans_dist::UpgradeReq 28719 # Tr system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 13912273 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks) @@ -731,15 +731,15 @@ system.toL2Bus.respLayer7.utilization 24.2 # La system.cpu0.num_reads 98977 # number of read accesses completed system.cpu0.num_writes 53590 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.tags.replacements 21970 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. -system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.replacements 21970 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. +system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits @@ -846,15 +846,15 @@ system.cpu0.l1c.no_allocate_misses 0 # Nu system.cpu1.num_reads 99824 # number of read accesses completed system.cpu1.num_writes 53636 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.tags.replacements 22223 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. -system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.replacements 22223 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. +system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits @@ -961,15 +961,15 @@ system.cpu1.l1c.no_allocate_misses 0 # Nu system.cpu2.num_reads 99336 # number of read accesses completed system.cpu2.num_writes 53403 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.tags.replacements 22214 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. -system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.replacements 22214 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. +system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits @@ -1076,15 +1076,15 @@ system.cpu2.l1c.no_allocate_misses 0 # Nu system.cpu3.num_reads 100000 # number of read accesses completed system.cpu3.num_writes 53536 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.tags.replacements 22464 # number of replacements -system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. -system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.replacements 22464 # number of replacements +system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. +system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits @@ -1191,15 +1191,15 @@ system.cpu3.l1c.no_allocate_misses 0 # Nu system.cpu4.num_reads 99830 # number of read accesses completed system.cpu4.num_writes 54064 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.tags.replacements 22082 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. -system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.replacements 22082 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. +system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits @@ -1306,15 +1306,15 @@ system.cpu4.l1c.no_allocate_misses 0 # Nu system.cpu5.num_reads 99630 # number of read accesses completed system.cpu5.num_writes 53500 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.tags.replacements 22051 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. -system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.replacements 22051 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. +system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits @@ -1421,15 +1421,15 @@ system.cpu5.l1c.no_allocate_misses 0 # Nu system.cpu6.num_reads 99897 # number of read accesses completed system.cpu6.num_writes 53584 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.tags.replacements 22385 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. -system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.replacements 22385 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. +system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits @@ -1536,15 +1536,15 @@ system.cpu6.l1c.no_allocate_misses 0 # Nu system.cpu7.num_reads 99207 # number of read accesses completed system.cpu7.num_writes 53401 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.tags.replacements 22143 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. -system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.replacements 22143 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. +system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index ff9167bb3..4e4b75a44 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 29067628326 # Simulator tick rate (ticks/s) -host_mem_usage 231288 # Number of bytes of host memory used -host_seconds 3.44 # Real time elapsed on the host +host_tick_rate 12102739985 # Simulator tick rate (ticks/s) +host_mem_usage 228608 # Number of bytes of host memory used +host_seconds 8.26 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -15,14 +15,15 @@ system.physmem.bw_read::cpu 2133311360 # To system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 213331136 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis @@ -169,18 +170,15 @@ system.physmem.avgGap 30000.29 # Av system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution -system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) system.membus.respLayer0.utilization 17.2 # Layer utilization (%) -system.cpu.numPackets 3333300 # Number of packets generated -system.cpu.numRetries 0 # Number of retries -system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -519,5 +517,8 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period +system.cpu.numPackets 3333300 # Number of packets generated +system.cpu.numRetries 0 # Number of retries +system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index 4db87dea6..14b3c1d80 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 14083896029 # Simulator tick rate (ticks/s) -host_mem_usage 231304 # Number of bytes of host memory used -host_seconds 7.10 # Real time elapsed on the host +host_tick_rate 8032030639 # Simulator tick rate (ticks/s) +host_mem_usage 228596 # Number of bytes of host memory used +host_seconds 12.45 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory @@ -26,18 +26,15 @@ system.membus.trans_dist::ReadReq 1 # Tr system.membus.trans_dist::ReadResp 1 # Transaction distribution system.membus.trans_dist::WriteReq 3333268 # Transaction distribution system.membus.trans_dist::WriteResp 3333267 # Transaction distribution -system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 213329216 # Total data (bytes) system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 16.7 # Layer utilization (%) system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.cpu.numPackets 3333269 # Number of packets generated -system.cpu.numRetries 1 # Number of retries -system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -376,5 +373,8 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period +system.cpu.numPackets 3333269 # Number of packets generated +system.cpu.numRetries 1 # Number of retries +system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ---------- |