summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
commitc3bf29bbeabdd3510a2e3c81c653c2931ad26e64 (patch)
treee3e1127150c71a880712e202690e185ddc201c5e
parentf3e65c2de285d185936674375a353d71e547d2eb (diff)
downloadgem5-c3bf29bbeabdd3510a2e3c81c653c2931ad26e64.tar.xz
ARM: Implement the udiv instruction.
-rw-r--r--src/arch/arm/isa/formats/mult.isa2
-rw-r--r--src/arch/arm/isa/insts/div.isa14
2 files changed, 15 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index 8b3720e49..cfd00b1a5 100644
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -303,7 +303,7 @@ def format Thumb32LongMulMulAccAndDiv() {{
break;
case 0x3:
if (op2 == 0xf) {
- return new WarnUnimplemented("udiv", machInst);
+ return new Udiv(machInst, rdhi, rn, rm);
}
break;
case 0x4:
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index b3bd19cdb..b240e2967 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -53,4 +53,18 @@ let {{
header_output = RegRegRegOpDeclare.subst(sdivIop)
decoder_output = RegRegRegOpConstructor.subst(sdivIop)
exec_output = PredOpExecute.subst(sdivIop)
+
+ udivCode = '''
+ if (Op2.uw == 0) {
+ Dest.uw = 0;
+ } else {
+ Dest.uw = Op1.uw / Op2.uw;
+ }
+ '''
+ udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
+ { "code": udivCode,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegRegOpDeclare.subst(udivIop)
+ decoder_output += RegRegRegOpConstructor.subst(udivIop)
+ exec_output += PredOpExecute.subst(udivIop)
}};